[llvm-commits] [llvm] r78994 - in /llvm/trunk/lib/Target/ARM: ARMISelLowering.cpp ARMISelLowering.h ARMInstrNEON.td
Bob Wilson
bob.wilson at apple.com
Thu Aug 13 22:13:08 PDT 2009
Author: bwilson
Date: Fri Aug 14 00:13:08 2009
New Revision: 78994
URL: http://llvm.org/viewvc/llvm-project?rev=78994&view=rev
Log:
Create a new ARM-specific DAG node, VDUP, to represent a splat from a
scalar_to_vector. Generate these VDUP nodes during legalization instead
of trying to recognize the pattern during selection.
Modified:
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.h
llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=78994&r1=78993&r2=78994&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Aug 14 00:13:08 2009
@@ -477,6 +477,7 @@
case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
+ case ARMISD::VDUP: return "ARMISD::VDUP";
case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
case ARMISD::VLD2D: return "ARMISD::VLD2D";
case ARMISD::VLD3D: return "ARMISD::VLD3D";
@@ -2449,9 +2450,12 @@
// of the same time so that they get CSEd properly.
if (SVN->isSplat()) {
int Lane = SVN->getSplatIndex();
- if (Lane != 0)
- return DAG.getNode(ARMISD::VDUPLANE, dl, VT, SVN->getOperand(0),
- DAG.getConstant(Lane, MVT::i32));
+ SDValue Op0 = SVN->getOperand(0);
+ if (Lane == 0 && Op0.getOpcode() == ISD::SCALAR_TO_VECTOR) {
+ return DAG.getNode(ARMISD::VDUP, dl, VT, Op0.getOperand(0));
+ }
+ return DAG.getNode(ARMISD::VDUPLANE, dl, VT, SVN->getOperand(0),
+ DAG.getConstant(Lane, MVT::i32));
}
if (isVREVMask(SVN, 64))
return DAG.getNode(ARMISD::VREV64, dl, VT, SVN->getOperand(0));
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=78994&r1=78993&r2=78994&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Fri Aug 14 00:13:08 2009
@@ -115,7 +115,8 @@
VGETLANEu, // zero-extend vector extract element
VGETLANEs, // sign-extend vector extract element
- // Vector duplicate lane:
+ // Vector duplicate:
+ VDUP,
VDUPLANE,
// Vector load/store with (de)interleaving
Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=78994&r1=78993&r2=78994&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Aug 14 00:13:08 2009
@@ -65,6 +65,8 @@
def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
+def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
+
// VDUPLANE can produce a quad-register result from a double-register source,
// so the result is not constrained to match the source.
def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
@@ -1747,20 +1749,14 @@
// VDUP : Vector Duplicate (from ARM core register to all elements)
-def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
- (vector_shuffle node:$lhs, node:$rhs), [{
- ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
- return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
-}]>;
-
class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
: NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
- [(set DPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
+ [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
: NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
- [(set QPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
+ [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
@@ -1771,16 +1767,12 @@
def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
NoItinerary, "vdup", ".32\t$dst, $src",
- [(set DPR:$dst, (v2f32 (splat_lo
- (scalar_to_vector
- (f32 (bitconvert GPR:$src))),
- undef)))]>;
+ [(set DPR:$dst, (v2f32 (NEONvdup
+ (f32 (bitconvert GPR:$src)))))]>;
def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
NoItinerary, "vdup", ".32\t$dst, $src",
- [(set QPR:$dst, (v4f32 (splat_lo
- (scalar_to_vector
- (f32 (bitconvert GPR:$src))),
- undef)))]>;
+ [(set QPR:$dst, (v4f32 (NEONvdup
+ (f32 (bitconvert GPR:$src)))))]>;
// VDUP : Vector Duplicate Lane (from scalar to all elements)
@@ -1826,16 +1818,12 @@
def VDUPfdf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 0, 0,
(outs DPR:$dst), (ins SPR:$src),
NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
- [(set DPR:$dst, (v2f32 (splat_lo
- (scalar_to_vector SPR:$src),
- undef)))]>;
+ [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
def VDUPfqf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 1, 0,
(outs QPR:$dst), (ins SPR:$src),
NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
- [(set QPR:$dst, (v4f32 (splat_lo
- (scalar_to_vector SPR:$src),
- undef)))]>;
+ [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
// VMOVN : Vector Narrowing Move
defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i",
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