[llvm-commits] [llvm] r78701 - in /llvm/trunk/lib/Target/ARM: ARMBaseInstrInfo.cpp ARMInstrThumb2.td

[Evan Cheng]

On Aug 11, 2009, at 12:42 PM, Jim Grosbach wrote:

> Author: grosbach
> Date: Tue Aug 11 14:42:21 2009
> New Revision: 78701
>
> URL: http://llvm.org/viewvc/llvm-project?rev=78701&view=rev
> Log:
> Add Thumb2 eh_sjlj_setjmp implementation
>
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
>    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
>
> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=78701&r1=78700&r2=78701&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Aug 11  
> 14:42:21 2009
> @@ -441,6 +441,8 @@
>       return MI->getOperand(2).getImm();
>     case ARM::Int_eh_sjlj_setjmp:
>       return 24;
> +    case ARM::t2Int_eh_sjlj_setjmp:
> +      return 20;
>     case ARM::BR_JTr:
>     case ARM::BR_JTm:
>     case ARM::BR_JTadd:
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=78701&r1=78700&r2=78701&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Aug 11 14:42:21  
> 2009
> @@ -1064,6 +1064,38 @@
> }
>
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
> +// SJLJ Exception handling intrinsics
> +//   eh_sjlj_setjmp() is a three instruction sequence to store the  
> return

3 instructions?

> +//   address and save #0 in R0 for the non-longjmp case.
> +//   Since by its nature we may be coming from some other function  
> to get
> +//   here, and we're using the stack frame for the containing  
> function to
> +//   save/restore registers, we can't keep anything live in regs  
> across
> +//   the eh_sjlj_setjmp(), else it will almost certainly have been  
> tromped upon
> +//   when we get here from a longjmp(). We force everthing out of  
> registers
> +//   except for our own input by listing the relevant registers in  
> Defs. By
> +//   doing so, we also cause the prologue/epilogue code to actively  
> preserve
> +//   all of the callee-saved resgisters, which is exactly what we  
> want.
> +let Defs =
> +  [ R0,  R1,  R3,  R4,  R5,  R6,  R7,  R8,  R9,  R10, R11, R12, LR,
> +    D0,  D2,  D3,  D4,  D5,  D6,  D7,  D8,  D9,  D10, D11, D12,  
> D13, D14, D15,
> +    D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27,  
> D28, D29, D30,
> +    D31 ] in {
> +  def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins GPR:$src),
> +                               AddrModeNone, SizeSpecial,  
> NoItinerary,
> +                               "str.w sp, [$src, #+8] @ eh_setjmp  
> begin\n"
> +                               "\tadr ip, 0f\n"
> +                               "\torr ip, #1\n"
> +                               "\tstr.w ip, [$src, #+4]\n"
> +                               "\tmovs r0, #0\n"
> +                               "\tb 1f\n"
> +                               "0:\tmovs r0, #1 @ eh_setjmp end\n"
> +                               "1:\n", "",
> +                               [(set R0, (ARMeh_sjlj_setjmp GPR: 
> $src))]>;

More questions. What do "0f" "1f" mean?  Can we generate multiple  
labels like 0: 1: in the same function? Can there be multiple  
Int_eh_sjlj_setjmp in a function? Does it make sense to add a id  
operand to the instruction so we can print out unique labels?

One more thing. The '\n' after '1:' is not needed.

Evan

> +}
> +
> +
> +
> +// 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
> // Control-Flow Instructions
> //
>
>
>
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