[llvm-commits] [llvm] r78761 - in /llvm/trunk/lib/Target/ARM: ARMISelDAGToDAG.cpp ARMInstrNEON.td
Bob Wilson
bob.wilson at apple.com
Wed Aug 12 10:04:18 PDT 2009
Sorry for missing the warnings. Fixed in r78815.
On Aug 11, 2009, at 10:15 PM, Evan Cheng wrote:
> Hi Bob,
>
> If the instruction has a matching pattern, it's not necessary to add
> mayLoad / mayStore. This patch is causing these tablegen warnings:
> Warning: mayLoad flag explicitly set on instruction 'VLD1d16' but flag
> already inferred from pattern.
> Warning: mayLoad flag explicitly set on instruction 'VLD1d32' but flag
> already inferred from pattern.
>
> Evan
>
> On Aug 11, 2009, at 5:49 PM, Bob Wilson wrote:
>
>> Author: bwilson
>> Date: Tue Aug 11 19:49:01 2009
>> New Revision: 78761
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=78761&view=rev
>> Log:
>> Add missing chain operands for VLD* and VST* instructions.
>> Set "mayLoad" and "mayStore" on the load/store instructions.
>>
>> Modified:
>> llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
>> llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=78761&r1=78760&r2=78761&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Aug 11
>> 19:49:01 2009
>> @@ -1357,8 +1357,9 @@
>> case MVT::v2f32:
>> case MVT::v2i32: Opc = ARM::VLD2d32; break;
>> }
>> - const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
>> - return CurDAG->getTargetNode(Opc, dl, VT, VT, MVT::Other, Ops,
>> 3);
>> + SDValue Chain = N->getOperand(0);
>> + const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
>> + return CurDAG->getTargetNode(Opc, dl, VT, VT, MVT::Other, Ops,
>> 4);
>> }
>>
>> case ARMISD::VLD3D: {
>> @@ -1374,8 +1375,9 @@
>> case MVT::v2f32:
>> case MVT::v2i32: Opc = ARM::VLD3d32; break;
>> }
>> - const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
>> - return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, MVT::Other,
>> Ops, 3);
>> + SDValue Chain = N->getOperand(0);
>> + const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
>> + return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, MVT::Other,
>> Ops, 4);
>> }
>>
>> case ARMISD::VLD4D: {
>> @@ -1391,10 +1393,11 @@
>> case MVT::v2f32:
>> case MVT::v2i32: Opc = ARM::VLD4d32; break;
>> }
>> - const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
>> + SDValue Chain = N->getOperand(0);
>> + const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
>> std::vector<EVT> ResTys(4, VT);
>> ResTys.push_back(MVT::Other);
>> - return CurDAG->getTargetNode(Opc, dl, ResTys, Ops, 3);
>> + return CurDAG->getTargetNode(Opc, dl, ResTys, Ops, 4);
>> }
>>
>> case ARMISD::VST2D: {
>> @@ -1409,9 +1412,10 @@
>> case MVT::v2f32:
>> case MVT::v2i32: Opc = ARM::VST2d32; break;
>> }
>> + SDValue Chain = N->getOperand(0);
>> const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
>> - N->getOperand(2), N->getOperand(3) };
>> - return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 5);
>> + N->getOperand(2), N->getOperand(3),
>> Chain };
>> + return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 6);
>> }
>>
>> case ARMISD::VST3D: {
>> @@ -1426,10 +1430,11 @@
>> case MVT::v2f32:
>> case MVT::v2i32: Opc = ARM::VST3d32; break;
>> }
>> + SDValue Chain = N->getOperand(0);
>> const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
>> N->getOperand(2), N->getOperand(3),
>> - N->getOperand(4) };
>> - return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 6);
>> + N->getOperand(4), Chain };
>> + return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7);
>> }
>>
>> case ARMISD::VST4D: {
>> @@ -1444,10 +1449,11 @@
>> case MVT::v2f32:
>> case MVT::v2i32: Opc = ARM::VST4d32; break;
>> }
>> + SDValue Chain = N->getOperand(0);
>> const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
>> N->getOperand(2), N->getOperand(3),
>> - N->getOperand(4), N->getOperand(5) };
>> - return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7);
>> + N->getOperand(4), N->getOperand(5),
>> Chain };
>> + return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 8);
>> }
>>
>> case ISD::INTRINSIC_WO_CHAIN: {
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=78761&r1=78760&r2=78761&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Aug 11 19:49:01
>> 2009
>> @@ -113,8 +113,8 @@
>> // NEON load / store instructions
>> //
>> =
>> =
>> =
>> ----------------------------------------------------------------------=
>> ==//
>>
>> -/* TODO: Take advantage of vldm.
>> let mayLoad = 1 in {
>> +/* TODO: Take advantage of vldm.
>> def VLDMD : NI<(outs),
>> (ins addrmode_neonldstm:$addr, reglist:$dst1,
>> variable_ops),
>> NoItinerary,
>> @@ -134,7 +134,6 @@
>> let Inst{20} = 1;
>> let Inst{11-9} = 0b101;
>> }
>> -}
>> */
>>
>> // Use vldmia to load a Q register as a D register pair.
>> @@ -149,18 +148,6 @@
>> let Inst{11-9} = 0b101;
>> }
>>
>> -// Use vstmia to store a Q register as a D register pair.
>> -def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
>> - NoItinerary,
>> - "vstmia $addr, ${src:dregpair}",
>> - [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
>> - let Inst{27-25} = 0b110;
>> - let Inst{24} = 0; // P bit
>> - let Inst{23} = 1; // U bit
>> - let Inst{20} = 0;
>> - let Inst{11-9} = 0b101;
>> -}
>> -
>> // VLD1 : Vector Load (multiple single elements)
>> class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
>> : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr),
>> @@ -215,6 +202,20 @@
>> def VLD4d8 : VLD4D<"vld4.8">;
>> def VLD4d16 : VLD4D<"vld4.16">;
>> def VLD4d32 : VLD4D<"vld4.32">;
>> +}
>> +
>> +let mayStore = 1 in {
>> +// Use vstmia to store a Q register as a D register pair.
>> +def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
>> + NoItinerary,
>> + "vstmia $addr, ${src:dregpair}",
>> + [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
>> + let Inst{27-25} = 0b110;
>> + let Inst{24} = 0; // P bit
>> + let Inst{23} = 1; // U bit
>> + let Inst{20} = 0;
>> + let Inst{11-9} = 0b101;
>> +}
>>
>> // VST1 : Vector Store (multiple single elements)
>> class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
>> @@ -268,6 +269,7 @@
>> def VST4d8 : VST4D<"vst4.8">;
>> def VST4d16 : VST4D<"vst4.16">;
>> def VST4d32 : VST4D<"vst4.32">;
>> +}
>>
>>
>> //
>> =
>> =
>> =
>> ----------------------------------------------------------------------=
>> ==//
>>
>>
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