[llvm-commits] [llvm] r78815 - /llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
Bob Wilson
bob.wilson at apple.com
Wed Aug 12 10:04:56 PDT 2009
Author: bwilson
Date: Wed Aug 12 12:04:56 2009
New Revision: 78815
URL: http://llvm.org/viewvc/llvm-project?rev=78815&view=rev
Log:
Fix TableGen warnings. This partly reverts my previous change to this file,
leaving the mayLoad and mayStore settings around only the load/store
instructions where those can't be inferred from the patterns.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=78815&r1=78814&r2=78815&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Aug 12 12:04:56 2009
@@ -113,8 +113,8 @@
// NEON load / store instructions
//===----------------------------------------------------------------------===//
-let mayLoad = 1 in {
/* TODO: Take advantage of vldm.
+let mayLoad = 1 in {
def VLDMD : NI<(outs),
(ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
NoItinerary,
@@ -134,6 +134,7 @@
let Inst{20} = 1;
let Inst{11-9} = 0b101;
}
+}
*/
// Use vldmia to load a Q register as a D register pair.
@@ -148,6 +149,18 @@
let Inst{11-9} = 0b101;
}
+// Use vstmia to store a Q register as a D register pair.
+def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
+ NoItinerary,
+ "vstmia $addr, ${src:dregpair}",
+ [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
+ let Inst{27-25} = 0b110;
+ let Inst{24} = 0; // P bit
+ let Inst{23} = 1; // U bit
+ let Inst{20} = 0;
+ let Inst{11-9} = 0b101;
+}
+
// VLD1 : Vector Load (multiple single elements)
class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
: NLdSt<(outs DPR:$dst), (ins addrmode6:$addr),
@@ -172,6 +185,8 @@
def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vld1>;
def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1>;
+let mayLoad = 1 in {
+
// VLD2 : Vector Load (multiple 2-element structures)
class VLD2D<string OpcodeStr>
: NLdSt<(outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr),
@@ -204,19 +219,6 @@
def VLD4d32 : VLD4D<"vld4.32">;
}
-let mayStore = 1 in {
-// Use vstmia to store a Q register as a D register pair.
-def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
- NoItinerary,
- "vstmia $addr, ${src:dregpair}",
- [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
- let Inst{27-25} = 0b110;
- let Inst{24} = 0; // P bit
- let Inst{23} = 1; // U bit
- let Inst{20} = 0;
- let Inst{11-9} = 0b101;
-}
-
// VST1 : Vector Store (multiple single elements)
class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
: NLdSt<(outs), (ins addrmode6:$addr, DPR:$src),
@@ -241,6 +243,8 @@
def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1>;
def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1>;
+let mayStore = 1 in {
+
// VST2 : Vector Store (multiple 2-element structures)
class VST2D<string OpcodeStr>
: NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2), NoItinerary,
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