[llvm-commits] [llvm] r78713 [1/2] - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PIC16/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/X86/AsmPrinter/ lib/Target/XCore/ lib/VMCore/ utils/TableGen/
Owen Anderson
resistor at mac.com
Tue Aug 11 13:47:23 PDT 2009
Author: resistor
Date: Tue Aug 11 15:47:22 2009
New Revision: 78713
URL: http://llvm.org/viewvc/llvm-project?rev=78713&view=rev
Log:
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.
Modified:
llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h
llvm/trunk/include/llvm/CodeGen/FastISel.h
llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
llvm/trunk/include/llvm/CodeGen/ValueTypes.h
llvm/trunk/include/llvm/Target/TargetLowering.h
llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.h
llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h
llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp
llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp
llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.h
llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.td
llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp
llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h
llvm/trunk/lib/Target/CellSPU/SPUOperands.td
llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
llvm/trunk/lib/Target/Mips/MipsISelLowering.h
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h
llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp
llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/trunk/lib/Target/SystemZ/SystemZOperands.td
llvm/trunk/lib/Target/TargetRegisterInfo.cpp
llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
llvm/trunk/lib/Target/X86/X86FastISel.cpp
llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.h
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp
llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
llvm/trunk/lib/VMCore/ValueTypes.cpp
llvm/trunk/lib/VMCore/Verifier.cpp
llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h
llvm/trunk/utils/TableGen/CodeGenIntrinsics.h
llvm/trunk/utils/TableGen/CodeGenRegisters.h
llvm/trunk/utils/TableGen/CodeGenTarget.cpp
llvm/trunk/utils/TableGen/CodeGenTarget.h
llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
llvm/trunk/utils/TableGen/FastISelEmitter.cpp
llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp
llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
Modified: llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h (original)
+++ llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h Tue Aug 11 15:47:22 2009
@@ -35,7 +35,7 @@
return false;
if (Chain->getNumOperands() > 0) {
SDValue C0 = Chain->getOperand(0);
- if (C0.getValueType() == EVT::Other)
+ if (C0.getValueType() == MVT::Other)
return C0.getNode() != Op && IsChainCompatible(C0.getNode(), Op);
}
return true;
Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/FastISel.h Tue Aug 11 15:47:22 2009
@@ -137,24 +137,24 @@
/// FastEmit_r - This method is called by target-independent code
/// to request that an instruction with the given type and opcode
/// be emitted.
- virtual unsigned FastEmit_(EVT::SimpleValueType VT,
- EVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_(MVT VT,
+ MVT RetVT,
ISD::NodeType Opcode);
/// FastEmit_r - This method is called by target-independent code
/// to request that an instruction with the given type, opcode, and
/// register operand be emitted.
///
- virtual unsigned FastEmit_r(EVT::SimpleValueType VT,
- EVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_r(MVT VT,
+ MVT RetVT,
ISD::NodeType Opcode, unsigned Op0);
/// FastEmit_rr - This method is called by target-independent code
/// to request that an instruction with the given type, opcode, and
/// register operands be emitted.
///
- virtual unsigned FastEmit_rr(EVT::SimpleValueType VT,
- EVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_rr(MVT VT,
+ MVT RetVT,
ISD::NodeType Opcode,
unsigned Op0, unsigned Op1);
@@ -162,8 +162,8 @@
/// to request that an instruction with the given type, opcode, and
/// register and immediate operands be emitted.
///
- virtual unsigned FastEmit_ri(EVT::SimpleValueType VT,
- EVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_ri(MVT VT,
+ MVT RetVT,
ISD::NodeType Opcode,
unsigned Op0, uint64_t Imm);
@@ -171,8 +171,8 @@
/// to request that an instruction with the given type, opcode, and
/// register and floating-point immediate operands be emitted.
///
- virtual unsigned FastEmit_rf(EVT::SimpleValueType VT,
- EVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_rf(MVT VT,
+ MVT RetVT,
ISD::NodeType Opcode,
unsigned Op0, ConstantFP *FPImm);
@@ -180,8 +180,8 @@
/// to request that an instruction with the given type, opcode, and
/// register and immediate operands be emitted.
///
- virtual unsigned FastEmit_rri(EVT::SimpleValueType VT,
- EVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_rri(MVT VT,
+ MVT RetVT,
ISD::NodeType Opcode,
unsigned Op0, unsigned Op1, uint64_t Imm);
@@ -189,33 +189,33 @@
/// to emit an instruction with an immediate operand using FastEmit_ri.
/// If that fails, it materializes the immediate into a register and try
/// FastEmit_rr instead.
- unsigned FastEmit_ri_(EVT::SimpleValueType VT,
+ unsigned FastEmit_ri_(MVT VT,
ISD::NodeType Opcode,
unsigned Op0, uint64_t Imm,
- EVT::SimpleValueType ImmType);
+ MVT ImmType);
/// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
/// to emit an instruction with an immediate operand using FastEmit_rf.
/// If that fails, it materializes the immediate into a register and try
/// FastEmit_rr instead.
- unsigned FastEmit_rf_(EVT::SimpleValueType VT,
+ unsigned FastEmit_rf_(MVT VT,
ISD::NodeType Opcode,
unsigned Op0, ConstantFP *FPImm,
- EVT::SimpleValueType ImmType);
+ MVT ImmType);
/// FastEmit_i - This method is called by target-independent code
/// to request that an instruction with the given type, opcode, and
/// immediate operand be emitted.
- virtual unsigned FastEmit_i(EVT::SimpleValueType VT,
- EVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_i(MVT VT,
+ MVT RetVT,
ISD::NodeType Opcode,
uint64_t Imm);
/// FastEmit_f - This method is called by target-independent code
/// to request that an instruction with the given type, opcode, and
/// floating-point immediate operand be emitted.
- virtual unsigned FastEmit_f(EVT::SimpleValueType VT,
- EVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_f(MVT VT,
+ MVT RetVT,
ISD::NodeType Opcode,
ConstantFP *FPImm);
@@ -268,12 +268,12 @@
/// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
/// from a specified index of a superregister to a specified type.
- unsigned FastEmitInst_extractsubreg(EVT::SimpleValueType RetVT,
+ unsigned FastEmitInst_extractsubreg(MVT RetVT,
unsigned Op0, uint32_t Idx);
/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
/// with all but the least significant bit set to zero.
- unsigned FastEmitZExtFromI1(EVT::SimpleValueType VT,
+ unsigned FastEmitZExtFromI1(MVT VT,
unsigned Op);
/// FastEmitBranch - Emit an unconditional branch to the given block,
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Tue Aug 11 15:47:22 2009
@@ -193,7 +193,7 @@
/// setRoot - Set the current root tag of the SelectionDAG.
///
const SDValue &setRoot(SDValue N) {
- assert((!N.getNode() || N.getValueType() == EVT::Other) &&
+ assert((!N.getNode() || N.getValueType() == MVT::Other) &&
"DAG root value is not a chain!");
return Root = N;
}
@@ -327,7 +327,7 @@
unsigned LabelID);
SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N) {
- return getNode(ISD::CopyToReg, dl, EVT::Other, Chain,
+ return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
getRegister(Reg, N.getValueType()), N);
}
@@ -336,7 +336,7 @@
// null) and that there should be a flag result.
SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N,
SDValue Flag) {
- SDVTList VTs = getVTList(EVT::Other, EVT::Flag);
+ SDVTList VTs = getVTList(MVT::Other, MVT::Flag);
SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Flag };
return getNode(ISD::CopyToReg, dl, VTs, Ops, Flag.getNode() ? 4 : 3);
}
@@ -344,13 +344,13 @@
// Similar to last getCopyToReg() except parameter Reg is a SDValue
SDValue getCopyToReg(SDValue Chain, DebugLoc dl, SDValue Reg, SDValue N,
SDValue Flag) {
- SDVTList VTs = getVTList(EVT::Other, EVT::Flag);
+ SDVTList VTs = getVTList(MVT::Other, MVT::Flag);
SDValue Ops[] = { Chain, Reg, N, Flag };
return getNode(ISD::CopyToReg, dl, VTs, Ops, Flag.getNode() ? 4 : 3);
}
SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, EVT VT) {
- SDVTList VTs = getVTList(VT, EVT::Other);
+ SDVTList VTs = getVTList(VT, MVT::Other);
SDValue Ops[] = { Chain, getRegister(Reg, VT) };
return getNode(ISD::CopyFromReg, dl, VTs, Ops, 2);
}
@@ -360,7 +360,7 @@
// null) and that there should be a flag result.
SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, EVT VT,
SDValue Flag) {
- SDVTList VTs = getVTList(VT, EVT::Other, EVT::Flag);
+ SDVTList VTs = getVTList(VT, MVT::Other, MVT::Flag);
SDValue Ops[] = { Chain, getRegister(Reg, VT), Flag };
return getNode(ISD::CopyFromReg, dl, VTs, Ops, Flag.getNode() ? 3 : 2);
}
@@ -391,7 +391,7 @@
/// a flag result (to ensure it's not CSE'd). CALLSEQ_START does not have a
/// useful DebugLoc.
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op) {
- SDVTList VTs = getVTList(EVT::Other, EVT::Flag);
+ SDVTList VTs = getVTList(MVT::Other, MVT::Flag);
SDValue Ops[] = { Chain, Op };
return getNode(ISD::CALLSEQ_START, DebugLoc::getUnknownLoc(),
VTs, Ops, 2);
@@ -402,7 +402,7 @@
/// a useful DebugLoc.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
SDValue InFlag) {
- SDVTList NodeTys = getVTList(EVT::Other, EVT::Flag);
+ SDVTList NodeTys = getVTList(MVT::Other, MVT::Flag);
SmallVector<SDValue, 4> Ops;
Ops.push_back(Chain);
Ops.push_back(Op1);
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Tue Aug 11 15:47:22 2009
@@ -1245,7 +1245,7 @@
/// to which the flag operand points. Otherwise return NULL.
SDNode *getFlaggedNode() const {
if (getNumOperands() != 0 &&
- getOperand(getNumOperands()-1).getValueType() == EVT::Flag)
+ getOperand(getNumOperands()-1).getValueType().getSimpleVT() == MVT::Flag)
return getOperand(getNumOperands()-1).getNode();
return 0;
}
@@ -1278,7 +1278,7 @@
return ValueList[ResNo];
}
- /// getValueSizeInBits - Returns EVT::getSizeInBits(getValueType(ResNo)).
+ /// getValueSizeInBits - Returns MVT::getSizeInBits(getValueType(ResNo)).
///
unsigned getValueSizeInBits(unsigned ResNo) const {
return getValueType(ResNo).getSizeInBits();
@@ -1505,7 +1505,7 @@
explicit HandleSDNode(SDValue X)
#endif
: SDNode(ISD::HANDLENODE, DebugLoc::getUnknownLoc(),
- getSDVTList(EVT::Other)) {
+ getSDVTList(MVT::Other)) {
InitOperands(&Op, X);
}
~HandleSDNode();
@@ -1914,7 +1914,7 @@
/// harder. Let's see if we need it first.
explicit BasicBlockSDNode(MachineBasicBlock *mbb)
: SDNode(ISD::BasicBlock, DebugLoc::getUnknownLoc(),
- getSDVTList(EVT::Other)), MBB(mbb) {
+ getSDVTList(MVT::Other)), MBB(mbb) {
}
public:
@@ -1965,7 +1965,7 @@
/// Create a SrcValue for a general value.
explicit SrcValueSDNode(const Value *v)
: SDNode(ISD::SRCVALUE, DebugLoc::getUnknownLoc(),
- getSDVTList(EVT::Other)), V(v) {}
+ getSDVTList(MVT::Other)), V(v) {}
public:
/// getValue - return the contained Value.
@@ -1987,7 +1987,7 @@
/// Create a MachineMemOperand node
explicit MemOperandSDNode(const MachineMemOperand &mo)
: SDNode(ISD::MEMOPERAND, DebugLoc::getUnknownLoc(),
- getSDVTList(EVT::Other)), MO(mo) {}
+ getSDVTList(MVT::Other)), MO(mo) {}
public:
/// MO - The contained MachineMemOperand.
@@ -2026,7 +2026,7 @@
DbgStopPointSDNode(SDValue ch, unsigned l, unsigned c,
Value *cu)
: SDNode(ISD::DBG_STOPPOINT, DebugLoc::getUnknownLoc(),
- getSDVTList(EVT::Other)), Line(l), Column(c), CU(cu) {
+ getSDVTList(MVT::Other)), Line(l), Column(c), CU(cu) {
InitOperands(&Chain, ch);
}
public:
@@ -2045,7 +2045,7 @@
unsigned LabelID;
friend class SelectionDAG;
LabelSDNode(unsigned NodeTy, DebugLoc dl, SDValue ch, unsigned id)
- : SDNode(NodeTy, dl, getSDVTList(EVT::Other)), LabelID(id) {
+ : SDNode(NodeTy, dl, getSDVTList(MVT::Other)), LabelID(id) {
InitOperands(&Chain, ch);
}
public:
@@ -2085,7 +2085,7 @@
friend class SelectionDAG;
explicit CondCodeSDNode(ISD::CondCode Cond)
: SDNode(ISD::CONDCODE, DebugLoc::getUnknownLoc(),
- getSDVTList(EVT::Other)), Condition(Cond) {
+ getSDVTList(MVT::Other)), Condition(Cond) {
}
public:
@@ -2210,7 +2210,7 @@
EVT VT;
bool Used;
- InputArg() : VT(EVT::Other), Used(false) {}
+ InputArg() : VT(MVT::Other), Used(false) {}
InputArg(ISD::ArgFlagsTy flags, EVT vt, bool used)
: Flags(flags), VT(vt), Used(used) {
assert(VT.isSimple() &&
@@ -2243,7 +2243,7 @@
friend class SelectionDAG;
explicit VTSDNode(EVT VT)
: SDNode(ISD::VALUETYPE, DebugLoc::getUnknownLoc(),
- getSDVTList(EVT::Other)), ValueType(VT) {
+ getSDVTList(MVT::Other)), ValueType(VT) {
}
public:
Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ValueTypes.h?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/ValueTypes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/ValueTypes.h Tue Aug 11 15:47:22 2009
@@ -24,9 +24,9 @@
namespace llvm {
class Type;
class LLVMContext;
+ struct EVT;
- struct EVT { // EVT = Machine Value Type
- public:
+ struct MVT { // MVT = Machine Value Type
enum SimpleValueType {
// If you change this numbering, you must change the values in
// ValueTypes.td as well!
@@ -113,131 +113,288 @@
LastSimpleValueType = 255
};
- private:
- /// This union holds low-level value types. Valid values include any of
- /// the values in the SimpleValueType enum, or any value returned from one
- /// of the EVT methods. Any value type equal to one of the SimpleValueType
- /// enum values is a "simple" value type. All others are "extended".
- ///
- /// Note that simple doesn't necessary mean legal for the target machine.
- /// All legal value types must be simple, but often there are some simple
- /// value types that are not legal.
- ///
- union {
- uintptr_t V;
- const Type *LLVMTy;
- };
-
- public:
- EVT() {}
- EVT(SimpleValueType S) : V(S) {}
+ SimpleValueType SimpleTy;
- bool operator==(const EVT VT) const {
- return getRawBits() == VT.getRawBits();
+ MVT() : SimpleTy((SimpleValueType)(LastSimpleValueType+1)) {}
+ MVT(SimpleValueType SVT) : SimpleTy(SVT) { }
+
+ bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
+ bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
+ bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
+ bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
+ bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }
+
+ /// isFloatingPoint - Return true if this is a FP, or a vector FP type.
+ bool isFloatingPoint() const {
+ return ((SimpleTy >= MVT::f32 && SimpleTy <= MVT::ppcf128) ||
+ (SimpleTy >= MVT::v2f32 && SimpleTy <= MVT::v4f64));
}
- bool operator!=(const EVT VT) const {
- return getRawBits() != VT.getRawBits();
+
+ /// isInteger - Return true if this is an integer, or a vector integer type.
+ bool isInteger() const {
+ return ((SimpleTy >= MVT::FIRST_INTEGER_VALUETYPE &&
+ SimpleTy <= MVT::LAST_INTEGER_VALUETYPE) ||
+ (SimpleTy >= MVT::v2i8 && SimpleTy <= MVT::v4i64));
}
- /// getFloatingPointVT - Returns the EVT that represents a floating point
- /// type with the given number of bits. There are two floating point types
- /// with 128 bits - this returns f128 rather than ppcf128.
- static EVT getFloatingPointVT(unsigned BitWidth) {
+ /// isVector - Return true if this is a vector value type.
+ bool isVector() const {
+ return (SimpleTy >= MVT::FIRST_VECTOR_VALUETYPE &&
+ SimpleTy <= MVT::LAST_VECTOR_VALUETYPE);
+ }
+
+ MVT getVectorElementType() const {
+ switch (SimpleTy) {
+ default:
+ return (MVT::SimpleValueType)(MVT::LastSimpleValueType+1);
+ case v2i8 :
+ case v4i8 :
+ case v8i8 :
+ case v16i8:
+ case v32i8: return i8;
+ case v2i16:
+ case v4i16:
+ case v8i16:
+ case v16i16: return i16;
+ case v2i32:
+ case v4i32:
+ case v8i32: return i32;
+ case v1i64:
+ case v2i64:
+ case v4i64: return i64;
+ case v2f32:
+ case v4f32:
+ case v8f32: return f32;
+ case v2f64:
+ case v4f64: return f64;
+ }
+ }
+
+ unsigned getVectorNumElements() const {
+ switch (SimpleTy) {
+ default:
+ return ~0U;
+ case v32i8: return 32;
+ case v16i8:
+ case v16i16: return 16;
+ case v8i8 :
+ case v8i16:
+ case v8i32:
+ case v8f32: return 8;
+ case v4i8:
+ case v4i16:
+ case v4i32:
+ case v4i64:
+ case v4f32:
+ case v4f64: return 4;
+ case v2i8:
+ case v2i16:
+ case v2i32:
+ case v2i64:
+ case v2f32:
+ case v2f64: return 2;
+ case v1i64: return 1;
+ }
+ }
+
+ unsigned getSizeInBits() const {
+ switch (SimpleTy) {
+ case iPTR:
+ assert(0 && "Value type size is target-dependent. Ask TLI.");
+ case iPTRAny:
+ case iAny:
+ case fAny:
+ assert(0 && "Value type is overloaded.");
+ default:
+ assert(0 && "getSizeInBits called on extended MVT.");
+ case i1 : return 1;
+ case i8 : return 8;
+ case i16 :
+ case v2i8: return 16;
+ case f32 :
+ case i32 :
+ case v4i8:
+ case v2i16: return 32;
+ case f64 :
+ case i64 :
+ case v8i8:
+ case v4i16:
+ case v2i32:
+ case v1i64:
+ case v2f32: return 64;
+ case f80 : return 80;
+ case f128:
+ case ppcf128:
+ case i128:
+ case v16i8:
+ case v8i16:
+ case v4i32:
+ case v2i64:
+ case v4f32:
+ case v2f64: return 128;
+ case v32i8:
+ case v16i16:
+ case v8i32:
+ case v4i64:
+ case v8f32:
+ case v4f64: return 256;
+ }
+ }
+
+ static MVT getFloatingPointVT(unsigned BitWidth) {
switch (BitWidth) {
default:
assert(false && "Bad bit width!");
case 32:
- return f32;
+ return MVT::f32;
case 64:
- return f64;
+ return MVT::f64;
case 80:
- return f80;
+ return MVT::f80;
case 128:
- return f128;
+ return MVT::f128;
}
}
-
- /// getIntegerVT - Returns the EVT that represents an integer with the given
- /// number of bits.
- static EVT getIntegerVT(unsigned BitWidth) {
+
+ static MVT getIntegerVT(unsigned BitWidth) {
switch (BitWidth) {
default:
- break;
+ return (MVT::SimpleValueType)(MVT::LastSimpleValueType+1);
case 1:
- return i1;
+ return MVT::i1;
case 8:
- return i8;
+ return MVT::i8;
case 16:
- return i16;
+ return MVT::i16;
case 32:
- return i32;
+ return MVT::i32;
case 64:
- return i64;
+ return MVT::i64;
case 128:
- return i128;
+ return MVT::i128;
}
- return getExtendedIntegerVT(BitWidth);
}
-
- /// getVectorVT - Returns the EVT that represents a vector NumElements in
- /// length, where each element is of type VT.
- static EVT getVectorVT(EVT VT, unsigned NumElements) {
- switch (VT.V) {
+
+ static MVT getVectorVT(MVT VT, unsigned NumElements) {
+ switch (VT.SimpleTy) {
default:
break;
- case i8:
- if (NumElements == 2) return v2i8;
- if (NumElements == 4) return v4i8;
- if (NumElements == 8) return v8i8;
- if (NumElements == 16) return v16i8;
- if (NumElements == 32) return v32i8;
+ case MVT::i8:
+ if (NumElements == 2) return MVT::v2i8;
+ if (NumElements == 4) return MVT::v4i8;
+ if (NumElements == 8) return MVT::v8i8;
+ if (NumElements == 16) return MVT::v16i8;
+ if (NumElements == 32) return MVT::v32i8;
break;
- case i16:
- if (NumElements == 2) return v2i16;
- if (NumElements == 4) return v4i16;
- if (NumElements == 8) return v8i16;
- if (NumElements == 16) return v16i16;
+ case MVT::i16:
+ if (NumElements == 2) return MVT::v2i16;
+ if (NumElements == 4) return MVT::v4i16;
+ if (NumElements == 8) return MVT::v8i16;
+ if (NumElements == 16) return MVT::v16i16;
break;
- case i32:
- if (NumElements == 2) return v2i32;
- if (NumElements == 4) return v4i32;
- if (NumElements == 8) return v8i32;
+ case MVT::i32:
+ if (NumElements == 2) return MVT::v2i32;
+ if (NumElements == 4) return MVT::v4i32;
+ if (NumElements == 8) return MVT::v8i32;
break;
- case i64:
- if (NumElements == 1) return v1i64;
- if (NumElements == 2) return v2i64;
- if (NumElements == 4) return v4i64;
+ case MVT::i64:
+ if (NumElements == 1) return MVT::v1i64;
+ if (NumElements == 2) return MVT::v2i64;
+ if (NumElements == 4) return MVT::v4i64;
break;
- case f32:
- if (NumElements == 2) return v2f32;
- if (NumElements == 4) return v4f32;
- if (NumElements == 8) return v8f32;
+ case MVT::f32:
+ if (NumElements == 2) return MVT::v2f32;
+ if (NumElements == 4) return MVT::v4f32;
+ if (NumElements == 8) return MVT::v8f32;
break;
- case f64:
- if (NumElements == 2) return v2f64;
- if (NumElements == 4) return v4f64;
+ case MVT::f64:
+ if (NumElements == 2) return MVT::v2f64;
+ if (NumElements == 4) return MVT::v4f64;
break;
}
- return getExtendedVectorVT(VT, NumElements);
+ return (MVT::SimpleValueType)(MVT::LastSimpleValueType+1);
+ }
+
+ static MVT getIntVectorWithNumElements(unsigned NumElts) {
+ switch (NumElts) {
+ default: return (MVT::SimpleValueType)(MVT::LastSimpleValueType+1);
+ case 1: return MVT::v1i64;
+ case 2: return MVT::v2i32;
+ case 4: return MVT::v4i16;
+ case 8: return MVT::v8i8;
+ case 16: return MVT::v16i8;
+ }
+ }
+ };
+
+ struct EVT { // EVT = Extended Value Type
+ private:
+ MVT V;
+ const Type *LLVMTy;
+
+ public:
+ EVT() : V((MVT::SimpleValueType)(MVT::LastSimpleValueType+1)) {}
+ EVT(MVT::SimpleValueType SVT) : V(SVT) { }
+ EVT(MVT S) : V(S) {}
+
+ bool operator==(const EVT VT) const {
+ if (V.SimpleTy == VT.V.SimpleTy) {
+ if (V.SimpleTy == MVT::LastSimpleValueType+1)
+ return LLVMTy == VT.LLVMTy;
+ return true;
+ }
+ return false;
+ }
+ bool operator!=(const EVT VT) const {
+ if (V.SimpleTy == VT.V.SimpleTy) {
+ if (V.SimpleTy == MVT::LastSimpleValueType+1)
+ return LLVMTy != VT.LLVMTy;
+ return false;
+ }
+ return true;
+ }
+
+ /// getFloatingPointVT - Returns the EVT that represents a floating point
+ /// type with the given number of bits. There are two floating point types
+ /// with 128 bits - this returns f128 rather than ppcf128.
+ static EVT getFloatingPointVT(unsigned BitWidth) {
+ return MVT::getFloatingPointVT(BitWidth);
+ }
+
+ /// getIntegerVT - Returns the EVT that represents an integer with the given
+ /// number of bits.
+ static EVT getIntegerVT(unsigned BitWidth) {
+ MVT M = MVT::getIntegerVT(BitWidth);
+ if (M.SimpleTy == MVT::LastSimpleValueType+1)
+ return getExtendedIntegerVT(BitWidth);
+ else
+ return M;
+ }
+
+ /// getVectorVT - Returns the EVT that represents a vector NumElements in
+ /// length, where each element is of type VT.
+ static EVT getVectorVT(EVT VT, unsigned NumElements) {
+ MVT M = MVT::getVectorVT(VT.V, NumElements);
+ if (M.SimpleTy == MVT::LastSimpleValueType+1)
+ return getExtendedVectorVT(VT, NumElements);
+ else
+ return M;
}
/// getIntVectorWithNumElements - Return any integer vector type that has
/// the specified number of elements.
static EVT getIntVectorWithNumElements(unsigned NumElts) {
- switch (NumElts) {
- default: return getVectorVT(i8, NumElts);
- case 1: return v1i64;
- case 2: return v2i32;
- case 4: return v4i16;
- case 8: return v8i8;
- case 16: return v16i8;
- }
+ MVT M = MVT::getIntVectorWithNumElements(NumElts);
+ if (M.SimpleTy == MVT::LastSimpleValueType+1)
+ return getVectorVT(EVT(MVT::i8), NumElts);
+ else
+ return M;
}
/// isSimple - Test if the given EVT is simple (as opposed to being
/// extended).
bool isSimple() const {
- return V <= LastSimpleValueType;
+ return V.SimpleTy <= MVT::LastSimpleValueType;
}
/// isExtended - Test if the given EVT is extended (as opposed to
@@ -249,49 +406,53 @@
/// isFloatingPoint - Return true if this is a FP, or a vector FP type.
bool isFloatingPoint() const {
return isSimple() ?
- ((V >= f32 && V <= ppcf128) ||
- (V >= v2f32 && V <= v4f64)) : isExtendedFloatingPoint();
+ ((V >= MVT::f32 && V <= MVT::ppcf128) ||
+ (V >= MVT::v2f32 && V <= MVT::v4f64)) : isExtendedFloatingPoint();
}
/// isInteger - Return true if this is an integer, or a vector integer type.
bool isInteger() const {
return isSimple() ?
- ((V >= FIRST_INTEGER_VALUETYPE && V <= LAST_INTEGER_VALUETYPE) ||
- (V >= v2i8 && V <= v4i64)) : isExtendedInteger();
+ ((V >= MVT::FIRST_INTEGER_VALUETYPE &&
+ V <= MVT::LAST_INTEGER_VALUETYPE) ||
+ (V >= MVT::v2i8 && V <= MVT::v4i64)) : isExtendedInteger();
}
/// isVector - Return true if this is a vector value type.
bool isVector() const {
return isSimple() ?
- (V >= FIRST_VECTOR_VALUETYPE && V <= LAST_VECTOR_VALUETYPE) :
+ (V >= MVT::FIRST_VECTOR_VALUETYPE && V <=
+ MVT::LAST_VECTOR_VALUETYPE) :
isExtendedVector();
}
/// is64BitVector - Return true if this is a 64-bit vector type.
bool is64BitVector() const {
return isSimple() ?
- (V==v8i8 || V==v4i16 || V==v2i32 || V==v1i64 || V==v2f32) :
+ (V==MVT::v8i8 || V==MVT::v4i16 || V==MVT::v2i32 ||
+ V==MVT::v1i64 || V==MVT::v2f32) :
isExtended64BitVector();
}
/// is128BitVector - Return true if this is a 128-bit vector type.
bool is128BitVector() const {
return isSimple() ?
- (V==v16i8 || V==v8i16 || V==v4i32 ||
- V==v2i64 || V==v4f32 || V==v2f64) :
+ (V==MVT::v16i8 || V==MVT::v8i16 || V==MVT::v4i32 ||
+ V==MVT::v2i64 || V==MVT::v4f32 || V==MVT::v2f64) :
isExtended128BitVector();
}
/// is256BitVector - Return true if this is a 256-bit vector type.
inline bool is256BitVector() const {
return isSimple() ?
- (V==v8f32 || V==v4f64 || V==v32i8 || V==v16i16 || V==v8i32 ||
- V==v4i64) : isExtended256BitVector();
+ (V==MVT::v8f32 || V==MVT::v4f64 || V==MVT::v32i8 ||
+ V==MVT::v16i16 || V==MVT::v8i32 || V==MVT::v4i64) :
+ isExtended256BitVector();
}
/// isOverloaded - Return true if this is an overloaded type for TableGen.
bool isOverloaded() const {
- return (V==iAny || V==fAny || V==vAny || V==iPTRAny);
+ return (V==MVT::iAny || V==MVT::fAny || V==MVT::vAny || V==MVT::iPTRAny);
}
/// isByteSized - Return true if the bit size is a multiple of 8.
@@ -333,115 +494,37 @@
/// getSimpleVT - Return the SimpleValueType held in the specified
/// simple EVT.
- SimpleValueType getSimpleVT() const {
+ MVT getSimpleVT() const {
assert(isSimple() && "Expected a SimpleValueType!");
- return SimpleValueType(V);
+ return V;
}
/// getVectorElementType - Given a vector type, return the type of
/// each element.
EVT getVectorElementType() const {
assert(isVector() && "Invalid vector type!");
- switch (V) {
- default:
+ if (isSimple())
+ return V.getVectorElementType();
+ else
return getExtendedVectorElementType();
- case v2i8 :
- case v4i8 :
- case v8i8 :
- case v16i8:
- case v32i8: return i8;
- case v2i16:
- case v4i16:
- case v8i16:
- case v16i16: return i16;
- case v2i32:
- case v4i32:
- case v8i32: return i32;
- case v1i64:
- case v2i64:
- case v4i64: return i64;
- case v2f32:
- case v4f32:
- case v8f32: return f32;
- case v2f64:
- case v4f64: return f64;
- }
}
/// getVectorNumElements - Given a vector type, return the number of
/// elements it contains.
unsigned getVectorNumElements() const {
assert(isVector() && "Invalid vector type!");
- switch (V) {
- default:
+ if (isSimple())
+ return V.getVectorNumElements();
+ else
return getExtendedVectorNumElements();
- case v32i8: return 32;
- case v16i8:
- case v16i16: return 16;
- case v8i8 :
- case v8i16:
- case v8i32:
- case v8f32: return 8;
- case v4i8:
- case v4i16:
- case v4i32:
- case v4i64:
- case v4f32:
- case v4f64: return 4;
- case v2i8:
- case v2i16:
- case v2i32:
- case v2i64:
- case v2f32:
- case v2f64: return 2;
- case v1i64: return 1;
- }
}
/// getSizeInBits - Return the size of the specified value type in bits.
unsigned getSizeInBits() const {
- switch (V) {
- case iPTR:
- assert(0 && "Value type size is target-dependent. Ask TLI.");
- case iPTRAny:
- case iAny:
- case fAny:
- case vAny:
- assert(0 && "Value type is overloaded.");
- default:
+ if (isSimple())
+ return V.getSizeInBits();
+ else
return getExtendedSizeInBits();
- case i1 : return 1;
- case i8 : return 8;
- case i16 :
- case v2i8: return 16;
- case f32 :
- case i32 :
- case v4i8:
- case v2i16: return 32;
- case f64 :
- case i64 :
- case v8i8:
- case v4i16:
- case v2i32:
- case v1i64:
- case v2f32: return 64;
- case f80 : return 80;
- case f128:
- case ppcf128:
- case i128:
- case v16i8:
- case v8i16:
- case v4i32:
- case v2i64:
- case v4f32:
- case v2f64: return 128;
- case v32i8:
- case v16i16:
- case v8i32:
- case v4i64:
- case v8f32:
- case v4f64: return 256;
- }
}
/// getStoreSizeInBits - Return the number of bits overwritten by a store
@@ -457,7 +540,7 @@
assert(isInteger() && !isVector() && "Invalid integer type!");
unsigned BitWidth = getSizeInBits();
if (BitWidth <= 8)
- return i8;
+ return EVT(MVT::i8);
else
return getIntegerVT(1 << Log2_32_Ceil(BitWidth));
}
@@ -495,14 +578,21 @@
/// types are returned as Other, otherwise they are invalid.
static EVT getEVT(const Type *Ty, bool HandleUnknown = false);
- /// getRawBits - Represent the type as a bunch of bits.
- uintptr_t getRawBits() const { return V; }
+ intptr_t getRawBits() {
+ if (V.SimpleTy <= MVT::LastSimpleValueType)
+ return V.SimpleTy;
+ else
+ return (intptr_t)(LLVMTy);
+ }
/// compareRawBits - A meaningless but well-behaved order, useful for
/// constructing containers.
struct compareRawBits {
bool operator()(EVT L, EVT R) const {
- return L.getRawBits() < R.getRawBits();
+ if (L.V.SimpleTy == R.V.SimpleTy)
+ return L.LLVMTy < R.LLVMTy;
+ else
+ return L.V.SimpleTy < R.V.SimpleTy;
}
};
Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Tue Aug 11 15:47:22 2009
@@ -111,8 +111,8 @@
bool isBigEndian() const { return !IsLittleEndian; }
bool isLittleEndian() const { return IsLittleEndian; }
- EVT::SimpleValueType getPointerTy() const { return PointerTy; }
- EVT::SimpleValueType getShiftAmountTy() const { return ShiftAmountTy; }
+ MVT getPointerTy() const { return PointerTy; }
+ MVT getShiftAmountTy() const { return ShiftAmountTy; }
/// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
/// codegen.
@@ -133,10 +133,10 @@
/// getSetCCResultType - Return the ValueType of the result of SETCC
/// operations. Also used to obtain the target's preferred type for
/// the condition operand of SELECT and BRCOND nodes. In the case of
- /// BRCOND the argument passed is EVT::Other since there are no other
+ /// BRCOND the argument passed is MVT::Other since there are no other
/// operands to get a type hint from.
virtual
- EVT::SimpleValueType getSetCCResultType(EVT VT) const;
+ MVT::SimpleValueType getSetCCResultType(EVT VT) const;
/// getBooleanContents - For targets without i1 registers, this gives the
/// nature of the high-bits of boolean values held in types wider than i1.
@@ -154,7 +154,7 @@
/// specified value type. This may only be called on legal types.
TargetRegisterClass *getRegClassFor(EVT VT) const {
assert(VT.isSimple() && "getRegClassFor called on illegal type!");
- TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT()];
+ TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
assert(RC && "This value type is not natively supported!");
return RC;
}
@@ -164,16 +164,16 @@
/// holds it without promotions or expansions.
bool isTypeLegal(EVT VT) const {
assert(!VT.isSimple() ||
- (unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
- return VT.isSimple() && RegClassForVT[VT.getSimpleVT()] != 0;
+ (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
+ return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
}
class ValueTypeActionImpl {
/// ValueTypeActions - This is a bitvector that contains two bits for each
/// value type, where the two bits correspond to the LegalizeAction enum.
/// This can be queried with "getTypeAction(VT)".
- /// dimension by (EVT::MAX_ALLOWED_VALUETYPE/32) * 2
- uint32_t ValueTypeActions[(EVT::MAX_ALLOWED_VALUETYPE/32)*2];
+ /// dimension by (MVT::MAX_ALLOWED_VALUETYPE/32) * 2
+ uint32_t ValueTypeActions[(MVT::MAX_ALLOWED_VALUETYPE/32)*2];
public:
ValueTypeActionImpl() {
ValueTypeActions[0] = ValueTypeActions[1] = 0;
@@ -197,12 +197,12 @@
assert(0 && "Unsupported extended type!");
return Legal;
}
- unsigned I = VT.getSimpleVT();
+ unsigned I = VT.getSimpleVT().SimpleTy;
assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3);
}
void setTypeAction(EVT VT, LegalizeAction Action) {
- unsigned I = VT.getSimpleVT();
+ unsigned I = VT.getSimpleVT().SimpleTy;
assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
ValueTypeActions[I>>4] |= Action << ((I*2) & 31);
}
@@ -228,8 +228,9 @@
/// returns the integer type to transform to.
EVT getTypeToTransformTo(EVT VT) const {
if (VT.isSimple()) {
- assert((unsigned)VT.getSimpleVT() < array_lengthof(TransformToType));
- EVT NVT = TransformToType[VT.getSimpleVT()];
+ assert((unsigned)VT.getSimpleVT().SimpleTy <
+ array_lengthof(TransformToType));
+ EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy];
assert(getTypeAction(NVT) != Promote &&
"Promote may not follow Expand or Promote");
return NVT;
@@ -255,7 +256,7 @@
return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
}
assert(0 && "Unsupported extended type!");
- return EVT(EVT::Other); // Not reached
+ return MVT(MVT::Other); // Not reached
}
/// getTypeToExpandTo - For types supported by the target, this is an
@@ -315,7 +316,7 @@
/// getWidenVectorType: given a vector type, returns the type to widen to
/// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
- /// If there is no vector type that we want to widen to, returns EVT::Other
+ /// If there is no vector type that we want to widen to, returns MVT::Other
/// When and were to widen is target dependent based on the cost of
/// scalarizing vs using the wider vector type.
virtual EVT getWidenVectorType(EVT VT) const;
@@ -353,9 +354,9 @@
LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
if (VT.isExtended()) return Expand;
assert(Op < array_lengthof(OpActions[0]) &&
- (unsigned)VT.getSimpleVT() < sizeof(OpActions[0][0])*8 &&
+ (unsigned)VT.getSimpleVT().SimpleTy < sizeof(OpActions[0][0])*8 &&
"Table isn't big enough!");
- unsigned I = (unsigned) VT.getSimpleVT();
+ unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
unsigned J = I & 31;
I = I >> 5;
return (LegalizeAction)((OpActions[I][Op] >> (J*2) ) & 3);
@@ -365,7 +366,7 @@
/// legal on this target or can be made legal with custom lowering. This
/// is used to help guide high-level lowering decisions.
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
- return (VT == EVT::Other || isTypeLegal(VT)) &&
+ return (VT == MVT::Other || isTypeLegal(VT)) &&
(getOperationAction(Op, VT) == Legal ||
getOperationAction(Op, VT) == Custom);
}
@@ -373,7 +374,7 @@
/// isOperationLegal - Return true if the specified operation is legal on this
/// target.
bool isOperationLegal(unsigned Op, EVT VT) const {
- return (VT == EVT::Other || isTypeLegal(VT)) &&
+ return (VT == MVT::Other || isTypeLegal(VT)) &&
getOperationAction(Op, VT) == Legal;
}
@@ -383,9 +384,10 @@
/// for it.
LegalizeAction getLoadExtAction(unsigned LType, EVT VT) const {
assert(LType < array_lengthof(LoadExtActions) &&
- (unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 &&
+ (unsigned)VT.getSimpleVT().SimpleTy < sizeof(LoadExtActions[0])*4 &&
"Table isn't big enough!");
- return (LegalizeAction)((LoadExtActions[LType] >> (2*VT.getSimpleVT())) & 3);
+ return (LegalizeAction)((LoadExtActions[LType] >>
+ (2*VT.getSimpleVT().SimpleTy)) & 3);
}
/// isLoadExtLegal - Return true if the specified load with extension is legal
@@ -402,11 +404,13 @@
/// expander for it.
LegalizeAction getTruncStoreAction(EVT ValVT,
EVT MemVT) const {
- assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) &&
- (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 &&
+ assert((unsigned)ValVT.getSimpleVT().SimpleTy <
+ array_lengthof(TruncStoreActions) &&
+ (unsigned)MemVT.getSimpleVT().SimpleTy <
+ sizeof(TruncStoreActions[0])*4 &&
"Table isn't big enough!");
- return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT()] >>
- (2*MemVT.getSimpleVT())) & 3);
+ return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT().SimpleTy] >>
+ (2*MemVT.getSimpleVT().SimpleTy)) & 3);
}
/// isTruncStoreLegal - Return true if the specified store with truncation is
@@ -424,9 +428,10 @@
LegalizeAction
getIndexedLoadAction(unsigned IdxMode, EVT VT) const {
assert( IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
- ((unsigned)VT.getSimpleVT()) < EVT::LAST_VALUETYPE &&
+ ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE &&
"Table isn't big enough!");
- return (LegalizeAction)((IndexedModeActions[(unsigned)VT.getSimpleVT()][0][IdxMode]));
+ return (LegalizeAction)((IndexedModeActions[
+ (unsigned)VT.getSimpleVT().SimpleTy][0][IdxMode]));
}
/// isIndexedLoadLegal - Return true if the specified indexed load is legal
@@ -444,9 +449,10 @@
LegalizeAction
getIndexedStoreAction(unsigned IdxMode, EVT VT) const {
assert(IdxMode < array_lengthof(IndexedModeActions[0][1]) &&
- (unsigned)VT.getSimpleVT() < EVT::LAST_VALUETYPE &&
+ (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
"Table isn't big enough!");
- return (LegalizeAction)((IndexedModeActions[(unsigned)VT.getSimpleVT()][1][IdxMode]));
+ return (LegalizeAction)((IndexedModeActions[
+ (unsigned)VT.getSimpleVT().SimpleTy][1][IdxMode]));
}
/// isIndexedStoreLegal - Return true if the specified indexed load is legal
@@ -463,11 +469,13 @@
/// for it.
LegalizeAction
getConvertAction(EVT FromVT, EVT ToVT) const {
- assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) &&
- (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 &&
+ assert((unsigned)FromVT.getSimpleVT().SimpleTy <
+ array_lengthof(ConvertActions) &&
+ (unsigned)ToVT.getSimpleVT().SimpleTy <
+ sizeof(ConvertActions[0])*4 &&
"Table isn't big enough!");
- return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT()] >>
- (2*ToVT.getSimpleVT())) & 3);
+ return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT().SimpleTy] >>
+ (2*ToVT.getSimpleVT().SimpleTy)) & 3);
}
/// isConvertLegal - Return true if the specified conversion is legal
@@ -484,10 +492,10 @@
LegalizeAction
getCondCodeAction(ISD::CondCode CC, EVT VT) const {
assert((unsigned)CC < array_lengthof(CondCodeActions) &&
- (unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 &&
+ (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 &&
"Table isn't big enough!");
LegalizeAction Action = (LegalizeAction)
- ((CondCodeActions[CC] >> (2*VT.getSimpleVT())) & 3);
+ ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3);
assert(Action != Promote && "Can't promote condition code!");
return Action;
}
@@ -507,9 +515,9 @@
"This operation isn't promoted!");
// See if this has an explicit type specified.
- std::map<std::pair<unsigned, EVT::SimpleValueType>,
- EVT::SimpleValueType>::const_iterator PTTI =
- PromoteToType.find(std::make_pair(Op, VT.getSimpleVT()));
+ std::map<std::pair<unsigned, MVT::SimpleValueType>,
+ MVT::SimpleValueType>::const_iterator PTTI =
+ PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy));
if (PTTI != PromoteToType.end()) return PTTI->second;
assert((VT.isInteger() || VT.isFloatingPoint()) &&
@@ -517,8 +525,8 @@
EVT NVT = VT;
do {
- NVT = (EVT::SimpleValueType)(NVT.getSimpleVT()+1);
- assert(NVT.isInteger() == VT.isInteger() && NVT != EVT::isVoid &&
+ NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1);
+ assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
"Didn't find type to promote to!");
} while (!isTypeLegal(NVT) ||
getOperationAction(Op, NVT) == Promote);
@@ -527,11 +535,11 @@
/// getValueType - Return the EVT corresponding to this LLVM type.
/// This is fixed by the LLVM operations except for the pointer size. If
- /// AllowUnknown is true, this will return EVT::Other for types with no EVT
+ /// AllowUnknown is true, this will return MVT::Other for types with no EVT
/// counterpart (e.g. structs), otherwise it will assert.
EVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
EVT VT = EVT::getEVT(Ty, AllowUnknown);
- return VT == EVT::iPTR ? PointerTy : VT;
+ return VT == MVT:: iPTR ? PointerTy : VT;
}
/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
@@ -543,8 +551,9 @@
/// eventually require.
EVT getRegisterType(EVT VT) const {
if (VT.isSimple()) {
- assert((unsigned)VT.getSimpleVT() < array_lengthof(RegisterTypeForVT));
- return RegisterTypeForVT[VT.getSimpleVT()];
+ assert((unsigned)VT.getSimpleVT().SimpleTy <
+ array_lengthof(RegisterTypeForVT));
+ return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
}
if (VT.isVector()) {
EVT VT1, RegisterVT;
@@ -556,7 +565,7 @@
return getRegisterType(getTypeToTransformTo(VT));
}
assert(0 && "Unsupported extended type!");
- return EVT(EVT::Other); // Not reached
+ return EVT(MVT::Other); // Not reached
}
/// getNumRegisters - Return the number of registers that this ValueType will
@@ -567,8 +576,9 @@
/// type. For an i140 on a 32 bit machine this means 5 registers.
unsigned getNumRegisters(EVT VT) const {
if (VT.isSimple()) {
- assert((unsigned)VT.getSimpleVT() < array_lengthof(NumRegistersForVT));
- return NumRegistersForVT[VT.getSimpleVT()];
+ assert((unsigned)VT.getSimpleVT().SimpleTy <
+ array_lengthof(NumRegistersForVT));
+ return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
}
if (VT.isVector()) {
EVT VT1, VT2;
@@ -638,7 +648,7 @@
virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align,
bool isSrcConst, bool isSrcStr,
SelectionDAG &DAG) const {
- return EVT::iAny;
+ return MVT::iAny;
}
/// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
@@ -869,7 +879,7 @@
/// setShiftAmountType - Describe the type that should be used for shift
/// amounts. This type defaults to the pointer type.
- void setShiftAmountType(EVT::SimpleValueType VT) { ShiftAmountTy = VT; }
+ void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
/// setBooleanContents - Specify how the target extends the result of a
/// boolean value from i1 to a wider type. See getBooleanContents.
@@ -933,9 +943,9 @@
/// regclass for the specified value type. This indicates the selector can
/// handle values of that class natively.
void addRegisterClass(EVT VT, TargetRegisterClass *RC) {
- assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
+ assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
AvailableRegClasses.push_back(std::make_pair(VT, RC));
- RegClassForVT[VT.getSimpleVT()] = RC;
+ RegClassForVT[VT.getSimpleVT().SimpleTy] = RC;
}
/// computeRegisterProperties - Once all of the register classes are added,
@@ -944,9 +954,9 @@
/// setOperationAction - Indicate that the specified operation does not work
/// with the specified type and indicate what to do about it.
- void setOperationAction(unsigned Op, EVT::SimpleValueType VT,
+ void setOperationAction(unsigned Op, MVT VT,
LegalizeAction Action) {
- unsigned I = (unsigned)VT;
+ unsigned I = (unsigned)VT.SimpleTy;
unsigned J = I & 31;
I = I >> 5;
OpActions[I][Op] &= ~(uint64_t(3UL) << (J*2));
@@ -955,80 +965,78 @@
/// setLoadExtAction - Indicate that the specified load with extension does
/// not work with the with specified type and indicate what to do about it.
- void setLoadExtAction(unsigned ExtType, EVT::SimpleValueType VT,
+ void setLoadExtAction(unsigned ExtType, MVT VT,
LegalizeAction Action) {
- assert((unsigned)VT < sizeof(LoadExtActions[0])*4 &&
+ assert((unsigned)VT.SimpleTy < sizeof(LoadExtActions[0])*4 &&
ExtType < array_lengthof(LoadExtActions) &&
"Table isn't big enough!");
- LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT*2);
- LoadExtActions[ExtType] |= (uint64_t)Action << VT*2;
+ LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
+ LoadExtActions[ExtType] |= (uint64_t)Action << VT.SimpleTy*2;
}
/// setTruncStoreAction - Indicate that the specified truncating store does
/// not work with the with specified type and indicate what to do about it.
- void setTruncStoreAction(EVT::SimpleValueType ValVT,
- EVT::SimpleValueType MemVT,
+ void setTruncStoreAction(MVT ValVT, MVT MemVT,
LegalizeAction Action) {
- assert((unsigned)ValVT < array_lengthof(TruncStoreActions) &&
- (unsigned)MemVT < sizeof(TruncStoreActions[0])*4 &&
+ assert((unsigned)ValVT.SimpleTy < array_lengthof(TruncStoreActions) &&
+ (unsigned)MemVT.SimpleTy < sizeof(TruncStoreActions[0])*4 &&
"Table isn't big enough!");
- TruncStoreActions[ValVT] &= ~(uint64_t(3UL) << MemVT*2);
- TruncStoreActions[ValVT] |= (uint64_t)Action << MemVT*2;
+ TruncStoreActions[ValVT.SimpleTy] &= ~(uint64_t(3UL) << MemVT.SimpleTy*2);
+ TruncStoreActions[ValVT.SimpleTy] |= (uint64_t)Action << MemVT.SimpleTy*2;
}
/// setIndexedLoadAction - Indicate that the specified indexed load does or
/// does not work with the with specified type and indicate what to do abort
/// it. NOTE: All indexed mode loads are initialized to Expand in
/// TargetLowering.cpp
- void setIndexedLoadAction(unsigned IdxMode, EVT::SimpleValueType VT,
+ void setIndexedLoadAction(unsigned IdxMode, MVT VT,
LegalizeAction Action) {
- assert((unsigned)VT < EVT::LAST_VALUETYPE &&
+ assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
"Table isn't big enough!");
- IndexedModeActions[(unsigned)VT][0][IdxMode] = (uint8_t)Action;
+ IndexedModeActions[(unsigned)VT.SimpleTy][0][IdxMode] = (uint8_t)Action;
}
/// setIndexedStoreAction - Indicate that the specified indexed store does or
/// does not work with the with specified type and indicate what to do about
/// it. NOTE: All indexed mode stores are initialized to Expand in
/// TargetLowering.cpp
- void setIndexedStoreAction(unsigned IdxMode, EVT::SimpleValueType VT,
+ void setIndexedStoreAction(unsigned IdxMode, MVT VT,
LegalizeAction Action) {
- assert((unsigned)VT < EVT::LAST_VALUETYPE &&
+ assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
IdxMode < array_lengthof(IndexedModeActions[0][1] ) &&
"Table isn't big enough!");
- IndexedModeActions[(unsigned)VT][1][IdxMode] = (uint8_t)Action;
+ IndexedModeActions[(unsigned)VT.SimpleTy][1][IdxMode] = (uint8_t)Action;
}
/// setConvertAction - Indicate that the specified conversion does or does
/// not work with the with specified type and indicate what to do about it.
- void setConvertAction(EVT::SimpleValueType FromVT, EVT::SimpleValueType ToVT,
+ void setConvertAction(MVT FromVT, MVT ToVT,
LegalizeAction Action) {
- assert((unsigned)FromVT < array_lengthof(ConvertActions) &&
- (unsigned)ToVT < sizeof(ConvertActions[0])*4 &&
+ assert((unsigned)FromVT.SimpleTy < array_lengthof(ConvertActions) &&
+ (unsigned)ToVT.SimpleTy < sizeof(ConvertActions[0])*4 &&
"Table isn't big enough!");
- ConvertActions[FromVT] &= ~(uint64_t(3UL) << ToVT*2);
- ConvertActions[FromVT] |= (uint64_t)Action << ToVT*2;
+ ConvertActions[FromVT.SimpleTy] &= ~(uint64_t(3UL) << ToVT.SimpleTy*2);
+ ConvertActions[FromVT.SimpleTy] |= (uint64_t)Action << ToVT.SimpleTy*2;
}
/// setCondCodeAction - Indicate that the specified condition code is or isn't
/// supported on the target and indicate what to do about it.
- void setCondCodeAction(ISD::CondCode CC, EVT::SimpleValueType VT,
+ void setCondCodeAction(ISD::CondCode CC, MVT VT,
LegalizeAction Action) {
- assert((unsigned)VT < sizeof(CondCodeActions[0])*4 &&
+ assert((unsigned)VT.SimpleTy < sizeof(CondCodeActions[0])*4 &&
(unsigned)CC < array_lengthof(CondCodeActions) &&
"Table isn't big enough!");
- CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT*2);
- CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT*2;
+ CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
+ CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2;
}
/// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
/// promotion code defaults to trying a larger integer/fp until it can find
/// one that works. If that default is insufficient, this method can be used
/// by the target to override the default.
- void AddPromotedToType(unsigned Opc, EVT::SimpleValueType OrigVT,
- EVT::SimpleValueType DestVT) {
- PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT;
+ void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
+ PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
}
/// addLegalFPImmediate - Indicate that this target can instruction select
@@ -1355,7 +1363,7 @@
AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
: InlineAsm::ConstraintInfo(info),
ConstraintType(TargetLowering::C_Unknown),
- CallOperandVal(0), ConstraintVT(EVT::Other) {
+ CallOperandVal(0), ConstraintVT(MVT::Other) {
}
};
@@ -1527,7 +1535,7 @@
/// PointerTy - The type to use for pointers, usually i32 or i64.
///
- EVT::SimpleValueType PointerTy;
+ MVT PointerTy;
/// IsLittleEndian - True if this is a little endian target.
///
@@ -1562,7 +1570,7 @@
/// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
/// PointerTy is.
- EVT::SimpleValueType ShiftAmountTy;
+ MVT ShiftAmountTy;
/// BooleanContents - Information about the contents of the high-bits in
/// boolean values held in a type wider than i1. See getBooleanContents.
@@ -1608,16 +1616,16 @@
/// RegClassForVT - This indicates the default register class to use for
/// each ValueType the target supports natively.
- TargetRegisterClass *RegClassForVT[EVT::LAST_VALUETYPE];
- unsigned char NumRegistersForVT[EVT::LAST_VALUETYPE];
- EVT RegisterTypeForVT[EVT::LAST_VALUETYPE];
+ TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
+ unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
+ EVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
/// TransformToType - For any value types we are promoting or expanding, this
/// contains the value type that we are changing to. For Expanded types, this
/// contains one step of the expand (e.g. i64 -> i32), even if there are
/// multiple steps required (e.g. i64 -> i16). For types natively supported
/// by the system, this holds the same type (e.g. i32 -> i32).
- EVT TransformToType[EVT::LAST_VALUETYPE];
+ EVT TransformToType[MVT::LAST_VALUETYPE];
/// OpActions - For each operation and each value type, keep a LegalizeAction
/// that indicates how instruction selection should deal with the operation.
@@ -1625,8 +1633,8 @@
/// operations that are not should be described. Note that operations on
/// non-legal value types are not described here.
/// This array is accessed using VT.getSimpleVT(), so it is subject to
- /// the EVT::MAX_ALLOWED_VALUETYPE * 2 bits.
- uint64_t OpActions[EVT::MAX_ALLOWED_VALUETYPE/(sizeof(uint64_t)*4)][ISD::BUILTIN_OP_END];
+ /// the MVT::MAX_ALLOWED_VALUETYPE * 2 bits.
+ uint64_t OpActions[MVT::MAX_ALLOWED_VALUETYPE/(sizeof(uint64_t)*4)][ISD::BUILTIN_OP_END];
/// LoadExtActions - For each load of load extension type and each value type,
/// keep a LegalizeAction that indicates how instruction selection should deal
@@ -1635,7 +1643,7 @@
/// TruncStoreActions - For each truncating store, keep a LegalizeAction that
/// indicates how instruction selection should deal with the store.
- uint64_t TruncStoreActions[EVT::LAST_VALUETYPE];
+ uint64_t TruncStoreActions[MVT::LAST_VALUETYPE];
/// IndexedModeActions - For each indexed mode and each value type,
/// keep a pair of LegalizeAction that indicates how instruction
@@ -1643,14 +1651,14 @@
/// dimension is now the value_type for the reference. The second
/// dimension is the load [0] vs. store[1]. The third dimension
/// represents the various modes for load store.
- uint8_t IndexedModeActions[EVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];
+ uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];
/// ConvertActions - For each conversion from source type to destination type,
/// keep a LegalizeAction that indicates how instruction selection should
/// deal with the conversion.
/// Currently, this is used only for floating->floating conversions
/// (FP_EXTEND and FP_ROUND).
- uint64_t ConvertActions[EVT::LAST_VALUETYPE];
+ uint64_t ConvertActions[MVT::LAST_VALUETYPE];
/// CondCodeActions - For each condition code (ISD::CondCode) keep a
/// LegalizeAction that indicates how instruction selection should
@@ -1675,7 +1683,7 @@
///
/// Targets add entries to this map with AddPromotedToType(..), clients access
/// this with getTypeToPromoteTo(..).
- std::map<std::pair<unsigned, EVT::SimpleValueType>, EVT::SimpleValueType>
+ std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
PromoteToType;
/// LibcallRoutineNames - Stores the name each libcall.
Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Tue Aug 11 15:47:22 2009
@@ -118,7 +118,7 @@
/// hasType - return true if this TargetRegisterClass has the ValueType vt.
///
bool hasType(EVT vt) const {
- for(int i = 0; VTs[i] != EVT::Other; ++i)
+ for(int i = 0; VTs[i].getSimpleVT().SimpleTy != MVT::Other; ++i)
if (VTs[i] == vt)
return true;
return false;
@@ -132,7 +132,7 @@
vt_iterator vt_end() const {
vt_iterator I = VTs;
- while (*I != EVT::Other) ++I;
+ while (I->getSimpleVT().SimpleTy != MVT::Other) ++I;
return I;
}
@@ -321,7 +321,7 @@
/// register of the given type. If type is EVT::Other, then just return any
/// register class the register belongs to.
virtual const TargetRegisterClass *
- getPhysicalRegisterRegClass(unsigned Reg, EVT VT = EVT::Other) const;
+ getPhysicalRegisterRegClass(unsigned Reg, EVT VT = MVT::Other) const;
/// getAllocatableSet - Returns a bitset indexed by register number
/// indicating if a register is allocatable or not. If a register class is
Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original)
+++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Tue Aug 11 15:47:22 2009
@@ -512,48 +512,48 @@
}]>;
def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i1;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
}]>;
def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i8;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
}]>;
def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i16;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
}]>;
def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i32;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
}]>;
def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::f32;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
}]>;
def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::f64;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
}]>;
def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i1;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
}]>;
def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i8;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
}]>;
def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i16;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
}]>;
def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i32;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
}]>;
def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i1;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
}]>;
def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i8;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
}]>;
def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i16;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
}]>;
def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i32;
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
}]>;
// store fragments.
@@ -573,23 +573,23 @@
}]>;
def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i8;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
}]>;
def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i16;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
}]>;
def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i32;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
}]>;
def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::f32;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
}]>;
def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::f64;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
}]>;
// indexed store fragments.
@@ -615,23 +615,23 @@
}]>;
def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
(pre_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i1;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
}]>;
def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
(pre_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i8;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
}]>;
def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
(pre_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i16;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
}]>;
def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
(pre_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i32;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
}]>;
def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
(pre_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::f32;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
}]>;
def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
@@ -647,23 +647,23 @@
}]>;
def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
(post_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i1;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
}]>;
def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
(post_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i8;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
}]>;
def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
(post_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i16;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
}]>;
def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
(post_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i32;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
}]>;
def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
(post_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == EVT::f32;
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
}]>;
// setcc convenience fragments.
@@ -711,40 +711,40 @@
def atomic_cmp_swap_8 :
PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
(atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
- return cast<AtomicSDNode>(N)->getMemoryVT() == EVT::i8;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}]>;
def atomic_cmp_swap_16 :
PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
(atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
- return cast<AtomicSDNode>(N)->getMemoryVT() == EVT::i16;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}]>;
def atomic_cmp_swap_32 :
PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
(atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
- return cast<AtomicSDNode>(N)->getMemoryVT() == EVT::i32;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}]>;
def atomic_cmp_swap_64 :
PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
(atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
- return cast<AtomicSDNode>(N)->getMemoryVT() == EVT::i64;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}]>;
multiclass binary_atomic_op<SDNode atomic_op> {
def _8 : PatFrag<(ops node:$ptr, node:$val),
(atomic_op node:$ptr, node:$val), [{
- return cast<AtomicSDNode>(N)->getMemoryVT() == EVT::i8;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}]>;
def _16 : PatFrag<(ops node:$ptr, node:$val),
(atomic_op node:$ptr, node:$val), [{
- return cast<AtomicSDNode>(N)->getMemoryVT() == EVT::i16;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}]>;
def _32 : PatFrag<(ops node:$ptr, node:$val),
(atomic_op node:$ptr, node:$val), [{
- return cast<AtomicSDNode>(N)->getMemoryVT() == EVT::i32;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}]>;
def _64 : PatFrag<(ops node:$ptr, node:$val),
(atomic_op node:$ptr, node:$val), [{
- return cast<AtomicSDNode>(N)->getMemoryVT() == EVT::i64;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}]>;
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Aug 11 15:47:22 2009
@@ -331,7 +331,7 @@
static char isNegatibleForFree(SDValue Op, bool LegalOperations,
unsigned Depth = 0) {
// No compile time optimizations on this type.
- if (Op.getValueType() == EVT::ppcf128)
+ if (Op.getValueType() == MVT::ppcf128)
return 0;
// fneg is removable even if it has multiple uses.
@@ -833,12 +833,12 @@
/// otherwise return a null sd operand.
static SDValue getInputChainForNode(SDNode *N) {
if (unsigned NumOps = N->getNumOperands()) {
- if (N->getOperand(0).getValueType() == EVT::Other)
+ if (N->getOperand(0).getValueType() == MVT::Other)
return N->getOperand(0);
- else if (N->getOperand(NumOps-1).getValueType() == EVT::Other)
+ else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
return N->getOperand(NumOps-1);
for (unsigned i = 1; i < NumOps-1; ++i)
- if (N->getOperand(i).getValueType() == EVT::Other)
+ if (N->getOperand(i).getValueType() == MVT::Other)
return N->getOperand(i);
}
return SDValue();
@@ -911,7 +911,7 @@
} else {
// New and improved token factor.
Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
- EVT::Other, &Ops[0], Ops.size());
+ MVT::Other, &Ops[0], Ops.size());
}
// Don't add users to work list.
@@ -1093,7 +1093,7 @@
if (N->hasNUsesOfValue(0, 1))
return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
DAG.getNode(ISD::CARRY_FALSE,
- N->getDebugLoc(), EVT::Flag));
+ N->getDebugLoc(), MVT::Flag));
// canonicalize constant to RHS.
if (N0C && !N1C)
@@ -1102,7 +1102,7 @@
// fold (addc x, 0) -> x + no carry out
if (N1C && N1C->isNullValue())
return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
- N->getDebugLoc(), EVT::Flag));
+ N->getDebugLoc(), MVT::Flag));
// fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
APInt LHSZero, LHSOne;
@@ -1119,7 +1119,7 @@
(LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
DAG.getNode(ISD::CARRY_FALSE,
- N->getDebugLoc(), EVT::Flag));
+ N->getDebugLoc(), MVT::Flag));
}
return SDValue();
@@ -1878,7 +1878,7 @@
LN0->isUnindexed() && N0.hasOneUse() &&
// Do not change the width of a volatile load.
!LN0->isVolatile()) {
- EVT ExtVT = EVT::Other;
+ EVT ExtVT = MVT::Other;
uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue()))
ExtVT = EVT::getIntegerVT(ActiveBits);
@@ -1887,7 +1887,7 @@
// Do not generate loads of non-round integer types since these can
// be expensive (and would be wrong if the type is not byte sized).
- if (ExtVT != EVT::Other && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
+ if (ExtVT != MVT::Other && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
(!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
EVT PtrType = N0.getOperand(1).getValueType();
@@ -2289,7 +2289,7 @@
}
// fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
- if (N1C && N1C->getAPIntValue() == 1 && VT == EVT::i1 &&
+ if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
(N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
@@ -2793,11 +2793,11 @@
if (N0C && N0C->isNullValue())
return N2;
// fold (select C, 1, X) -> (or C, X)
- if (VT == EVT::i1 && N1C && N1C->getAPIntValue() == 1)
+ if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
// fold (select C, 0, 1) -> (xor C, 1)
if (VT.isInteger() &&
- (VT0 == EVT::i1 ||
+ (VT0 == MVT::i1 ||
(VT0.isInteger() &&
TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
@@ -2813,27 +2813,27 @@
return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
}
// fold (select C, 0, X) -> (and (not C), X)
- if (VT == VT0 && VT == EVT::i1 && N1C && N1C->isNullValue()) {
+ if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
AddToWorkList(NOTNode.getNode());
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
}
// fold (select C, X, 1) -> (or (not C), X)
- if (VT == VT0 && VT == EVT::i1 && N2C && N2C->getAPIntValue() == 1) {
+ if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
AddToWorkList(NOTNode.getNode());
return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
}
// fold (select C, X, 0) -> (and C, X)
- if (VT == EVT::i1 && N2C && N2C->isNullValue())
+ if (VT == MVT::i1 && N2C && N2C->isNullValue())
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
// fold (select X, X, Y) -> (or X, Y)
// fold (select X, 1, Y) -> (or X, Y)
- if (VT == EVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
+ if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
// fold (select X, Y, X) -> (and X, Y)
// fold (select X, Y, 0) -> (and X, Y)
- if (VT == EVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
+ if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
// If we can fold this based on the true/false value, do so.
@@ -2843,10 +2843,10 @@
// fold selects based on a setcc into other things, such as min/max/abs
if (N0.getOpcode() == ISD::SETCC) {
// FIXME:
- // Check against EVT::Other for SELECT_CC, which is a workaround for targets
+ // Check against MVT::Other for SELECT_CC, which is a workaround for targets
// having to say they don't support SELECT_CC on every type the DAG knows
// about, since there is no way to mark an opcode illegal at all value types
- if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, EVT::Other) &&
+ if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
N0.getOperand(0), N0.getOperand(1),
@@ -3887,7 +3887,7 @@
if (SrcEltVT.isFloatingPoint()) {
// Convert the input float vector to a int vector where the elements are the
// same sizes.
- assert((SrcEltVT == EVT::f32 || SrcEltVT == EVT::f64) && "Unknown FP VT!");
+ assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
EVT IntVT = EVT::getIntegerVT(SrcEltVT.getSizeInBits());
BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
SrcEltVT = IntVT;
@@ -3896,7 +3896,7 @@
// Now we know the input is an integer vector. If the output is a FP type,
// convert to integer first, then to FP of the right size.
if (DstEltVT.isFloatingPoint()) {
- assert((DstEltVT == EVT::f32 || DstEltVT == EVT::f64) && "Unknown FP VT!");
+ assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
EVT TmpVT = EVT::getIntegerVT(DstEltVT.getSizeInBits());
SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode();
@@ -3988,7 +3988,7 @@
}
// fold (fadd c1, c2) -> (fadd c1, c2)
- if (N0CFP && N1CFP && VT != EVT::ppcf128)
+ if (N0CFP && N1CFP && VT != MVT::ppcf128)
return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
// canonicalize constant to RHS
if (N0CFP && !N1CFP)
@@ -4029,7 +4029,7 @@
}
// fold (fsub c1, c2) -> c1-c2
- if (N0CFP && N1CFP && VT != EVT::ppcf128)
+ if (N0CFP && N1CFP && VT != MVT::ppcf128)
return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
// fold (fsub A, 0) -> A
if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
@@ -4063,7 +4063,7 @@
}
// fold (fmul c1, c2) -> c1*c2
- if (N0CFP && N1CFP && VT != EVT::ppcf128)
+ if (N0CFP && N1CFP && VT != MVT::ppcf128)
return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
// canonicalize constant to RHS
if (N0CFP && !N1CFP)
@@ -4118,7 +4118,7 @@
}
// fold (fdiv c1, c2) -> c1/c2
- if (N0CFP && N1CFP && VT != EVT::ppcf128)
+ if (N0CFP && N1CFP && VT != MVT::ppcf128)
return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
@@ -4145,7 +4145,7 @@
EVT VT = N->getValueType(0);
// fold (frem c1, c2) -> fmod(c1,c2)
- if (N0CFP && N1CFP && VT != EVT::ppcf128)
+ if (N0CFP && N1CFP && VT != MVT::ppcf128)
return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
return SDValue();
@@ -4158,7 +4158,7 @@
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
EVT VT = N->getValueType(0);
- if (N0CFP && N1CFP && VT != EVT::ppcf128) // Constant fold
+ if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
if (N1CFP) {
@@ -4208,7 +4208,7 @@
EVT OpVT = N0.getValueType();
// fold (sint_to_fp c1) -> c1fp
- if (N0C && OpVT != EVT::ppcf128)
+ if (N0C && OpVT != MVT::ppcf128)
return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
// If the input is a legal type, and SINT_TO_FP is not legal on this target,
@@ -4230,7 +4230,7 @@
EVT OpVT = N0.getValueType();
// fold (uint_to_fp c1) -> c1fp
- if (N0C && OpVT != EVT::ppcf128)
+ if (N0C && OpVT != MVT::ppcf128)
return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
// If the input is a legal type, and UINT_TO_FP is not legal on this target,
@@ -4263,7 +4263,7 @@
EVT VT = N->getValueType(0);
// fold (fp_to_uint c1fp) -> c1
- if (N0CFP && VT != EVT::ppcf128)
+ if (N0CFP && VT != MVT::ppcf128)
return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
return SDValue();
@@ -4276,7 +4276,7 @@
EVT VT = N->getValueType(0);
// fold (fp_round c1fp) -> c1fp
- if (N0CFP && N0.getValueType() != EVT::ppcf128)
+ if (N0CFP && N0.getValueType() != MVT::ppcf128)
return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
// fold (fp_round (fp_extend x)) -> x
@@ -4330,7 +4330,7 @@
return SDValue();
// fold (fp_extend c1fp) -> c1fp
- if (N0CFP && VT != EVT::ppcf128)
+ if (N0CFP && VT != MVT::ppcf128)
return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
// Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
@@ -4398,7 +4398,7 @@
EVT VT = N->getValueType(0);
// fold (fabs c1) -> fabs(c1)
- if (N0CFP && VT != EVT::ppcf128)
+ if (N0CFP && VT != MVT::ppcf128)
return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
// fold (fabs (fabs x)) -> (fabs x)
if (N0.getOpcode() == ISD::FABS)
@@ -4438,12 +4438,12 @@
return Chain;
// unconditional branch
if (N1C && N1C->getAPIntValue() == 1)
- return DAG.getNode(ISD::BR, N->getDebugLoc(), EVT::Other, Chain, N2);
+ return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2);
// fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
// on the target.
if (N1.getOpcode() == ISD::SETCC &&
- TLI.isOperationLegalOrCustom(ISD::BR_CC, EVT::Other)) {
- return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), EVT::Other,
+ TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
+ return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
Chain, N1.getOperand(2),
N1.getOperand(0), N1.getOperand(1), N2);
}
@@ -4491,7 +4491,7 @@
removeFromWorkList(N1.getNode());
DAG.DeleteNode(N1.getNode());
return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
- EVT::Other, Chain, SetCC, N2);
+ MVT::Other, Chain, SetCC, N2);
}
}
}
@@ -4516,7 +4516,7 @@
// fold br_cc true, dest -> br dest (unconditional branch)
if (SCCC && !SCCC->isNullValue())
- return DAG.getNode(ISD::BR, N->getDebugLoc(), EVT::Other,
+ return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other,
N->getOperand(0), N->getOperand(4));
// fold br_cc false, dest -> unconditional fall through
if (SCCC && SCCC->isNullValue())
@@ -4524,7 +4524,7 @@
// fold to a simpler setcc
if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
- return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), EVT::Other,
+ return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
N->getOperand(0), Simp.getOperand(2),
Simp.getOperand(0), Simp.getOperand(1),
N->getOperand(4));
@@ -4859,7 +4859,7 @@
// the updated indexed value in case of indexed loads), change uses of the
// chain value into uses of the chain input (i.e. delete the dead load).
if (!LD->isVolatile()) {
- if (N->getValueType(1) == EVT::Other) {
+ if (N->getValueType(1) == MVT::Other) {
// Unindexed loads.
if (N->hasNUsesOfValue(0, 0)) {
// It's not safe to use the two value CombineTo variant here. e.g.
@@ -4883,7 +4883,7 @@
}
} else {
// Indexed loads.
- assert(N->getValueType(2) == EVT::Other && "Malformed indexed loads?");
+ assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
SDValue Undef = DAG.getUNDEF(N->getValueType(0));
DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
@@ -4942,7 +4942,7 @@
// Create token factor to keep old chain connected.
SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
- EVT::Other, Chain, ReplLoad.getValue(1));
+ MVT::Other, Chain, ReplLoad.getValue(1));
// Replace uses with load result and token factor. Don't add users
// to work list.
@@ -5096,42 +5096,42 @@
// transform should not be done in this case.
if (Value.getOpcode() != ISD::TargetConstantFP) {
SDValue Tmp;
- switch (CFP->getValueType(0).getSimpleVT()) {
+ switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unknown FP type");
- case EVT::f80: // We don't do this for these yet.
- case EVT::f128:
- case EVT::ppcf128:
+ case MVT::f80: // We don't do this for these yet.
+ case MVT::f128:
+ case MVT::ppcf128:
break;
- case EVT::f32:
- if (((TLI.isTypeLegal(EVT::i32) || !LegalTypes) && !LegalOperations &&
+ case MVT::f32:
+ if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations &&
!ST->isVolatile()) ||
- TLI.isOperationLegalOrCustom(ISD::STORE, EVT::i32)) {
+ TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
- bitcastToAPInt().getZExtValue(), EVT::i32);
+ bitcastToAPInt().getZExtValue(), MVT::i32);
return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
Ptr, ST->getSrcValue(),
ST->getSrcValueOffset(), ST->isVolatile(),
ST->getAlignment());
}
break;
- case EVT::f64:
- if (((TLI.isTypeLegal(EVT::i64) || !LegalTypes) && !LegalOperations &&
+ case MVT::f64:
+ if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations &&
!ST->isVolatile()) ||
- TLI.isOperationLegalOrCustom(ISD::STORE, EVT::i64)) {
+ TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
- getZExtValue(), EVT::i64);
+ getZExtValue(), MVT::i64);
return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
Ptr, ST->getSrcValue(),
ST->getSrcValueOffset(), ST->isVolatile(),
ST->getAlignment());
} else if (!ST->isVolatile() &&
- TLI.isOperationLegalOrCustom(ISD::STORE, EVT::i32)) {
+ TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
// Many FP stores are not made apparent until after legalize, e.g. for
// argument passing. Since this is so common, custom legalize the
// 64-bit integer store into two 32-bit stores.
uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
- SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, EVT::i32);
- SDValue Hi = DAG.getConstant(Val >> 32, EVT::i32);
+ SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
+ SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
if (TLI.isBigEndian()) std::swap(Lo, Hi);
int SVOffset = ST->getSrcValueOffset();
@@ -5149,7 +5149,7 @@
SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
Ptr, ST->getSrcValue(),
SVOffset, isVolatile, Alignment);
- return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), EVT::Other,
+ return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
St0, St1);
}
@@ -5179,7 +5179,7 @@
// Create token to keep both nodes around.
SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
- EVT::Other, Chain, ReplStore);
+ MVT::Other, Chain, ReplStore);
// Don't add users to work list.
return CombineTo(N, Token, false);
@@ -5932,7 +5932,7 @@
Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
N2.getValueType(), SCC);
} else {
- SCC = DAG.getSetCC(N0.getDebugLoc(), EVT::i1, N0, N1, CC);
+ SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
N2.getValueType(), SCC);
}
@@ -6239,7 +6239,7 @@
}
// Construct a custom tailored token factor.
- SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), EVT::Other,
+ SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
&Aliases[0], Aliases.size());
// Make sure the old chain gets cleaned up.
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Tue Aug 11 15:47:22 2009
@@ -65,10 +65,10 @@
// Ignore illegal types. We must do this before looking up the value
// in ValueMap because Arguments are given virtual registers regardless
// of whether FastISel can handle them.
- EVT::SimpleValueType VT = RealVT.getSimpleVT();
+ MVT VT = RealVT.getSimpleVT();
if (!TLI.isTypeLegal(VT)) {
- // Promote EVT::i1 to a legal type though, because it's common and easy.
- if (VT == EVT::i1)
+ // Promote MVT::i1 to a legal type though, because it's common and easy.
+ if (VT == MVT::i1)
VT = TLI.getTypeToTransformTo(VT).getSimpleVT();
else
return 0;
@@ -190,7 +190,7 @@
///
bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
- if (VT == EVT::Other || !VT.isSimple())
+ if (VT == MVT::Other || !VT.isSimple())
// Unhandled type. Halt "fast" selection and bail.
return false;
@@ -199,9 +199,9 @@
// under the assumption that i64 won't be used if the target doesn't
// support it.
if (!TLI.isTypeLegal(VT)) {
- // EVT::i1 is special. Allow AND, OR, or XOR because they
+ // MVT::i1 is special. Allow AND, OR, or XOR because they
// don't require additional zeroing, which makes them easy.
- if (VT == EVT::i1 &&
+ if (VT == MVT::i1 &&
(ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
ISDOpcode == ISD::XOR))
VT = TLI.getTypeToTransformTo(VT);
@@ -261,7 +261,7 @@
return false;
const Type *Ty = I->getOperand(0)->getType();
- EVT::SimpleValueType VT = TLI.getPointerTy();
+ MVT VT = TLI.getPointerTy();
for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
OI != E; ++OI) {
Value *Idx = *OI;
@@ -457,7 +457,7 @@
default: break;
case TargetLowering::Expand: {
EVT VT = (IID == Intrinsic::eh_selector_i32 ?
- EVT::i32 : EVT::i64);
+ MVT::i32 : MVT::i64);
if (MMI) {
if (MBB->isLandingPad())
@@ -497,8 +497,8 @@
EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
EVT DstVT = TLI.getValueType(I->getType());
- if (SrcVT == EVT::Other || !SrcVT.isSimple() ||
- DstVT == EVT::Other || !DstVT.isSimple())
+ if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
+ DstVT == MVT::Other || !DstVT.isSimple())
// Unhandled type. Halt "fast" selection and bail.
return false;
@@ -506,7 +506,7 @@
// it may be i1 if we're doing a truncate because that's
// easy and somewhat common.
if (!TLI.isTypeLegal(DstVT))
- if (DstVT != EVT::i1 || Opcode != ISD::TRUNCATE)
+ if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
// Unhandled type. Halt "fast" selection and bail.
return false;
@@ -514,7 +514,7 @@
// it may be i1 if we're doing zero-extension because that's
// easy and somewhat common.
if (!TLI.isTypeLegal(SrcVT))
- if (SrcVT != EVT::i1 || Opcode != ISD::ZERO_EXTEND)
+ if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
// Unhandled type. Halt "fast" selection and bail.
return false;
@@ -524,14 +524,14 @@
return false;
// If the operand is i1, arrange for the high bits in the register to be zero.
- if (SrcVT == EVT::i1) {
+ if (SrcVT == MVT::i1) {
SrcVT = TLI.getTypeToTransformTo(SrcVT);
InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
if (!InputReg)
return false;
}
// If the result is i1, truncate to the target's type for i1 first.
- if (DstVT == EVT::i1)
+ if (DstVT == MVT::i1)
DstVT = TLI.getTypeToTransformTo(DstVT);
unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
@@ -559,8 +559,8 @@
EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
EVT DstVT = TLI.getValueType(I->getType());
- if (SrcVT == EVT::Other || !SrcVT.isSimple() ||
- DstVT == EVT::Other || !DstVT.isSimple() ||
+ if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
+ DstVT == MVT::Other || !DstVT.isSimple() ||
!TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
// Unhandled type. Halt "fast" selection and bail.
return false;
@@ -759,45 +759,44 @@
FastISel::~FastISel() {}
-unsigned FastISel::FastEmit_(EVT::SimpleValueType, EVT::SimpleValueType,
+unsigned FastISel::FastEmit_(MVT, MVT,
ISD::NodeType) {
return 0;
}
-unsigned FastISel::FastEmit_r(EVT::SimpleValueType, EVT::SimpleValueType,
+unsigned FastISel::FastEmit_r(MVT, MVT,
ISD::NodeType, unsigned /*Op0*/) {
return 0;
}
-unsigned FastISel::FastEmit_rr(EVT::SimpleValueType, EVT::SimpleValueType,
+unsigned FastISel::FastEmit_rr(MVT, MVT,
ISD::NodeType, unsigned /*Op0*/,
unsigned /*Op0*/) {
return 0;
}
-unsigned FastISel::FastEmit_i(EVT::SimpleValueType, EVT::SimpleValueType,
- ISD::NodeType, uint64_t /*Imm*/) {
+unsigned FastISel::FastEmit_i(MVT, MVT, ISD::NodeType, uint64_t /*Imm*/) {
return 0;
}
-unsigned FastISel::FastEmit_f(EVT::SimpleValueType, EVT::SimpleValueType,
+unsigned FastISel::FastEmit_f(MVT, MVT,
ISD::NodeType, ConstantFP * /*FPImm*/) {
return 0;
}
-unsigned FastISel::FastEmit_ri(EVT::SimpleValueType, EVT::SimpleValueType,
+unsigned FastISel::FastEmit_ri(MVT, MVT,
ISD::NodeType, unsigned /*Op0*/,
uint64_t /*Imm*/) {
return 0;
}
-unsigned FastISel::FastEmit_rf(EVT::SimpleValueType, EVT::SimpleValueType,
+unsigned FastISel::FastEmit_rf(MVT, MVT,
ISD::NodeType, unsigned /*Op0*/,
ConstantFP * /*FPImm*/) {
return 0;
}
-unsigned FastISel::FastEmit_rri(EVT::SimpleValueType, EVT::SimpleValueType,
+unsigned FastISel::FastEmit_rri(MVT, MVT,
ISD::NodeType,
unsigned /*Op0*/, unsigned /*Op1*/,
uint64_t /*Imm*/) {
@@ -808,9 +807,9 @@
/// to emit an instruction with an immediate operand using FastEmit_ri.
/// If that fails, it materializes the immediate into a register and try
/// FastEmit_rr instead.
-unsigned FastISel::FastEmit_ri_(EVT::SimpleValueType VT, ISD::NodeType Opcode,
+unsigned FastISel::FastEmit_ri_(MVT VT, ISD::NodeType Opcode,
unsigned Op0, uint64_t Imm,
- EVT::SimpleValueType ImmType) {
+ MVT ImmType) {
// First check if immediate type is legal. If not, we can't use the ri form.
unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
if (ResultReg != 0)
@@ -825,9 +824,9 @@
/// to emit an instruction with a floating-point immediate operand using
/// FastEmit_rf. If that fails, it materializes the immediate into a register
/// and try FastEmit_rr instead.
-unsigned FastISel::FastEmit_rf_(EVT::SimpleValueType VT, ISD::NodeType Opcode,
+unsigned FastISel::FastEmit_rf_(MVT VT, ISD::NodeType Opcode,
unsigned Op0, ConstantFP *FPImm,
- EVT::SimpleValueType ImmType) {
+ MVT ImmType) {
// First check if immediate type is legal. If not, we can't use the rf form.
unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
if (ResultReg != 0)
@@ -988,7 +987,7 @@
return ResultReg;
}
-unsigned FastISel::FastEmitInst_extractsubreg(EVT::SimpleValueType RetVT,
+unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
unsigned Op0, uint32_t Idx) {
const TargetRegisterClass* RC = MRI.getRegClass(Op0);
@@ -1009,6 +1008,6 @@
/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
/// with all but the least significant bit set to zero.
-unsigned FastISel::FastEmitZExtFromI1(EVT::SimpleValueType VT, unsigned Op) {
+unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op) {
return FastEmit_ri(VT, VT, ISD::AND, Op, 1);
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Aug 11 15:47:22 2009
@@ -213,7 +213,7 @@
CodeGenOpt::Level ol)
: TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
ValueTypeActions(TLI.getValueTypeActions()) {
- assert(EVT::LAST_VALUETYPE <= EVT::MAX_ALLOWED_VALUETYPE &&
+ assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
"Too many value types for ValueTypeActions to hold!");
}
@@ -254,19 +254,19 @@
// The chain is usually at the end.
SDValue TheChain(Node, Node->getNumValues()-1);
- if (TheChain.getValueType() != EVT::Other) {
+ if (TheChain.getValueType() != MVT::Other) {
// Sometimes it's at the beginning.
TheChain = SDValue(Node, 0);
- if (TheChain.getValueType() != EVT::Other) {
+ if (TheChain.getValueType() != MVT::Other) {
// Otherwise, hunt for it.
for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
- if (Node->getValueType(i) == EVT::Other) {
+ if (Node->getValueType(i) == MVT::Other) {
TheChain = SDValue(Node, i);
break;
}
// Otherwise, we walked into a node without a chain.
- if (TheChain.getValueType() != EVT::Other)
+ if (TheChain.getValueType() != MVT::Other)
return 0;
}
}
@@ -290,7 +290,7 @@
assert(Node && "Didn't find callseq_start for a call??");
if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
- assert(Node->getOperand(0).getValueType() == EVT::Other &&
+ assert(Node->getOperand(0).getValueType() == MVT::Other &&
"Node doesn't have a token chain argument!");
return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
}
@@ -347,15 +347,15 @@
EVT VT = CFP->getValueType(0);
ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
if (!UseCP) {
- assert((VT == EVT::f64 || VT == EVT::f32) && "Invalid type expansion");
+ assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
- (VT == EVT::f64) ? EVT::i64 : EVT::i32);
+ (VT == MVT::f64) ? MVT::i64 : MVT::i32);
}
EVT OrigVT = VT;
EVT SVT = VT;
- while (SVT != EVT::f32) {
- SVT = (EVT::SimpleValueType)(SVT.getSimpleVT() - 1);
+ while (SVT != MVT::f32) {
+ SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
// Only do this if the target has a native EXTLOAD instruction from
// smaller type.
@@ -450,7 +450,7 @@
MemVT, ST->isVolatile(),
MinAlign(ST->getAlignment(), Offset)));
// The order of the stores doesn't matter - say it with a TokenFactor.
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &Stores[0],
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
Stores.size());
}
}
@@ -459,7 +459,7 @@
"Unaligned store of unknown type.");
// Get the half-size VT
EVT NewStoredVT =
- (EVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
+ (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT().SimpleTy - 1);
int NumBits = NewStoredVT.getSizeInBits();
int IncrementSize = NumBits / 8;
@@ -480,7 +480,7 @@
ST->getSrcValue(), SVOffset + IncrementSize,
NewStoredVT, ST->isVolatile(), Alignment);
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Store1, Store2);
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
}
/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
@@ -552,7 +552,7 @@
NULL, 0, MemVT));
// The order of the stores doesn't matter - say it with a TokenFactor.
- SDValue TF = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &Stores[0],
+ SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
Stores.size());
// Finally, perform the original load only redirected to the stack slot.
@@ -607,7 +607,7 @@
SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
- SDValue TF = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
+ SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
SDValue Ops[] = { Result, TF };
@@ -702,27 +702,27 @@
bool isVolatile = ST->isVolatile();
DebugLoc dl = ST->getDebugLoc();
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
- if (CFP->getValueType(0) == EVT::f32 &&
- getTypeAction(EVT::i32) == Legal) {
+ if (CFP->getValueType(0) == MVT::f32 &&
+ getTypeAction(MVT::i32) == Legal) {
Tmp3 = DAG.getConstant(CFP->getValueAPF().
bitcastToAPInt().zextOrTrunc(32),
- EVT::i32);
+ MVT::i32);
return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
SVOffset, isVolatile, Alignment);
- } else if (CFP->getValueType(0) == EVT::f64) {
+ } else if (CFP->getValueType(0) == MVT::f64) {
// If this target supports 64-bit registers, do a single 64-bit store.
- if (getTypeAction(EVT::i64) == Legal) {
+ if (getTypeAction(MVT::i64) == Legal) {
Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
- zextOrTrunc(64), EVT::i64);
+ zextOrTrunc(64), MVT::i64);
return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
SVOffset, isVolatile, Alignment);
- } else if (getTypeAction(EVT::i32) == Legal && !ST->isVolatile()) {
+ } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
// Otherwise, if the target supports 32-bit registers, use 2 32-bit
// stores. If the target supports neither 32- nor 64-bits, this
// xform is certainly not worth it.
const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
- SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), EVT::i32);
- SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), EVT::i32);
+ SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
+ SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
if (TLI.isBigEndian()) std::swap(Lo, Hi);
Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
@@ -732,7 +732,7 @@
Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
isVolatile, MinAlign(Alignment, 4U));
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
}
}
}
@@ -777,7 +777,7 @@
case ISD::INTRINSIC_VOID:
case ISD::VAARG:
case ISD::STACKSAVE:
- Action = TLI.getOperationAction(Node->getOpcode(), EVT::Other);
+ Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
break;
case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP:
@@ -882,7 +882,7 @@
case ISD::BR_CC:
case ISD::BRCOND:
// Branches tweak the chain to include LastCALLSEQ_END
- Ops[0] = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Ops[0],
+ Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
LastCALLSEQ_END);
Ops[0] = LegalizeOp(Ops[0]);
LastCALLSEQ_END = DAG.getEntryNode();
@@ -979,7 +979,7 @@
// Merge in the last call, to ensure that this call start after the last
// call ended.
if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
- Tmp1 = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
Tmp1, LastCALLSEQ_END);
Tmp1 = LegalizeOp(Tmp1);
}
@@ -1026,7 +1026,7 @@
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
// Do not try to legalize the target-specific arguments (#1+), except for
// an optional flag input.
- if (Node->getOperand(Node->getNumOperands()-1).getValueType() != EVT::Flag){
+ if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
if (Tmp1 != Node->getOperand(0)) {
SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
Ops[0] = Tmp1;
@@ -1122,8 +1122,8 @@
// tells the optimizers that those bits are undefined. It would be
// nice to have an effective generic way of getting these benefits...
// Until such a way is found, don't insist on promoting i1 here.
- (SrcVT != EVT::i1 ||
- TLI.getLoadExtAction(ExtType, EVT::i1) == TargetLowering::Promote)) {
+ (SrcVT != MVT::i1 ||
+ TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
// Promote to a byte-sized load if not loading an integral number of
// bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
unsigned NewWidth = SrcVT.getStoreSizeInBits();
@@ -1189,7 +1189,7 @@
// Build a factor node to remember that this load is independent of the
// other one.
- Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
+ Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
// Move the top bits to the right place.
@@ -1218,7 +1218,7 @@
// Build a factor node to remember that this load is independent of the
// other one.
- Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
+ Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
// Move the top bits to the right place.
@@ -1267,7 +1267,7 @@
break;
case TargetLowering::Expand:
// f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
- if (SrcVT == EVT::f32 && Node->getValueType(0) == EVT::f64) {
+ if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
LD->getSrcValueOffset(),
LD->isVolatile(), LD->getAlignment());
@@ -1416,7 +1416,7 @@
}
// The order of the stores doesn't matter.
- Result = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
+ Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
} else {
if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
Tmp2 != ST->getBasePtr())
@@ -1524,7 +1524,7 @@
SDValue StoreChain;
if (!Stores.empty()) // Not all undef elements?
- StoreChain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&Stores[0], Stores.size());
else
StoreChain = DAG.getEntryNode();
@@ -1537,28 +1537,28 @@
DebugLoc dl = Node->getDebugLoc();
SDValue Tmp1 = Node->getOperand(0);
SDValue Tmp2 = Node->getOperand(1);
- assert((Tmp2.getValueType() == EVT::f32 ||
- Tmp2.getValueType() == EVT::f64) &&
+ assert((Tmp2.getValueType() == MVT::f32 ||
+ Tmp2.getValueType() == MVT::f64) &&
"Ugly special-cased code!");
// Get the sign bit of the RHS.
SDValue SignBit;
- EVT IVT = Tmp2.getValueType() == EVT::f64 ? EVT::i64 : EVT::i32;
+ EVT IVT = Tmp2.getValueType() == MVT::f64 ? MVT::i64 : MVT::i32;
if (isTypeLegal(IVT)) {
SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
} else {
assert(isTypeLegal(TLI.getPointerTy()) &&
- (TLI.getPointerTy() == EVT::i32 ||
- TLI.getPointerTy() == EVT::i64) &&
+ (TLI.getPointerTy() == MVT::i32 ||
+ TLI.getPointerTy() == MVT::i64) &&
"Legal type for load?!");
SDValue StackPtr = DAG.CreateStackTemporary(Tmp2.getValueType());
SDValue StorePtr = StackPtr, LoadPtr = StackPtr;
SDValue Ch =
DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StorePtr, NULL, 0);
- if (Tmp2.getValueType() == EVT::f64 && TLI.isLittleEndian())
+ if (Tmp2.getValueType() == MVT::f64 && TLI.isLittleEndian())
LoadPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(),
LoadPtr, DAG.getIntPtrConstant(4));
SignBit = DAG.getExtLoad(ISD::SEXTLOAD, dl, TLI.getPointerTy(),
- Ch, LoadPtr, NULL, 0, EVT::i32);
+ Ch, LoadPtr, NULL, 0, MVT::i32);
}
SignBit =
DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
@@ -1577,8 +1577,8 @@
DebugLoc dl = Node->getDebugLoc();
DwarfWriter *DW = DAG.getDwarfWriter();
bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC,
- EVT::Other);
- bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, EVT::Other);
+ MVT::Other);
+ bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other);
const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit());
@@ -1592,9 +1592,9 @@
// A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
// won't hurt anything.
if (useDEBUG_LOC) {
- return DAG.getNode(ISD::DEBUG_LOC, dl, EVT::Other, Node->getOperand(0),
- DAG.getConstant(Line, EVT::i32),
- DAG.getConstant(Col, EVT::i32),
+ return DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Node->getOperand(0),
+ DAG.getConstant(Line, MVT::i32),
+ DAG.getConstant(Col, MVT::i32),
DAG.getSrcValue(CU.getGV()));
} else {
unsigned ID = DW->RecordSourceLine(Line, Col, CU);
@@ -1886,12 +1886,12 @@
RTLIB::Libcall Call_F80,
RTLIB::Libcall Call_PPCF128) {
RTLIB::Libcall LC;
- switch (Node->getValueType(0).getSimpleVT()) {
+ switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unexpected request for libcall!");
- case EVT::f32: LC = Call_F32; break;
- case EVT::f64: LC = Call_F64; break;
- case EVT::f80: LC = Call_F80; break;
- case EVT::ppcf128: LC = Call_PPCF128; break;
+ case MVT::f32: LC = Call_F32; break;
+ case MVT::f64: LC = Call_F64; break;
+ case MVT::f80: LC = Call_F80; break;
+ case MVT::ppcf128: LC = Call_PPCF128; break;
}
return ExpandLibCall(LC, Node, false);
}
@@ -1902,12 +1902,12 @@
RTLIB::Libcall Call_I64,
RTLIB::Libcall Call_I128) {
RTLIB::Libcall LC;
- switch (Node->getValueType(0).getSimpleVT()) {
+ switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unexpected request for libcall!");
- case EVT::i16: LC = Call_I16; break;
- case EVT::i32: LC = Call_I32; break;
- case EVT::i64: LC = Call_I64; break;
- case EVT::i128: LC = Call_I128; break;
+ case MVT::i16: LC = Call_I16; break;
+ case MVT::i32: LC = Call_I32; break;
+ case MVT::i64: LC = Call_I64; break;
+ case MVT::i128: LC = Call_I128; break;
}
return ExpandLibCall(LC, Node, isSigned);
}
@@ -1920,11 +1920,11 @@
SDValue Op0,
EVT DestVT,
DebugLoc dl) {
- if (Op0.getValueType() == EVT::i32) {
+ if (Op0.getValueType() == MVT::i32) {
// simple 32-bit [signed|unsigned] integer to float/double expansion
// Get the stack frame index of a 8 byte buffer.
- SDValue StackSlot = DAG.CreateStackTemporary(EVT::f64);
+ SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
// word offset constant for Hi/Lo address computation
SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
@@ -1939,8 +1939,8 @@
SDValue Op0Mapped;
if (isSigned) {
// constant used to invert sign bit (signed to unsigned mapping)
- SDValue SignBit = DAG.getConstant(0x80000000u, EVT::i32);
- Op0Mapped = DAG.getNode(ISD::XOR, dl, EVT::i32, Op0, SignBit);
+ SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
+ Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
} else {
Op0Mapped = Op0;
}
@@ -1948,28 +1948,28 @@
SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
Op0Mapped, Lo, NULL, 0);
// initial hi portion of constructed double
- SDValue InitialHi = DAG.getConstant(0x43300000u, EVT::i32);
+ SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
// store the hi of the constructed double - biased exponent
SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0);
// load the constructed double
- SDValue Load = DAG.getLoad(EVT::f64, dl, Store2, StackSlot, NULL, 0);
+ SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0);
// FP constant to bias correct the final result
SDValue Bias = DAG.getConstantFP(isSigned ?
BitsToDouble(0x4330000080000000ULL) :
BitsToDouble(0x4330000000000000ULL),
- EVT::f64);
+ MVT::f64);
// subtract the bias
- SDValue Sub = DAG.getNode(ISD::FSUB, dl, EVT::f64, Load, Bias);
+ SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
// final result
SDValue Result;
// handle final rounding
- if (DestVT == EVT::f64) {
+ if (DestVT == MVT::f64) {
// do nothing
Result = Sub;
- } else if (DestVT.bitsLT(EVT::f64)) {
+ } else if (DestVT.bitsLT(MVT::f64)) {
Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
DAG.getIntPtrConstant(0));
- } else if (DestVT.bitsGT(EVT::f64)) {
+ } else if (DestVT.bitsGT(MVT::f64)) {
Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
}
return Result;
@@ -1988,12 +1988,12 @@
// as a negative number. To counteract this, the dynamic code adds an
// offset depending on the data type.
uint64_t FF;
- switch (Op0.getValueType().getSimpleVT()) {
+ switch (Op0.getValueType().getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unsupported integer type!");
- case EVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
- case EVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
- case EVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
- case EVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
+ case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
+ case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
+ case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
+ case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
}
if (TLI.isLittleEndian()) FF <<= 32;
Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
@@ -2003,8 +2003,8 @@
CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
Alignment = std::min(Alignment, 4u);
SDValue FudgeInReg;
- if (DestVT == EVT::f32)
- FudgeInReg = DAG.getLoad(EVT::f32, dl, DAG.getEntryNode(), CPIdx,
+ if (DestVT == MVT::f32)
+ FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0,
false, Alignment);
else {
@@ -2012,7 +2012,7 @@
LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0,
- EVT::f32, false, Alignment));
+ MVT::f32, false, Alignment));
}
return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
@@ -2034,7 +2034,7 @@
// Scan for the appropriate larger type to use.
while (1) {
- NewInTy = (EVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
+ NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
assert(NewInTy.isInteger() && "Ran out of possibilities!");
// If the target supports SINT_TO_FP of this type, use it.
@@ -2076,7 +2076,7 @@
// Scan for the appropriate larger type to use.
while (1) {
- NewOutTy = (EVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
+ NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
assert(NewOutTy.isInteger() && "Ran out of possibilities!");
if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
@@ -2107,13 +2107,13 @@
EVT VT = Op.getValueType();
EVT SHVT = TLI.getShiftAmountTy();
SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unhandled Expand type in BSWAP!");
- case EVT::i16:
+ case MVT::i16:
Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
- case EVT::i32:
+ case MVT::i32:
Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
@@ -2123,7 +2123,7 @@
Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
- case EVT::i64:
+ case MVT::i64:
Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
@@ -2834,7 +2834,7 @@
Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
TLI.getPICJumpTableRelocBase(Table, DAG));
}
- Tmp1 = DAG.getNode(ISD::BRIND, dl, EVT::Other, LD.getValue(1), Addr);
+ Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
Results.push_back(Tmp1);
break;
}
@@ -2844,12 +2844,12 @@
Tmp1 = Node->getOperand(0);
Tmp2 = Node->getOperand(1);
if (Tmp2.getOpcode() == ISD::SETCC) {
- Tmp1 = DAG.getNode(ISD::BR_CC, dl, EVT::Other,
+ Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
Tmp1, Tmp2.getOperand(2),
Tmp2.getOperand(0), Tmp2.getOperand(1),
Node->getOperand(2));
} else {
- Tmp1 = DAG.getNode(ISD::BR_CC, dl, EVT::Other, Tmp1,
+ Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
DAG.getCondCode(ISD::SETNE), Tmp2,
DAG.getConstant(0, Tmp2.getValueType()),
Node->getOperand(2));
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Tue Aug 11 15:47:22 2009
@@ -31,10 +31,10 @@
RTLIB::Libcall Call_F80,
RTLIB::Libcall Call_PPCF128) {
return
- VT == EVT::f32 ? Call_F32 :
- VT == EVT::f64 ? Call_F64 :
- VT == EVT::f80 ? Call_F80 :
- VT == EVT::ppcf128 ? Call_PPCF128 :
+ VT == MVT::f32 ? Call_F32 :
+ VT == MVT::f64 ? Call_F64 :
+ VT == MVT::f80 ? Call_F80 :
+ VT == MVT::ppcf128 ? Call_PPCF128 :
RTLIB::UNKNOWN_LIBCALL;
}
@@ -353,7 +353,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FPOWI(SDNode *N) {
- assert(N->getOperand(1).getValueType() == EVT::i32 &&
+ assert(N->getOperand(1).getValueType() == MVT::i32 &&
"Unsupported power type!");
EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)), N->getOperand(1) };
@@ -510,9 +510,9 @@
// a larger type, eg: i8 -> fp. Even if it is legal, no libcall may exactly
// match. Look for an appropriate libcall.
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- for (unsigned t = EVT::FIRST_INTEGER_VALUETYPE;
- t <= EVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; ++t) {
- NVT = (EVT::SimpleValueType)t;
+ for (unsigned t = MVT::FIRST_INTEGER_VALUETYPE;
+ t <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; ++t) {
+ NVT = (MVT::SimpleValueType)t;
// The source needs to big enough to hold the operand.
if (NVT.bitsGE(SVT))
LC = Signed ? RTLIB::getSINTTOFP(NVT, RVT):RTLIB::getUINTTOFP (NVT, RVT);
@@ -576,68 +576,68 @@
SDValue RHSInt = GetSoftenedFloat(NewRHS);
EVT VT = NewLHS.getValueType();
- assert((VT == EVT::f32 || VT == EVT::f64) && "Unsupported setcc type!");
+ assert((VT == MVT::f32 || VT == MVT::f64) && "Unsupported setcc type!");
// Expand into one or more soft-fp libcall(s).
RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
switch (CCCode) {
case ISD::SETEQ:
case ISD::SETOEQ:
- LC1 = (VT == EVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
+ LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
break;
case ISD::SETNE:
case ISD::SETUNE:
- LC1 = (VT == EVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
+ LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
break;
case ISD::SETGE:
case ISD::SETOGE:
- LC1 = (VT == EVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
+ LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
break;
case ISD::SETLT:
case ISD::SETOLT:
- LC1 = (VT == EVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
+ LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
break;
case ISD::SETLE:
case ISD::SETOLE:
- LC1 = (VT == EVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
+ LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
break;
case ISD::SETGT:
case ISD::SETOGT:
- LC1 = (VT == EVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
+ LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
break;
case ISD::SETUO:
- LC1 = (VT == EVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
+ LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
break;
case ISD::SETO:
- LC1 = (VT == EVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
+ LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
break;
default:
- LC1 = (VT == EVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
+ LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
switch (CCCode) {
case ISD::SETONE:
// SETONE = SETOLT | SETOGT
- LC1 = (VT == EVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
+ LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
// Fallthrough
case ISD::SETUGT:
- LC2 = (VT == EVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
+ LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
break;
case ISD::SETUGE:
- LC2 = (VT == EVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
+ LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
break;
case ISD::SETULT:
- LC2 = (VT == EVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
+ LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
break;
case ISD::SETULE:
- LC2 = (VT == EVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
+ LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
break;
case ISD::SETUEQ:
- LC2 = (VT == EVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
+ LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
break;
default: assert(false && "Do not know how to soften this setcc!");
}
}
- EVT RetVT = EVT::i32; // FIXME: is this the correct return type?
+ EVT RetVT = MVT::i32; // FIXME: is this the correct return type?
SDValue Ops[2] = { LHSInt, RHSInt };
NewLHS = MakeLibCall(LC1, RetVT, Ops, 2, false/*sign irrelevant*/, dl);
NewRHS = DAG.getConstant(0, RetVT);
@@ -841,7 +841,7 @@
void DAGTypeLegalizer::ExpandFloatRes_FABS(SDNode *N, SDValue &Lo,
SDValue &Hi) {
- assert(N->getValueType(0) == EVT::ppcf128 &&
+ assert(N->getValueType(0) == MVT::ppcf128 &&
"Logic only correct for ppcf128!");
DebugLoc dl = N->getDebugLoc();
SDValue Tmp;
@@ -1088,7 +1088,7 @@
void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo,
SDValue &Hi) {
- assert(N->getValueType(0) == EVT::ppcf128 && "Unsupported XINT_TO_FP!");
+ assert(N->getValueType(0) == MVT::ppcf128 && "Unsupported XINT_TO_FP!");
EVT VT = N->getValueType(0);
EVT NVT = TLI.getTypeToTransformTo(VT);
SDValue Src = N->getOperand(0);
@@ -1099,20 +1099,20 @@
// First do an SINT_TO_FP, whether the original was signed or unsigned.
// When promoting partial word types to i32 we must honor the signedness,
// though.
- if (SrcVT.bitsLE(EVT::i32)) {
+ if (SrcVT.bitsLE(MVT::i32)) {
// The integer can be represented exactly in an f64.
Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
- EVT::i32, Src);
+ MVT::i32, Src);
Lo = DAG.getConstantFP(APFloat(APInt(NVT.getSizeInBits(), 0)), NVT);
Hi = DAG.getNode(ISD::SINT_TO_FP, dl, NVT, Src);
} else {
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- if (SrcVT.bitsLE(EVT::i64)) {
+ if (SrcVT.bitsLE(MVT::i64)) {
Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
- EVT::i64, Src);
+ MVT::i64, Src);
LC = RTLIB::SINTTOFP_I64_PPCF128;
- } else if (SrcVT.bitsLE(EVT::i128)) {
- Src = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i128, Src);
+ } else if (SrcVT.bitsLE(MVT::i128)) {
+ Src = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i128, Src);
LC = RTLIB::SINTTOFP_I128_PPCF128;
}
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XINT_TO_FP!");
@@ -1134,23 +1134,23 @@
static const uint64_t TwoE128[] = { 0x47f0000000000000LL, 0 };
const uint64_t *Parts = 0;
- switch (SrcVT.getSimpleVT()) {
+ switch (SrcVT.getSimpleVT().SimpleTy) {
default:
assert(false && "Unsupported UINT_TO_FP!");
- case EVT::i32:
+ case MVT::i32:
Parts = TwoE32;
break;
- case EVT::i64:
+ case MVT::i64:
Parts = TwoE64;
break;
- case EVT::i128:
+ case MVT::i128:
Parts = TwoE128;
break;
}
Lo = DAG.getNode(ISD::FADD, dl, VT, Hi,
DAG.getConstantFP(APFloat(APInt(128, 2, Parts)),
- EVT::ppcf128));
+ MVT::ppcf128));
Lo = DAG.getNode(ISD::SELECT_CC, dl, VT, Src, DAG.getConstant(0, SrcVT),
Lo, Hi, DAG.getCondCode(ISD::SETLT));
GetPairElements(Lo, Lo, Hi);
@@ -1223,7 +1223,7 @@
GetExpandedFloat(NewRHS, RHSLo, RHSHi);
EVT VT = NewLHS.getValueType();
- assert(VT == EVT::ppcf128 && "Unsupported setcc type!");
+ assert(VT == MVT::ppcf128 && "Unsupported setcc type!");
// FIXME: This generated code sucks. We want to generate
// FCMPU crN, hi1, hi2
@@ -1264,7 +1264,7 @@
}
SDValue DAGTypeLegalizer::ExpandFloatOp_FP_ROUND(SDNode *N) {
- assert(N->getOperand(0).getValueType() == EVT::ppcf128 &&
+ assert(N->getOperand(0).getValueType() == MVT::ppcf128 &&
"Logic only correct for ppcf128!");
SDValue Lo, Hi;
GetExpandedFloat(N->getOperand(0), Lo, Hi);
@@ -1279,14 +1279,14 @@
// Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
// PPC (the libcall is not available). FIXME: Do this in a less hacky way.
- if (RVT == EVT::i32) {
- assert(N->getOperand(0).getValueType() == EVT::ppcf128 &&
+ if (RVT == MVT::i32) {
+ assert(N->getOperand(0).getValueType() == MVT::ppcf128 &&
"Logic only correct for ppcf128!");
- SDValue Res = DAG.getNode(ISD::FP_ROUND_INREG, dl, EVT::ppcf128,
- N->getOperand(0), DAG.getValueType(EVT::f64));
- Res = DAG.getNode(ISD::FP_ROUND, dl, EVT::f64, Res,
+ SDValue Res = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128,
+ N->getOperand(0), DAG.getValueType(MVT::f64));
+ Res = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Res,
DAG.getIntPtrConstant(1));
- return DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, Res);
+ return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res);
}
RTLIB::Libcall LC = RTLIB::getFPTOSINT(N->getOperand(0).getValueType(), RVT);
@@ -1300,24 +1300,24 @@
// Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
// PPC (the libcall is not available). FIXME: Do this in a less hacky way.
- if (RVT == EVT::i32) {
- assert(N->getOperand(0).getValueType() == EVT::ppcf128 &&
+ if (RVT == MVT::i32) {
+ assert(N->getOperand(0).getValueType() == MVT::ppcf128 &&
"Logic only correct for ppcf128!");
const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
APFloat APF = APFloat(APInt(128, 2, TwoE31));
- SDValue Tmp = DAG.getConstantFP(APF, EVT::ppcf128);
+ SDValue Tmp = DAG.getConstantFP(APF, MVT::ppcf128);
// X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
// FIXME: generated code sucks.
- return DAG.getNode(ISD::SELECT_CC, dl, EVT::i32, N->getOperand(0), Tmp,
- DAG.getNode(ISD::ADD, dl, EVT::i32,
- DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32,
+ return DAG.getNode(ISD::SELECT_CC, dl, MVT::i32, N->getOperand(0), Tmp,
+ DAG.getNode(ISD::ADD, dl, MVT::i32,
+ DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32,
DAG.getNode(ISD::FSUB, dl,
- EVT::ppcf128,
+ MVT::ppcf128,
N->getOperand(0),
Tmp)),
- DAG.getConstant(0x80000000, EVT::i32)),
+ DAG.getConstant(0x80000000, MVT::i32)),
DAG.getNode(ISD::FP_TO_SINT, dl,
- EVT::i32, N->getOperand(0)),
+ MVT::i32, N->getOperand(0)),
DAG.getCondCode(ISD::SETGE));
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Tue Aug 11 15:47:22 2009
@@ -718,7 +718,7 @@
assert(OpNo == 1 && "only know how to promote condition");
// Promote all the way up to the canonical SetCC type.
- EVT SVT = TLI.getSetCCResultType(EVT::Other);
+ EVT SVT = TLI.getSetCCResultType(MVT::Other);
SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
// The chain (Op#0) and basic block destination (Op#2) are always legal types.
@@ -802,7 +802,7 @@
NewOps[0] = N->getOperand(0);
for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
SDValue Flag = GetPromotedInteger(N->getOperand(i));
- NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, EVT::i1);
+ NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
}
return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
array_lengthof(NewOps));
@@ -1009,7 +1009,7 @@
TLI.isOperationLegalOrCustom(ISD::ADDC,
TLI.getTypeToExpandTo(NVT))) {
// Emit this X << 1 as X+X.
- SDVTList VTList = DAG.getVTList(NVT, EVT::Flag);
+ SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
SDValue LoOps[2] = { InL, InL };
Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
@@ -1237,7 +1237,7 @@
// Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
// them. TODO: Teach operation legalization how to expand unsupported
// ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
- // a carry of type EVT::Flag, but there doesn't seem to be any way to
+ // a carry of type MVT::Flag, but there doesn't seem to be any way to
// generate a value of this type in the expanded code sequence.
bool hasCarry =
TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
@@ -1245,7 +1245,7 @@
TLI.getTypeToExpandTo(NVT));
if (hasCarry) {
- SDVTList VTList = DAG.getVTList(NVT, EVT::Flag);
+ SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
if (N->getOpcode() == ISD::ADD) {
Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
HiOps[2] = Lo.getValue(1);
@@ -1290,7 +1290,7 @@
DebugLoc dl = N->getDebugLoc();
GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
- SDVTList VTList = DAG.getVTList(LHSL.getValueType(), EVT::Flag);
+ SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
SDValue LoOps[2] = { LHSL, RHSL };
SDValue HiOps[3] = { LHSH, RHSH };
@@ -1316,7 +1316,7 @@
DebugLoc dl = N->getDebugLoc();
GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
- SDVTList VTList = DAG.getVTList(LHSL.getValueType(), EVT::Flag);
+ SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
SDValue HiOps[3] = { LHSH, RHSH };
@@ -1539,7 +1539,7 @@
// Build a factor node to remember that this load is independent of the
// other one.
- Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
+ Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
} else {
// Big-endian - high bits are at low addresses. Favor aligned loads at
@@ -1565,7 +1565,7 @@
// Build a factor node to remember that this load is independent of the
// other one.
- Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
+ Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
if (ExcessBits < NVT.getSizeInBits()) {
@@ -1673,13 +1673,13 @@
// If nothing else, we can make a libcall.
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- if (VT == EVT::i16)
+ if (VT == MVT::i16)
LC = RTLIB::MUL_I16;
- else if (VT == EVT::i32)
+ else if (VT == MVT::i32)
LC = RTLIB::MUL_I32;
- else if (VT == EVT::i64)
+ else if (VT == MVT::i64)
LC = RTLIB::MUL_I64;
- else if (VT == EVT::i128)
+ else if (VT == MVT::i128)
LC = RTLIB::MUL_I128;
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
@@ -1693,13 +1693,13 @@
DebugLoc dl = N->getDebugLoc();
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- if (VT == EVT::i16)
+ if (VT == MVT::i16)
LC = RTLIB::SDIV_I16;
- else if (VT == EVT::i32)
+ else if (VT == MVT::i32)
LC = RTLIB::SDIV_I32;
- else if (VT == EVT::i64)
+ else if (VT == MVT::i64)
LC = RTLIB::SDIV_I64;
- else if (VT == EVT::i128)
+ else if (VT == MVT::i128)
LC = RTLIB::SDIV_I128;
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
@@ -1755,34 +1755,34 @@
bool isSigned;
if (N->getOpcode() == ISD::SHL) {
isSigned = false; /*sign irrelevant*/
- if (VT == EVT::i16)
+ if (VT == MVT::i16)
LC = RTLIB::SHL_I16;
- else if (VT == EVT::i32)
+ else if (VT == MVT::i32)
LC = RTLIB::SHL_I32;
- else if (VT == EVT::i64)
+ else if (VT == MVT::i64)
LC = RTLIB::SHL_I64;
- else if (VT == EVT::i128)
+ else if (VT == MVT::i128)
LC = RTLIB::SHL_I128;
} else if (N->getOpcode() == ISD::SRL) {
isSigned = false;
- if (VT == EVT::i16)
+ if (VT == MVT::i16)
LC = RTLIB::SRL_I16;
- else if (VT == EVT::i32)
+ else if (VT == MVT::i32)
LC = RTLIB::SRL_I32;
- else if (VT == EVT::i64)
+ else if (VT == MVT::i64)
LC = RTLIB::SRL_I64;
- else if (VT == EVT::i128)
+ else if (VT == MVT::i128)
LC = RTLIB::SRL_I128;
} else {
assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
isSigned = true;
- if (VT == EVT::i16)
+ if (VT == MVT::i16)
LC = RTLIB::SRA_I16;
- else if (VT == EVT::i32)
+ else if (VT == MVT::i32)
LC = RTLIB::SRA_I32;
- else if (VT == EVT::i64)
+ else if (VT == MVT::i64)
LC = RTLIB::SRA_I64;
- else if (VT == EVT::i128)
+ else if (VT == MVT::i128)
LC = RTLIB::SRA_I128;
}
@@ -1857,13 +1857,13 @@
DebugLoc dl = N->getDebugLoc();
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- if (VT == EVT::i16)
+ if (VT == MVT::i16)
LC = RTLIB::SREM_I16;
- else if (VT == EVT::i32)
+ else if (VT == MVT::i32)
LC = RTLIB::SREM_I32;
- else if (VT == EVT::i64)
+ else if (VT == MVT::i64)
LC = RTLIB::SREM_I64;
- else if (VT == EVT::i128)
+ else if (VT == MVT::i128)
LC = RTLIB::SREM_I128;
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
@@ -1888,13 +1888,13 @@
DebugLoc dl = N->getDebugLoc();
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- if (VT == EVT::i16)
+ if (VT == MVT::i16)
LC = RTLIB::UDIV_I16;
- else if (VT == EVT::i32)
+ else if (VT == MVT::i32)
LC = RTLIB::UDIV_I32;
- else if (VT == EVT::i64)
+ else if (VT == MVT::i64)
LC = RTLIB::UDIV_I64;
- else if (VT == EVT::i128)
+ else if (VT == MVT::i128)
LC = RTLIB::UDIV_I128;
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
@@ -1908,13 +1908,13 @@
DebugLoc dl = N->getDebugLoc();
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- if (VT == EVT::i16)
+ if (VT == MVT::i16)
LC = RTLIB::UREM_I16;
- else if (VT == EVT::i32)
+ else if (VT == MVT::i32)
LC = RTLIB::UREM_I32;
- else if (VT == EVT::i64)
+ else if (VT == MVT::i64)
LC = RTLIB::UREM_I64;
- else if (VT == EVT::i128)
+ else if (VT == MVT::i128)
LC = RTLIB::UREM_I128;
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
@@ -2222,7 +2222,7 @@
Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
SVOffset+IncrementSize, NEVT,
isVolatile, MinAlign(Alignment, IncrementSize));
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
} else {
// Big-endian - high bits are at low addresses. Favor aligned stores at
// the cost of some bit-fiddling.
@@ -2257,7 +2257,7 @@
SVOffset+IncrementSize,
EVT::getIntegerVT(ExcessBits),
isVolatile, MinAlign(Alignment, IncrementSize));
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
}
}
@@ -2288,11 +2288,11 @@
const uint64_t F32TwoE128 = 0x7F800000ULL;
APInt FF(32, 0);
- if (SrcVT == EVT::i32)
+ if (SrcVT == MVT::i32)
FF = APInt(32, F32TwoE32);
- else if (SrcVT == EVT::i64)
+ else if (SrcVT == MVT::i64)
FF = APInt(32, F32TwoE64);
- else if (SrcVT == EVT::i128)
+ else if (SrcVT == MVT::i128)
FF = APInt(32, F32TwoE128);
else
assert(false && "Unsupported UINT_TO_FP!");
@@ -2323,7 +2323,7 @@
// Load the value out, extending it from f32 to the destination float type.
// FIXME: Avoid the extend by constructing the right constant pool?
SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
- FudgePtr, NULL, 0, EVT::f32,
+ FudgePtr, NULL, 0, MVT::f32,
false, Alignment);
return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Tue Aug 11 15:47:22 2009
@@ -159,7 +159,7 @@
explicit DAGTypeLegalizer(SelectionDAG &dag)
: TLI(dag.getTargetLoweringInfo()), DAG(dag),
ValueTypeActions(TLI.getValueTypeActions()) {
- assert(EVT::LAST_VALUETYPE <= EVT::MAX_ALLOWED_VALUETYPE &&
+ assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
"Too many value types for ValueTypeActions to hold!");
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp Tue Aug 11 15:47:22 2009
@@ -220,7 +220,7 @@
// Build a factor node to remember that this load is independent of the
// other one.
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
// Handle endianness of the load.
@@ -402,7 +402,7 @@
SVOffset + IncrementSize,
isVolatile, MinAlign(Alignment, IncrementSize));
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp Tue Aug 11 15:47:22 2009
@@ -306,7 +306,7 @@
Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
OperandEltVT,
Operand,
- DAG.getConstant(i, EVT::i32));
+ DAG.getConstant(i, MVT::i32));
} else {
// A scalar operand; just use it as is.
Operands[j] = Operand;
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Tue Aug 11 15:47:22 2009
@@ -213,7 +213,7 @@
DebugLoc DL = N->getDebugLoc();
// Turn it into a scalar SETCC.
- return DAG.getNode(ISD::SETCC, DL, EVT::i1, LHS, RHS, N->getOperand(2));
+ return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
}
SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
@@ -247,16 +247,16 @@
if (TLI.getBooleanContents() !=
TargetLowering::ZeroOrNegativeOneBooleanContent)
Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, SVT, Res,
- DAG.getValueType(EVT::i1));
+ DAG.getValueType(MVT::i1));
// Truncate to the final type.
return DAG.getNode(ISD::TRUNCATE, DL, NVT, Res);
}
// The SETCC result type is smaller than the vector element type.
- // If the SetCC result is not sign-extended, chop it down to EVT::i1.
+ // If the SetCC result is not sign-extended, chop it down to MVT::i1.
if (TLI.getBooleanContents() !=
TargetLowering::ZeroOrNegativeOneBooleanContent)
- Res = DAG.getNode(ISD::TRUNCATE, DL, EVT::i1, Res);
+ Res = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Res);
// Sign extend to the final type.
return DAG.getNode(ISD::SIGN_EXTEND, DL, NVT, Res);
}
@@ -725,7 +725,7 @@
// Build a factor node to remember that this load is independent of the
// other one.
- Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
+ Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
// Legalized the chain result - switch anything that used the old chain to
@@ -1097,7 +1097,7 @@
Hi = DAG.getStore(Ch, dl, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
isVol, MinAlign(Alignment, IncrementSize));
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
}
@@ -1660,7 +1660,7 @@
if (LdChain.size() == 1)
NewChain = LdChain[0];
else
- NewChain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &LdChain[0],
+ NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LdChain[0],
LdChain.size());
// Modified the chain - switch anything that used the old chain to use
@@ -1941,7 +1941,7 @@
return StChain[0];
else
return DAG.getNode(ISD::TokenFactor, dl,
- EVT::Other,&StChain[0],StChain.size());
+ MVT::Other,&StChain[0],StChain.size());
}
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp Tue Aug 11 15:47:22 2009
@@ -216,15 +216,15 @@
bool TryUnfold = false;
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
EVT VT = N->getValueType(i);
- if (VT == EVT::Flag)
+ if (VT == MVT::Flag)
return NULL;
- else if (VT == EVT::Other)
+ else if (VT == MVT::Other)
TryUnfold = true;
}
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
const SDValue &Op = N->getOperand(i);
EVT VT = Op.getNode()->getValueType(Op.getResNo());
- if (VT == EVT::Flag)
+ if (VT == MVT::Flag)
return NULL;
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Tue Aug 11 15:47:22 2009
@@ -353,15 +353,15 @@
bool TryUnfold = false;
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
EVT VT = N->getValueType(i);
- if (VT == EVT::Flag)
+ if (VT == MVT::Flag)
return NULL;
- else if (VT == EVT::Other)
+ else if (VT == MVT::Other)
TryUnfold = true;
}
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
const SDValue &Op = N->getOperand(i);
EVT VT = Op.getNode()->getValueType(Op.getResNo());
- if (VT == EVT::Flag)
+ if (VT == MVT::Flag)
return NULL;
}
@@ -630,7 +630,7 @@
if (Node->getOpcode() == ISD::INLINEASM) {
// Inline asm can clobber physical defs.
unsigned NumOps = Node->getNumOperands();
- if (Node->getOperand(NumOps-1).getValueType() == EVT::Flag)
+ if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
--NumOps; // Ignore the flag operand.
for (unsigned i = 2; i != NumOps;) {
@@ -1217,7 +1217,7 @@
return false;
for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
EVT VT = N->getValueType(i);
- if (VT == EVT::Flag || VT == EVT::Other)
+ if (VT == MVT::Flag || VT == MVT::Other)
continue;
if (!N->hasAnyUseOfValue(i))
continue;
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Tue Aug 11 15:47:22 2009
@@ -111,7 +111,7 @@
// Scan up to find flagged preds.
SDNode *N = NI;
while (N->getNumOperands() &&
- N->getOperand(N->getNumOperands()-1).getValueType() == EVT::Flag) {
+ N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
N = N->getOperand(N->getNumOperands()-1).getNode();
assert(N->getNodeId() == -1 && "Node already inserted!");
N->setNodeId(NodeSUnit->NodeNum);
@@ -119,7 +119,7 @@
// Scan down to find any flagged succs.
N = NI;
- while (N->getValueType(N->getNumValues()-1) == EVT::Flag) {
+ while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
SDValue FlagVal(N, N->getNumValues()-1);
// There are either zero or one users of the Flag result.
@@ -190,8 +190,8 @@
if (OpSU == SU) continue; // In the same group.
EVT OpVT = N->getOperand(i).getValueType();
- assert(OpVT != EVT::Flag && "Flagged nodes should be in same sunit!");
- bool isChain = OpVT == EVT::Other;
+ assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
+ bool isChain = OpVT == MVT::Other;
unsigned PhysReg = 0;
int Cost = 1;
@@ -244,9 +244,9 @@
/// not go into the resulting MachineInstr).
unsigned ScheduleDAGSDNodes::CountResults(SDNode *Node) {
unsigned N = Node->getNumValues();
- while (N && Node->getValueType(N - 1) == EVT::Flag)
+ while (N && Node->getValueType(N - 1) == MVT::Flag)
--N;
- if (N && Node->getValueType(N - 1) == EVT::Other)
+ if (N && Node->getValueType(N - 1) == MVT::Other)
--N; // Skip over chain result.
return N;
}
@@ -266,9 +266,9 @@
/// operand
unsigned ScheduleDAGSDNodes::ComputeMemOperandsEnd(SDNode *Node) {
unsigned N = Node->getNumOperands();
- while (N && Node->getOperand(N - 1).getValueType() == EVT::Flag)
+ while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
--N;
- if (N && Node->getOperand(N - 1).getValueType() == EVT::Other)
+ if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
--N; // Ignore chain if it exists.
return N;
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp Tue Aug 11 15:47:22 2009
@@ -70,7 +70,7 @@
if (Op.getNode() != Node || Op.getResNo() != ResNo)
continue;
EVT VT = Node->getValueType(Op.getResNo());
- if (VT == EVT::Other || VT == EVT::Flag)
+ if (VT == MVT::Other || VT == MVT::Flag)
continue;
Match = false;
if (User->isMachineOpcode()) {
@@ -238,8 +238,8 @@
unsigned IIOpNum,
const TargetInstrDesc *II,
DenseMap<SDValue, unsigned> &VRBaseMap) {
- assert(Op.getValueType() != EVT::Other &&
- Op.getValueType() != EVT::Flag &&
+ assert(Op.getValueType() != MVT::Other &&
+ Op.getValueType() != MVT::Flag &&
"Chain and flag operands should occur at end of operand list!");
// Get/emit the operand.
unsigned VReg = getVR(Op, VRBaseMap);
@@ -322,8 +322,8 @@
MI->addOperand(MachineOperand::CreateES(ES->getSymbol(), 0,
ES->getTargetFlags()));
} else {
- assert(Op.getValueType() != EVT::Other &&
- Op.getValueType() != EVT::Flag &&
+ assert(Op.getValueType() != MVT::Other &&
+ Op.getValueType() != MVT::Flag &&
"Chain and flag operands should occur at end of operand list!");
AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap);
}
@@ -599,7 +599,7 @@
}
case ISD::INLINEASM: {
unsigned NumOps = Node->getNumOperands();
- if (Node->getOperand(NumOps-1).getValueType() == EVT::Flag)
+ if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
--NumOps; // Ignore the flag operand.
// Create the inline asm machine instruction.
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Aug 11 15:47:22 2009
@@ -54,13 +54,13 @@
}
static const fltSemantics *EVTToAPFloatSemantics(EVT VT) {
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unknown FP format");
- case EVT::f32: return &APFloat::IEEEsingle;
- case EVT::f64: return &APFloat::IEEEdouble;
- case EVT::f80: return &APFloat::x87DoubleExtended;
- case EVT::f128: return &APFloat::IEEEquad;
- case EVT::ppcf128: return &APFloat::PPCDoubleDouble;
+ case MVT::f32: return &APFloat::IEEEsingle;
+ case MVT::f64: return &APFloat::IEEEdouble;
+ case MVT::f80: return &APFloat::x87DoubleExtended;
+ case MVT::f128: return &APFloat::IEEEquad;
+ case MVT::ppcf128: return &APFloat::PPCDoubleDouble;
}
}
@@ -83,7 +83,7 @@
assert(VT.isFloatingPoint() && "Can only convert between FP types");
// PPC long double cannot be converted to any other type.
- if (VT == EVT::ppcf128 ||
+ if (VT == MVT::ppcf128 ||
&Val.getSemantics() == &APFloat::PPCDoubleDouble)
return false;
@@ -503,7 +503,7 @@
/// doNotCSE - Return true if CSE should not be performed for this node.
static bool doNotCSE(SDNode *N) {
- if (N->getValueType(0) == EVT::Flag)
+ if (N->getValueType(0) == MVT::Flag)
return true; // Never CSE anything that produces a flag.
switch (N->getOpcode()) {
@@ -518,7 +518,7 @@
// Check that remaining values produced are not flags.
for (unsigned i = 1, e = N->getNumValues(); i != e; ++i)
- if (N->getValueType(i) == EVT::Flag)
+ if (N->getValueType(i) == MVT::Flag)
return true; // Never CSE anything that produces a flag.
return false;
@@ -643,8 +643,8 @@
if (VT.isExtended()) {
Erased = ExtendedValueTypeNodes.erase(VT);
} else {
- Erased = ValueTypeNodes[VT.getSimpleVT()] != 0;
- ValueTypeNodes[VT.getSimpleVT()] = 0;
+ Erased = ValueTypeNodes[VT.getSimpleVT().SimpleTy] != 0;
+ ValueTypeNodes[VT.getSimpleVT().SimpleTy] = 0;
}
break;
}
@@ -657,7 +657,7 @@
// Verify that the node was actually in one of the CSE maps, unless it has a
// flag result (which cannot be CSE'd) or is one of the special cases that are
// not subject to CSE.
- if (!Erased && N->getValueType(N->getNumValues()-1) != EVT::Flag &&
+ if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag &&
!N->isMachineOpcode() && !doNotCSE(N)) {
N->dump(this);
cerr << "\n";
@@ -788,7 +788,7 @@
/// given type.
///
unsigned SelectionDAG::getEVTAlignment(EVT VT) const {
- const Type *Ty = VT == EVT::iPTR ?
+ const Type *Ty = VT == MVT::iPTR ?
PointerType::get(Type::Int8Ty, 0) :
VT.getTypeForEVT();
@@ -799,7 +799,7 @@
SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli)
: TLI(tli), FLI(fli), DW(0),
EntryNode(ISD::EntryToken, DebugLoc::getUnknownLoc(),
- getVTList(EVT::Other)), Root(getEntryNode()) {
+ getVTList(MVT::Other)), Root(getEntryNode()) {
AllNodes.push_back(&EntryNode);
}
@@ -950,7 +950,7 @@
SDValue SelectionDAG::getConstantFP(double Val, EVT VT, bool isTarget) {
EVT EltVT =
VT.isVector() ? VT.getVectorElementType() : VT;
- if (EltVT==EVT::f32)
+ if (EltVT==MVT::f32)
return getConstantFP(APFloat((float)Val), VT, isTarget);
else
return getConstantFP(APFloat(Val), VT, isTarget);
@@ -1084,7 +1084,7 @@
SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) {
FoldingSetNodeID ID;
- AddNodeIDNode(ID, ISD::BasicBlock, getVTList(EVT::Other), 0, 0);
+ AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0);
ID.AddPointer(MBB);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
@@ -1097,11 +1097,12 @@
}
SDValue SelectionDAG::getValueType(EVT VT) {
- if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size())
- ValueTypeNodes.resize(VT.getSimpleVT()+1);
+ if (VT.isSimple() && (unsigned)VT.getSimpleVT().SimpleTy >=
+ ValueTypeNodes.size())
+ ValueTypeNodes.resize(VT.getSimpleVT().SimpleTy+1);
SDNode *&N = VT.isExtended() ?
- ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()];
+ ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT().SimpleTy];
if (N) return SDValue(N, 0);
N = NodeAllocator.Allocate<VTSDNode>();
@@ -1299,7 +1300,7 @@
unsigned LabelID) {
FoldingSetNodeID ID;
SDValue Ops[] = { Root };
- AddNodeIDNode(ID, Opcode, getVTList(EVT::Other), &Ops[0], 1);
+ AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1);
ID.AddInteger(LabelID);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
@@ -1316,7 +1317,7 @@
"SrcValue is not a pointer?");
FoldingSetNodeID ID;
- AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(EVT::Other), 0, 0);
+ AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0);
ID.AddPointer(V);
void *IP = 0;
@@ -1338,7 +1339,7 @@
#endif
FoldingSetNodeID ID;
- AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(EVT::Other), 0, 0);
+ AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0);
MO.Profile(ID);
void *IP = 0;
@@ -1439,7 +1440,7 @@
if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) {
// No compile time operations on this type yet.
- if (N1C->getValueType(0) == EVT::ppcf128)
+ if (N1C->getValueType(0) == MVT::ppcf128)
return SDValue();
APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF());
@@ -2277,7 +2278,7 @@
case ISD::SINT_TO_FP: {
const uint64_t zero[] = {0, 0};
// No compile time operations on this type.
- if (VT==EVT::ppcf128)
+ if (VT==MVT::ppcf128)
break;
APFloat apf = APFloat(APInt(BitWidth, 2, zero));
(void)apf.convertFromAPInt(Val,
@@ -2286,9 +2287,9 @@
return getConstantFP(apf, VT);
}
case ISD::BIT_CONVERT:
- if (VT == EVT::f32 && C->getValueType(0) == EVT::i32)
+ if (VT == MVT::f32 && C->getValueType(0) == MVT::i32)
return getConstantFP(Val.bitsToFloat(), VT);
- else if (VT == EVT::f64 && C->getValueType(0) == EVT::i64)
+ else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64)
return getConstantFP(Val.bitsToDouble(), VT);
break;
case ISD::BSWAP:
@@ -2305,7 +2306,7 @@
// Constant fold unary operations with a floating point constant operand.
if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) {
APFloat V = C->getValueAPF(); // make copy
- if (VT != EVT::ppcf128 && Operand.getValueType() != EVT::ppcf128) {
+ if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) {
switch (Opcode) {
case ISD::FNEG:
V.changeSign();
@@ -2337,9 +2338,9 @@
return getConstant(api, VT);
}
case ISD::BIT_CONVERT:
- if (VT == EVT::i32 && C->getValueType(0) == EVT::f32)
+ if (VT == MVT::i32 && C->getValueType(0) == MVT::f32)
return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT);
- else if (VT == EVT::i64 && C->getValueType(0) == EVT::f64)
+ else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64)
return getConstant(V.bitcastToAPInt().getZExtValue(), VT);
break;
}
@@ -2450,7 +2451,7 @@
SDNode *N;
SDVTList VTs = getVTList(VT);
- if (VT != EVT::Flag) { // Don't CSE flag producing nodes
+ if (VT != MVT::Flag) { // Don't CSE flag producing nodes
FoldingSetNodeID ID;
SDValue Ops[1] = { Operand };
AddNodeIDNode(ID, Opcode, VTs, Ops, 1);
@@ -2515,8 +2516,8 @@
switch (Opcode) {
default: break;
case ISD::TokenFactor:
- assert(VT == EVT::Other && N1.getValueType() == EVT::Other &&
- N2.getValueType() == EVT::Other && "Invalid token factor!");
+ assert(VT == MVT::Other && N1.getValueType() == MVT::Other &&
+ N2.getValueType() == MVT::Other && "Invalid token factor!");
// Fold trivial token factors.
if (N1.getOpcode() == ISD::EntryToken) return N2;
if (N2.getOpcode() == ISD::EntryToken) return N1;
@@ -2606,7 +2607,7 @@
// Always fold shifts of i1 values so the code generator doesn't need to
// handle them. Since we know the size of the shift has to be less than the
// size of the value, the shift/rotate count is guaranteed to be zero.
- if (VT == EVT::i1)
+ if (VT == MVT::i1)
return N1;
break;
case ISD::FP_ROUND_INREG: {
@@ -2747,7 +2748,7 @@
// Cannonicalize constant to RHS if commutative
std::swap(N1CFP, N2CFP);
std::swap(N1, N2);
- } else if (N2CFP && VT != EVT::ppcf128) {
+ } else if (N2CFP && VT != MVT::ppcf128) {
APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF();
APFloat::opStatus s;
switch (Opcode) {
@@ -2862,7 +2863,7 @@
// Memoize this node if possible.
SDNode *N;
SDVTList VTs = getVTList(VT);
- if (VT != EVT::Flag) {
+ if (VT != MVT::Flag) {
SDValue Ops[] = { N1, N2 };
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTs, Ops, 2);
@@ -2921,7 +2922,7 @@
case ISD::BRCOND:
if (N2C) {
if (N2C->getZExtValue()) // Unconditional branch
- return getNode(ISD::BR, DL, EVT::Other, N1, N3);
+ return getNode(ISD::BR, DL, MVT::Other, N1, N3);
else
return N1; // Never-taken branch
}
@@ -2939,7 +2940,7 @@
// Memoize node if it doesn't produce a flag.
SDNode *N;
SDVTList VTs = getVTList(VT);
- if (VT != EVT::Flag) {
+ if (VT != MVT::Flag) {
SDValue Ops[] = { N1, N2, N3 };
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTs, Ops, 3);
@@ -2993,7 +2994,7 @@
ArgChains.push_back(SDValue(L, 1));
// Build a tokenfactor for all the chains.
- return getNode(ISD::TokenFactor, Chain.getDebugLoc(), EVT::Other,
+ return getNode(ISD::TokenFactor, Chain.getDebugLoc(), MVT::Other,
&ArgChains[0], ArgChains.size());
}
@@ -3041,7 +3042,7 @@
if (VT.isInteger())
return DAG.getConstant(0, VT);
unsigned NumElts = VT.getVectorNumElements();
- EVT EltVT = (VT.getVectorElementType() == EVT::f32) ? EVT::i32 : EVT::i64;
+ EVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
DAG.getConstant(0, EVT::getVectorVT(EltVT, NumElts)));
}
@@ -3105,7 +3106,7 @@
bool isSrcConst = isa<ConstantSDNode>(Src);
bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses();
EVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr, DAG);
- if (VT != EVT::iAny) {
+ if (VT != MVT::iAny) {
unsigned NewAlign = (unsigned)
TLI.getTargetData()->getABITypeAlignment(VT.getTypeForEVT());
// If source is a string constant, this will require an unaligned load.
@@ -3113,14 +3114,14 @@
if (Dst.getOpcode() != ISD::FrameIndex) {
// Can't change destination alignment. It requires a unaligned store.
if (AllowUnalign)
- VT = EVT::iAny;
+ VT = MVT::iAny;
} else {
int FI = cast<FrameIndexSDNode>(Dst)->getIndex();
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
if (MFI->isFixedObjectIndex(FI)) {
// Can't change destination alignment. It requires a unaligned store.
if (AllowUnalign)
- VT = EVT::iAny;
+ VT = MVT::iAny;
} else {
// Give the stack frame object a larger alignment if needed.
if (MFI->getObjectAlignment(FI) < NewAlign)
@@ -3131,21 +3132,21 @@
}
}
- if (VT == EVT::iAny) {
+ if (VT == MVT::iAny) {
if (AllowUnalign) {
- VT = EVT::i64;
+ VT = MVT::i64;
} else {
switch (Align & 7) {
- case 0: VT = EVT::i64; break;
- case 4: VT = EVT::i32; break;
- case 2: VT = EVT::i16; break;
- default: VT = EVT::i8; break;
+ case 0: VT = MVT::i64; break;
+ case 4: VT = MVT::i32; break;
+ case 2: VT = MVT::i16; break;
+ default: VT = MVT::i8; break;
}
}
- EVT LVT = EVT::i64;
+ EVT LVT = MVT::i64;
while (!TLI.isTypeLegal(LVT))
- LVT = (EVT::SimpleValueType)(LVT.getSimpleVT() - 1);
+ LVT = (MVT::SimpleValueType)(LVT.getSimpleVT().SimpleTy - 1);
assert(LVT.isInteger());
if (VT.bitsGT(LVT))
@@ -3158,14 +3159,14 @@
while (VTSize > Size) {
// For now, only use non-vector load / store's for the left-over pieces.
if (VT.isVector()) {
- VT = EVT::i64;
+ VT = MVT::i64;
while (!TLI.isTypeLegal(VT))
- VT = (EVT::SimpleValueType)(VT.getSimpleVT() - 1);
+ VT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy - 1);
VTSize = VT.getSizeInBits() / 8;
} else {
// This can result in a type that is not legal on the target, e.g.
// 1 or 2 bytes on PPC.
- VT = (EVT::SimpleValueType)(VT.getSimpleVT() - 1);
+ VT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy - 1);
VTSize >>= 1;
}
}
@@ -3240,7 +3241,7 @@
DstOff += VTSize;
}
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&OutChains[0], OutChains.size());
}
@@ -3283,7 +3284,7 @@
LoadChains.push_back(Value.getValue(1));
SrcOff += VTSize;
}
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&LoadChains[0], LoadChains.size());
OutChains.clear();
for (unsigned i = 0; i < NumMemOps; i++) {
@@ -3298,7 +3299,7 @@
DstOff += VTSize;
}
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&OutChains[0], OutChains.size());
}
@@ -3333,7 +3334,7 @@
DstOff += VTSize;
}
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&OutChains[0], OutChains.size());
}
@@ -3478,10 +3479,10 @@
Entry.Node = Dst; Entry.Ty = IntPtrTy;
Args.push_back(Entry);
// Extend or truncate the argument to be an i32 value for the call.
- if (Src.getValueType().bitsGT(EVT::i32))
- Src = getNode(ISD::TRUNCATE, dl, EVT::i32, Src);
+ if (Src.getValueType().bitsGT(MVT::i32))
+ Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src);
else
- Src = getNode(ISD::ZERO_EXTEND, dl, EVT::i32, Src);
+ Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src);
Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
Args.push_back(Entry);
Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false;
@@ -3510,7 +3511,7 @@
if (Alignment == 0) // Ensure that codegen never sees alignment 0
Alignment = getEVTAlignment(MemVT);
- SDVTList VTs = getVTList(VT, EVT::Other);
+ SDVTList VTs = getVTList(VT, MVT::Other);
FoldingSetNodeID ID;
ID.AddInteger(MemVT.getRawBits());
SDValue Ops[] = {Chain, Ptr, Cmp, Swp};
@@ -3549,7 +3550,7 @@
if (Alignment == 0) // Ensure that codegen never sees alignment 0
Alignment = getEVTAlignment(MemVT);
- SDVTList VTs = getVTList(VT, EVT::Other);
+ SDVTList VTs = getVTList(VT, MVT::Other);
FoldingSetNodeID ID;
ID.AddInteger(MemVT.getRawBits());
SDValue Ops[] = {Chain, Ptr, Val};
@@ -3600,7 +3601,7 @@
bool ReadMem, bool WriteMem) {
// Memoize the node unless it returns a flag.
MemIntrinsicSDNode *N;
- if (VTList.VTs[VTList.NumVTs-1] != EVT::Flag) {
+ if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
void *IP = 0;
@@ -3652,7 +3653,7 @@
"Unindexed load with an offset!");
SDVTList VTs = Indexed ?
- getVTList(VT, Ptr.getValueType(), EVT::Other) : getVTList(VT, EVT::Other);
+ getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other);
SDValue Ops[] = { Chain, Ptr, Offset };
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3);
@@ -3708,7 +3709,7 @@
if (Alignment == 0) // Ensure that codegen never sees alignment 0
Alignment = getEVTAlignment(VT);
- SDVTList VTs = getVTList(EVT::Other);
+ SDVTList VTs = getVTList(MVT::Other);
SDValue Undef = getUNDEF(Ptr.getValueType());
SDValue Ops[] = { Chain, Val, Ptr, Undef };
FoldingSetNodeID ID;
@@ -3743,7 +3744,7 @@
if (Alignment == 0) // Ensure that codegen never sees alignment 0
Alignment = getEVTAlignment(VT);
- SDVTList VTs = getVTList(EVT::Other);
+ SDVTList VTs = getVTList(MVT::Other);
SDValue Undef = getUNDEF(Ptr.getValueType());
SDValue Ops[] = { Chain, Val, Ptr, Undef };
FoldingSetNodeID ID;
@@ -3768,7 +3769,7 @@
StoreSDNode *ST = cast<StoreSDNode>(OrigStore);
assert(ST->getOffset().getOpcode() == ISD::UNDEF &&
"Store is already a indexed store!");
- SDVTList VTs = getVTList(Base.getValueType(), EVT::Other);
+ SDVTList VTs = getVTList(Base.getValueType(), MVT::Other);
SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset };
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
@@ -3791,7 +3792,7 @@
SDValue Chain, SDValue Ptr,
SDValue SV) {
SDValue Ops[] = { Chain, Ptr, SV };
- return getNode(ISD::VAARG, dl, getVTList(VT, EVT::Other), Ops, 3);
+ return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 3);
}
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
@@ -3844,7 +3845,7 @@
SDNode *N;
SDVTList VTs = getVTList(VT);
- if (VT != EVT::Flag) {
+ if (VT != MVT::Flag) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps);
void *IP = 0;
@@ -3896,7 +3897,7 @@
case ISD::SRL_PARTS:
case ISD::SHL_PARTS:
if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG &&
- cast<VTSDNode>(N3.getOperand(1))->getVT() != EVT::i1)
+ cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1)
return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0));
else if (N3.getOpcode() == ISD::AND)
if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) {
@@ -3912,7 +3913,7 @@
// Memoize the node unless it returns a flag.
SDNode *N;
- if (VTList.VTs[VTList.NumVTs-1] != EVT::Flag) {
+ if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
void *IP = 0;
@@ -4407,7 +4408,7 @@
unsigned NumOps) {
// If an identical node already exists, use it.
void *IP = 0;
- if (VTs.VTs[VTs.NumVTs-1] != EVT::Flag) {
+ if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opc, VTs, Ops, NumOps);
if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP))
@@ -4581,7 +4582,7 @@
/// else return NULL.
SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList,
const SDValue *Ops, unsigned NumOps) {
- if (VTList.VTs[VTList.NumVTs-1] != EVT::Flag) {
+ if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
void *IP = 0;
@@ -4996,7 +4997,7 @@
}
static ManagedStatic<std::set<EVT, EVT::compareRawBits> > EVTs;
-static EVT VTs[EVT::LAST_VALUETYPE];
+static EVT VTs[MVT::LAST_VALUETYPE];
static ManagedStatic<sys::SmartMutex<true> > VTMutex;
/// getValueTypeList - Return a pointer to the specified value type.
@@ -5006,8 +5007,8 @@
if (VT.isExtended()) {
return &(*EVTs->insert(VT).first);
} else {
- VTs[VT.getSimpleVT()] = VT;
- return &VTs[VT.getSimpleVT()];
+ VTs[VT.getSimpleVT().SimpleTy] = VT;
+ return &VTs[VT.getSimpleVT().SimpleTy];
}
}
@@ -5449,7 +5450,7 @@
for (unsigned i = 0, e = getNumValues(); i != e; ++i) {
if (i) OS << ",";
- if (getValueType(i) == EVT::Other)
+ if (getValueType(i) == MVT::Other)
OS << "ch";
else
OS << getValueType(i).getEVTString();
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Tue Aug 11 15:47:22 2009
@@ -496,11 +496,11 @@
ValueVT, &Ops[0], NumIntermediates);
} else if (PartVT.isFloatingPoint()) {
// FP split into multiple FP parts (for ppcf128)
- assert(ValueVT == EVT(EVT::ppcf128) && PartVT == EVT(EVT::f64) &&
+ assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
"Unexpected split");
SDValue Lo, Hi;
- Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(EVT::f64), Parts[0]);
- Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(EVT::f64), Parts[1]);
+ Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[0]);
+ Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[1]);
if (TLI.isBigEndian())
std::swap(Lo, Hi);
Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi);
@@ -774,7 +774,7 @@
}
// Otherwise, we have to make a token factor node.
- SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), EVT::Other,
+ SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
&PendingLoads[0], PendingLoads.size());
PendingLoads.clear();
DAG.setRoot(Root);
@@ -804,7 +804,7 @@
PendingExports.push_back(Root);
}
- Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), EVT::Other,
+ Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
&PendingExports[0],
PendingExports.size());
PendingExports.clear();
@@ -961,7 +961,7 @@
// conventions. The frontend should mark functions whose return values
// require promoting with signext or zeroext attributes.
if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
- EVT MinVT = TLI.getRegisterType(EVT::i32);
+ EVT MinVT = TLI.getRegisterType(MVT::i32);
if (VT.bitsLT(MinVT))
VT = MinVT;
}
@@ -995,7 +995,7 @@
Outs, getCurDebugLoc(), DAG);
// Verify that the target's LowerReturn behaved as expected.
- assert(Chain.getNode() && Chain.getValueType() == EVT::Other &&
+ assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
"LowerReturn didn't return a valid chain!");
// Update the DAG with the new chain value resulting from return lowering.
@@ -1250,7 +1250,7 @@
// If this is not a fall-through branch, emit the branch.
if (Succ0MBB != NextBlock)
DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
- EVT::Other, getControlRoot(),
+ MVT::Other, getControlRoot(),
DAG.getBasicBlock(Succ0MBB)));
return;
}
@@ -1334,7 +1334,7 @@
SDValue True = DAG.getConstant(1, CondLHS.getValueType());
Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
} else
- Cond = DAG.getSetCC(dl, EVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
+ Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
} else {
assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
@@ -1345,12 +1345,12 @@
EVT VT = CmpOp.getValueType();
if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
- Cond = DAG.getSetCC(dl, EVT::i1, CmpOp, DAG.getConstant(High, VT),
+ Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
ISD::SETLE);
} else {
SDValue SUB = DAG.getNode(ISD::SUB, dl,
VT, CmpOp, DAG.getConstant(Low, VT));
- Cond = DAG.getSetCC(dl, EVT::i1, SUB,
+ Cond = DAG.getSetCC(dl, MVT::i1, SUB,
DAG.getConstant(High-Low, VT), ISD::SETULE);
}
}
@@ -1374,7 +1374,7 @@
Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
}
SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
- EVT::Other, getControlRoot(), Cond,
+ MVT::Other, getControlRoot(), Cond,
DAG.getBasicBlock(CB.TrueBB));
// If the branch was constant folded, fix up the CFG.
@@ -1389,7 +1389,7 @@
if (CB.FalseBB == NextBlock)
DAG.setRoot(BrCond);
else
- DAG.setRoot(DAG.getNode(ISD::BR, dl, EVT::Other, BrCond,
+ DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
DAG.getBasicBlock(CB.FalseBB)));
}
}
@@ -1403,7 +1403,7 @@
JT.Reg, PTy);
SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
- EVT::Other, Index.getValue(1),
+ MVT::Other, Index.getValue(1),
Table, Index));
}
@@ -1452,13 +1452,13 @@
NextBlock = BBI;
SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
- EVT::Other, CopyTo, CMP,
+ MVT::Other, CopyTo, CMP,
DAG.getBasicBlock(JT.Default));
if (JT.MBB == NextBlock)
DAG.setRoot(BrCond);
else
- DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), EVT::Other, BrCond,
+ DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
DAG.getBasicBlock(JT.MBB)));
}
@@ -1502,13 +1502,13 @@
CurMBB->addSuccessor(MBB);
SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
- EVT::Other, CopyTo, RangeCmp,
+ MVT::Other, CopyTo, RangeCmp,
DAG.getBasicBlock(B.Default));
if (MBB == NextBlock)
DAG.setRoot(BrRange);
else
- DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), EVT::Other, CopyTo,
+ DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
DAG.getBasicBlock(MBB)));
}
@@ -1537,7 +1537,7 @@
CurMBB->addSuccessor(NextMBB);
SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
- EVT::Other, getControlRoot(),
+ MVT::Other, getControlRoot(),
AndCmp, DAG.getBasicBlock(B.TargetBB));
// Set NextBlock to be the MBB immediately after the current one, if any.
@@ -1550,7 +1550,7 @@
if (NextMBB == NextBlock)
DAG.setRoot(BrAnd);
else
- DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), EVT::Other, BrAnd,
+ DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
DAG.getBasicBlock(NextMBB)));
}
@@ -1575,7 +1575,7 @@
// Drop into normal successor.
DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
- EVT::Other, getControlRoot(),
+ MVT::Other, getControlRoot(),
DAG.getBasicBlock(Return)));
}
@@ -1669,8 +1669,8 @@
static inline bool areJTsAllowed(const TargetLowering &TLI) {
return !DisableJumpTables &&
- (TLI.isOperationLegalOrCustom(ISD::BR_JT, EVT::Other) ||
- TLI.isOperationLegalOrCustom(ISD::BRIND, EVT::Other));
+ (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
+ TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
}
static APInt ComputeRange(const APInt &First, const APInt &Last) {
@@ -2096,7 +2096,7 @@
CurMBB->addSuccessor(Default);
if (Default != NextBlock)
DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
- EVT::Other, getControlRoot(),
+ MVT::Other, getControlRoot(),
DAG.getBasicBlock(Default)));
return;
}
@@ -2680,7 +2680,7 @@
if (PtrBits < 64) {
OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
TLI.getPointerTy(),
- DAG.getConstant(Offs, EVT::i64));
+ DAG.getConstant(Offs, MVT::i64));
} else
OffsVal = DAG.getIntPtrConstant(Offs);
N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
@@ -2770,7 +2770,7 @@
DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
- SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), EVT::Other);
+ SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
VTs, Ops, 3);
setValue(&I, DSA);
@@ -2826,7 +2826,7 @@
if (!ConstantMemory) {
SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
- EVT::Other,
+ MVT::Other,
&Chains[0], NumValues);
if (isVolatile)
DAG.setRoot(Chain);
@@ -2872,7 +2872,7 @@
isVolatile, Alignment);
DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
- EVT::Other, &Chains[0], NumValues));
+ MVT::Other, &Chains[0], NumValues));
}
/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
@@ -2918,7 +2918,7 @@
}
#endif // NDEBUG
if (HasChain)
- ValueVTs.push_back(EVT::Other);
+ ValueVTs.push_back(MVT::Other);
SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
@@ -3033,11 +3033,11 @@
/// where Op is the hexidecimal representation of floating point value.
static SDValue
GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
- SDValue t1 = DAG.getNode(ISD::AND, dl, EVT::i32, Op,
- DAG.getConstant(0x007fffff, EVT::i32));
- SDValue t2 = DAG.getNode(ISD::OR, dl, EVT::i32, t1,
- DAG.getConstant(0x3f800000, EVT::i32));
- return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t2);
+ SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
+ DAG.getConstant(0x007fffff, MVT::i32));
+ SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
+ DAG.getConstant(0x3f800000, MVT::i32));
+ return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
}
/// GetExponent - Get the exponent:
@@ -3048,19 +3048,19 @@
static SDValue
GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
DebugLoc dl) {
- SDValue t0 = DAG.getNode(ISD::AND, dl, EVT::i32, Op,
- DAG.getConstant(0x7f800000, EVT::i32));
- SDValue t1 = DAG.getNode(ISD::SRL, dl, EVT::i32, t0,
+ SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
+ DAG.getConstant(0x7f800000, MVT::i32));
+ SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
DAG.getConstant(23, TLI.getPointerTy()));
- SDValue t2 = DAG.getNode(ISD::SUB, dl, EVT::i32, t1,
- DAG.getConstant(127, EVT::i32));
- return DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, t2);
+ SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
+ DAG.getConstant(127, MVT::i32));
+ return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
}
/// getF32Constant - Get 32-bit floating point constant.
static SDValue
getF32Constant(SelectionDAG &DAG, unsigned Flt) {
- return DAG.getConstantFP(APFloat(APInt(32, Flt)), EVT::f32);
+ return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
}
/// Inlined utility function to implement binary input atomic intrinsics for
@@ -3087,7 +3087,7 @@
SDValue Op1 = getValue(I.getOperand(1));
SDValue Op2 = getValue(I.getOperand(2));
- SDVTList VTs = DAG.getVTList(Op1.getValueType(), EVT::i1);
+ SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
SDValue Result = DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2);
setValue(&I, Result);
@@ -3101,7 +3101,7 @@
SDValue result;
DebugLoc dl = getCurDebugLoc();
- if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
+ if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getOperand(1));
@@ -3110,16 +3110,16 @@
//
// #define LOG2OFe 1.4426950f
// IntegerPartOfX = ((int32_t)(X * LOG2OFe));
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, Op,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
getF32Constant(DAG, 0x3fb8aa3b));
- SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, t0);
+ SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
// FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
- SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, IntegerPartOfX);
- SDValue X = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0, t1);
+ SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
+ SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
// IntegerPartOfX <<= 23;
- IntegerPartOfX = DAG.getNode(ISD::SHL, dl, EVT::i32, IntegerPartOfX,
+ IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
DAG.getConstant(23, TLI.getPointerTy()));
if (LimitFloatPrecision <= 6) {
@@ -3130,20 +3130,20 @@
// (0.735607626f + 0.252464424f * x) * x;
//
// error 0.0144103317, which is 6 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0x3e814304));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3f3c50c8));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3f7f5e7e));
- SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,EVT::i32, t5);
+ SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
// Add the exponent into the result in integer domain.
- SDValue t6 = DAG.getNode(ISD::ADD, dl, EVT::i32,
+ SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
TwoToFracPartOfX, IntegerPartOfX);
- result = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t6);
+ result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
@@ -3153,23 +3153,23 @@
// (0.224338339f + 0.792043434e-1f * x) * x) * x;
//
// 0.000107046256 error, which is 13 to 14 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0x3da235e3));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3e65b8f3));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3f324b07));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
getF32Constant(DAG, 0x3f7ff8fd));
- SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,EVT::i32, t7);
+ SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
// Add the exponent into the result in integer domain.
- SDValue t8 = DAG.getNode(ISD::ADD, dl, EVT::i32,
+ SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
TwoToFracPartOfX, IntegerPartOfX);
- result = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t8);
+ result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
@@ -3182,33 +3182,33 @@
// (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
//
// error 2.47208000*10^(-7), which is better than 18 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0x3924b03e));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3ab24b87));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3c1d8c17));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
getF32Constant(DAG, 0x3d634a1d));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
- SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
+ SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
getF32Constant(DAG, 0x3e75fe14));
- SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
- SDValue t11 = DAG.getNode(ISD::FADD, dl, EVT::f32, t10,
+ SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
+ SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
getF32Constant(DAG, 0x3f317234));
- SDValue t12 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t11, X);
- SDValue t13 = DAG.getNode(ISD::FADD, dl, EVT::f32, t12,
+ SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
+ SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
getF32Constant(DAG, 0x3f800000));
SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
- EVT::i32, t13);
+ MVT::i32, t13);
// Add the exponent into the result in integer domain.
- SDValue t14 = DAG.getNode(ISD::ADD, dl, EVT::i32,
+ SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
TwoToFracPartOfX, IntegerPartOfX);
- result = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t14);
+ result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
}
} else {
// No special expansion.
@@ -3227,14 +3227,14 @@
SDValue result;
DebugLoc dl = getCurDebugLoc();
- if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
+ if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getOperand(1));
- SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op);
+ SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
// Scale the exponent by log(2) [0.69314718f].
SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
- SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, EVT::f32, Exp,
+ SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
getF32Constant(DAG, 0x3f317218));
// Get the significand and build it into a floating-point number with
@@ -3249,16 +3249,16 @@
// (1.4034025f - 0.23903021f * x) * x;
//
// error 0.0034276066, which is better than 8 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0xbe74c456));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
getF32Constant(DAG, 0x3fb3a2b1));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
- SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+ SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3f949a29));
result = DAG.getNode(ISD::FADD, dl,
- EVT::f32, LogOfExponent, LogOfMantissa);
+ MVT::f32, LogOfExponent, LogOfMantissa);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
@@ -3269,22 +3269,22 @@
// (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
//
// error 0.000061011436, which is 14 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0xbd67b6d6));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
getF32Constant(DAG, 0x3ee4f4b8));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3fbc278b));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x40348e95));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
- SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+ SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
getF32Constant(DAG, 0x3fdef31a));
result = DAG.getNode(ISD::FADD, dl,
- EVT::f32, LogOfExponent, LogOfMantissa);
+ MVT::f32, LogOfExponent, LogOfMantissa);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
@@ -3297,28 +3297,28 @@
// (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
//
// error 0.0000023660568, which is better than 18 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0xbc91e5ac));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
getF32Constant(DAG, 0x3e4350aa));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3f60d3e3));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x4011cdf0));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
getF32Constant(DAG, 0x406cfd1c));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
- SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
+ SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
getF32Constant(DAG, 0x408797cb));
- SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
- SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t10,
+ SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
+ SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
getF32Constant(DAG, 0x4006dcab));
result = DAG.getNode(ISD::FADD, dl,
- EVT::f32, LogOfExponent, LogOfMantissa);
+ MVT::f32, LogOfExponent, LogOfMantissa);
}
} else {
// No special expansion.
@@ -3337,10 +3337,10 @@
SDValue result;
DebugLoc dl = getCurDebugLoc();
- if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
+ if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getOperand(1));
- SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op);
+ SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
// Get the exponent.
SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
@@ -3357,16 +3357,16 @@
// Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
//
// error 0.0049451742, which is more than 7 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0xbeb08fe0));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
getF32Constant(DAG, 0x40019463));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
- SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+ SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3fd6633d));
result = DAG.getNode(ISD::FADD, dl,
- EVT::f32, LogOfExponent, Log2ofMantissa);
+ MVT::f32, LogOfExponent, Log2ofMantissa);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
@@ -3377,22 +3377,22 @@
// (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
//
// error 0.0000876136000, which is better than 13 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0xbda7262e));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
getF32Constant(DAG, 0x3f25280b));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
getF32Constant(DAG, 0x4007b923));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x40823e2f));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
- SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+ SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
getF32Constant(DAG, 0x4020d29c));
result = DAG.getNode(ISD::FADD, dl,
- EVT::f32, LogOfExponent, Log2ofMantissa);
+ MVT::f32, LogOfExponent, Log2ofMantissa);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
@@ -3406,28 +3406,28 @@
// 0.25691327e-1f * x) * x) * x) * x) * x) * x;
//
// error 0.0000018516, which is better than 18 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0xbcd2769e));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
getF32Constant(DAG, 0x3e8ce0b9));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3fa22ae7));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x40525723));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
getF32Constant(DAG, 0x40aaf200));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
- SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
+ SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
getF32Constant(DAG, 0x40c39dad));
- SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
- SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t10,
+ SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
+ SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
getF32Constant(DAG, 0x4042902c));
result = DAG.getNode(ISD::FADD, dl,
- EVT::f32, LogOfExponent, Log2ofMantissa);
+ MVT::f32, LogOfExponent, Log2ofMantissa);
}
} else {
// No special expansion.
@@ -3446,14 +3446,14 @@
SDValue result;
DebugLoc dl = getCurDebugLoc();
- if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
+ if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getOperand(1));
- SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op);
+ SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
// Scale the exponent by log10(2) [0.30102999f].
SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
- SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, EVT::f32, Exp,
+ SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
getF32Constant(DAG, 0x3e9a209a));
// Get the significand and build it into a floating-point number with
@@ -3468,16 +3468,16 @@
// (0.60948995f - 0.10380950f * x) * x;
//
// error 0.0014886165, which is 6 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0xbdd49a13));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
getF32Constant(DAG, 0x3f1c0789));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
- SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+ SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3f011300));
result = DAG.getNode(ISD::FADD, dl,
- EVT::f32, LogOfExponent, Log10ofMantissa);
+ MVT::f32, LogOfExponent, Log10ofMantissa);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
@@ -3487,19 +3487,19 @@
// (-0.31664806f + 0.47637168e-1f * x) * x) * x;
//
// error 0.00019228036, which is better than 12 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0x3d431f31));
- SDValue t1 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
getF32Constant(DAG, 0x3ea21fb2));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3f6ae232));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3f25f7c3));
result = DAG.getNode(ISD::FADD, dl,
- EVT::f32, LogOfExponent, Log10ofMantissa);
+ MVT::f32, LogOfExponent, Log10ofMantissa);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
@@ -3511,25 +3511,25 @@
// (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
//
// error 0.0000037995730, which is better than 18 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0x3c5d51ce));
- SDValue t1 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
getF32Constant(DAG, 0x3e00685a));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3efb6798));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3f88d192));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
getF32Constant(DAG, 0x3fc4316c));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
- SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
+ SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
getF32Constant(DAG, 0x3f57ce70));
result = DAG.getNode(ISD::FADD, dl,
- EVT::f32, LogOfExponent, Log10ofMantissa);
+ MVT::f32, LogOfExponent, Log10ofMantissa);
}
} else {
// No special expansion.
@@ -3548,18 +3548,18 @@
SDValue result;
DebugLoc dl = getCurDebugLoc();
- if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
+ if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getOperand(1));
- SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, Op);
+ SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
// FractionalPartOfX = x - (float)IntegerPartOfX;
- SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, IntegerPartOfX);
- SDValue X = DAG.getNode(ISD::FSUB, dl, EVT::f32, Op, t1);
+ SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
+ SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
// IntegerPartOfX <<= 23;
- IntegerPartOfX = DAG.getNode(ISD::SHL, dl, EVT::i32, IntegerPartOfX,
+ IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
DAG.getConstant(23, TLI.getPointerTy()));
if (LimitFloatPrecision <= 6) {
@@ -3570,19 +3570,19 @@
// (0.735607626f + 0.252464424f * x) * x;
//
// error 0.0144103317, which is 6 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0x3e814304));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3f3c50c8));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3f7f5e7e));
- SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t5);
+ SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, EVT::i32, t6, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- EVT::f32, TwoToFractionalPartOfX);
+ MVT::f32, TwoToFractionalPartOfX);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
@@ -3592,22 +3592,22 @@
// (0.224338339f + 0.792043434e-1f * x) * x) * x;
//
// error 0.000107046256, which is 13 to 14 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0x3da235e3));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3e65b8f3));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3f324b07));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
getF32Constant(DAG, 0x3f7ff8fd));
- SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t7);
+ SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, EVT::i32, t8, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- EVT::f32, TwoToFractionalPartOfX);
+ MVT::f32, TwoToFractionalPartOfX);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
@@ -3619,31 +3619,31 @@
// (0.961591928e-2f +
// (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
// error 2.47208000*10^(-7), which is better than 18 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0x3924b03e));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3ab24b87));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3c1d8c17));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
getF32Constant(DAG, 0x3d634a1d));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
- SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
+ SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
getF32Constant(DAG, 0x3e75fe14));
- SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
- SDValue t11 = DAG.getNode(ISD::FADD, dl, EVT::f32, t10,
+ SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
+ SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
getF32Constant(DAG, 0x3f317234));
- SDValue t12 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t11, X);
- SDValue t13 = DAG.getNode(ISD::FADD, dl, EVT::f32, t12,
+ SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
+ SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
getF32Constant(DAG, 0x3f800000));
- SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t13);
+ SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, EVT::i32, t14, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- EVT::f32, TwoToFractionalPartOfX);
+ MVT::f32, TwoToFractionalPartOfX);
}
} else {
// No special expansion.
@@ -3664,8 +3664,8 @@
DebugLoc dl = getCurDebugLoc();
bool IsExp10 = false;
- if (getValue(Val).getValueType() == EVT::f32 &&
- getValue(I.getOperand(2)).getValueType() == EVT::f32 &&
+ if (getValue(Val).getValueType() == MVT::f32 &&
+ getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
@@ -3683,16 +3683,16 @@
//
// #define LOG2OF10 3.3219281f
// IntegerPartOfX = (int32_t)(x * LOG2OF10);
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, Op,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
getF32Constant(DAG, 0x40549a78));
- SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, t0);
+ SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
// FractionalPartOfX = x - (float)IntegerPartOfX;
- SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, IntegerPartOfX);
- SDValue X = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0, t1);
+ SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
+ SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
// IntegerPartOfX <<= 23;
- IntegerPartOfX = DAG.getNode(ISD::SHL, dl, EVT::i32, IntegerPartOfX,
+ IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
DAG.getConstant(23, TLI.getPointerTy()));
if (LimitFloatPrecision <= 6) {
@@ -3703,19 +3703,19 @@
// (0.735607626f + 0.252464424f * x) * x;
//
// error 0.0144103317, which is 6 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0x3e814304));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3f3c50c8));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3f7f5e7e));
- SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t5);
+ SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, EVT::i32, t6, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- EVT::f32, TwoToFractionalPartOfX);
+ MVT::f32, TwoToFractionalPartOfX);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
@@ -3725,22 +3725,22 @@
// (0.224338339f + 0.792043434e-1f * x) * x) * x;
//
// error 0.000107046256, which is 13 to 14 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0x3da235e3));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3e65b8f3));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3f324b07));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
getF32Constant(DAG, 0x3f7ff8fd));
- SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t7);
+ SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, EVT::i32, t8, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- EVT::f32, TwoToFractionalPartOfX);
+ MVT::f32, TwoToFractionalPartOfX);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
@@ -3752,31 +3752,31 @@
// (0.961591928e-2f +
// (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
// error 2.47208000*10^(-7), which is better than 18 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
getF32Constant(DAG, 0x3924b03e));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
getF32Constant(DAG, 0x3ab24b87));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
getF32Constant(DAG, 0x3c1d8c17));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
getF32Constant(DAG, 0x3d634a1d));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
- SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
+ SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
getF32Constant(DAG, 0x3e75fe14));
- SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
- SDValue t11 = DAG.getNode(ISD::FADD, dl, EVT::f32, t10,
+ SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
+ SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
getF32Constant(DAG, 0x3f317234));
- SDValue t12 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t11, X);
- SDValue t13 = DAG.getNode(ISD::FADD, dl, EVT::f32, t12,
+ SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
+ SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
getF32Constant(DAG, 0x3f800000));
- SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t13);
+ SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, EVT::i32, t14, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- EVT::f32, TwoToFractionalPartOfX);
+ MVT::f32, TwoToFractionalPartOfX);
}
} else {
// No special expansion.
@@ -3973,14 +3973,14 @@
return 0;
Value *Variable = DI.getVariable();
- DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, EVT::Other, getRoot(),
+ DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
getValue(DI.getAddress()), getValue(Variable)));
return 0;
}
case Intrinsic::eh_exception: {
// Insert the EXCEPTIONADDR instruction.
assert(CurMBB->isLandingPad() &&"Call to eh.exception not in landing pad!");
- SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), EVT::Other);
+ SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
SDValue Ops[1];
Ops[0] = DAG.getRoot();
SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
@@ -3993,7 +3993,7 @@
case Intrinsic::eh_selector_i64: {
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
EVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
- EVT::i32 : EVT::i64);
+ MVT::i32 : MVT::i64);
if (MMI) {
if (CurMBB->isLandingPad())
@@ -4008,7 +4008,7 @@
}
// Insert the EHSELECTION instruction.
- SDVTList VTs = DAG.getVTList(VT, EVT::Other);
+ SDVTList VTs = DAG.getVTList(VT, MVT::Other);
SDValue Ops[2];
Ops[0] = getValue(I.getOperand(1));
Ops[1] = getRoot();
@@ -4026,7 +4026,7 @@
case Intrinsic::eh_typeid_for_i64: {
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
EVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
- EVT::i32 : EVT::i64);
+ MVT::i32 : MVT::i64);
if (MMI) {
// Find the type id for the given typeinfo.
@@ -4047,7 +4047,7 @@
if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
MMI->setCallsEHReturn(true);
DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
- EVT::Other,
+ MVT::Other,
getControlRoot(),
getValue(I.getOperand(1)),
getValue(I.getOperand(2))));
@@ -4165,13 +4165,13 @@
return 0;
case Intrinsic::pcmarker: {
SDValue Tmp = getValue(I.getOperand(1));
- DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, EVT::Other, getRoot(), Tmp));
+ DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
return 0;
}
case Intrinsic::readcyclecounter: {
SDValue Op = getRoot();
SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
- DAG.getVTList(EVT::i64, EVT::Other),
+ DAG.getVTList(MVT::i64, MVT::Other),
&Op, 1);
setValue(&I, Tmp);
DAG.setRoot(Tmp.getValue(1));
@@ -4206,14 +4206,14 @@
case Intrinsic::stacksave: {
SDValue Op = getRoot();
SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
- DAG.getVTList(TLI.getPointerTy(), EVT::Other), &Op, 1);
+ DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
setValue(&I, Tmp);
DAG.setRoot(Tmp.getValue(1));
return 0;
}
case Intrinsic::stackrestore: {
SDValue Tmp = getValue(I.getOperand(1));
- DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, EVT::Other, getRoot(), Tmp));
+ DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
return 0;
}
case Intrinsic::stackprotector: {
@@ -4254,7 +4254,7 @@
Ops[5] = DAG.getSrcValue(F);
SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
- DAG.getVTList(TLI.getPointerTy(), EVT::Other),
+ DAG.getVTList(TLI.getPointerTy(), MVT::Other),
Ops, 6);
setValue(&I, Tmp);
@@ -4278,12 +4278,12 @@
return 0;
case Intrinsic::flt_rounds: {
- setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, EVT::i32));
+ setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
return 0;
}
case Intrinsic::trap: {
- DAG.setRoot(DAG.getNode(ISD::TRAP, dl,EVT::Other, getRoot()));
+ DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
return 0;
}
@@ -4306,7 +4306,7 @@
Ops[1] = getValue(I.getOperand(1));
Ops[2] = getValue(I.getOperand(2));
Ops[3] = getValue(I.getOperand(3));
- DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, EVT::Other, &Ops[0], 4));
+ DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
return 0;
}
@@ -4316,7 +4316,7 @@
for (int x = 1; x < 6; ++x)
Ops[x] = getValue(I.getOperand(x));
- DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, EVT::Other, &Ops[0], 6));
+ DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
return 0;
}
case Intrinsic::atomic_cmp_swap: {
@@ -4639,25 +4639,25 @@
// FIXME: We capture more information than the dag can represent. For
// now, just use the tightest assertzext/assertsext possible.
bool isSExt = true;
- EVT FromVT(EVT::Other);
+ EVT FromVT(MVT::Other);
if (NumSignBits == RegSize)
- isSExt = true, FromVT = EVT::i1; // ASSERT SEXT 1
+ isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
else if (NumZeroBits >= RegSize-1)
- isSExt = false, FromVT = EVT::i1; // ASSERT ZEXT 1
+ isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
else if (NumSignBits > RegSize-8)
- isSExt = true, FromVT = EVT::i8; // ASSERT SEXT 8
+ isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
else if (NumZeroBits >= RegSize-8)
- isSExt = false, FromVT = EVT::i8; // ASSERT ZEXT 8
+ isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
else if (NumSignBits > RegSize-16)
- isSExt = true, FromVT = EVT::i16; // ASSERT SEXT 16
+ isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
else if (NumZeroBits >= RegSize-16)
- isSExt = false, FromVT = EVT::i16; // ASSERT ZEXT 16
+ isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
else if (NumSignBits > RegSize-32)
- isSExt = true, FromVT = EVT::i32; // ASSERT SEXT 32
+ isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
else if (NumZeroBits >= RegSize-32)
- isSExt = false, FromVT = EVT::i32; // ASSERT ZEXT 32
+ isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
- if (FromVT != EVT::Other) {
+ if (FromVT != MVT::Other) {
P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
RegisterVT, P, DAG.getValueType(FromVT));
@@ -4724,7 +4724,7 @@
// = op c3, ..., f2
Chain = Chains[NumRegs-1];
else
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &Chains[0], NumRegs);
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
}
/// AddInlineAsmOperands - Add this value to the specified inlineasm node
@@ -4757,11 +4757,11 @@
isAllocatableRegister(unsigned Reg, MachineFunction &MF,
const TargetLowering &TLI,
const TargetRegisterInfo *TRI) {
- EVT FoundVT = EVT::Other;
+ EVT FoundVT = MVT::Other;
const TargetRegisterClass *FoundRC = 0;
for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
E = TRI->regclass_end(); RCI != E; ++RCI) {
- EVT ThisVT = EVT::Other;
+ EVT ThisVT = MVT::Other;
const TargetRegisterClass *RC = *RCI;
// If none of the the value types for this register class are valid, we
@@ -4772,14 +4772,14 @@
// If we have already found this register in a different register class,
// choose the one with the largest VT specified. For example, on
// PowerPC, we favor f64 register classes over f32.
- if (FoundVT == EVT::Other || FoundVT.bitsLT(*I)) {
+ if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
ThisVT = *I;
break;
}
}
}
- if (ThisVT == EVT::Other) continue;
+ if (ThisVT == MVT::Other) continue;
// NOTE: This isn't ideal. In particular, this might allocate the
// frame pointer in functions that need it (due to them not being taken
@@ -4836,10 +4836,10 @@
/// getCallOperandValEVT - Return the EVT of the Value* that this operand
/// corresponds to. If there is no Value* for this operand, it returns
- /// EVT::Other.
+ /// MVT::Other.
EVT getCallOperandValEVT(const TargetLowering &TLI,
const TargetData *TD) const {
- if (CallOperandVal == 0) return EVT::Other;
+ if (CallOperandVal == 0) return MVT::Other;
if (isa<BasicBlock>(CallOperandVal))
return TLI.getPointerTy();
@@ -4932,7 +4932,7 @@
OpInfo.ConstraintVT);
unsigned NumRegs = 1;
- if (OpInfo.ConstraintVT != EVT::Other) {
+ if (OpInfo.ConstraintVT != MVT::Other) {
// If this is a FP input in an integer register (or visa versa) insert a bit
// cast of the input value. More generally, handle any case where the input
// value disagrees with the register class we plan to stick this in.
@@ -4968,7 +4968,7 @@
// assign it now.
if (unsigned AssignedReg = PhysReg.first) {
const TargetRegisterClass *RC = PhysReg.second;
- if (OpInfo.ConstraintVT == EVT::Other)
+ if (OpInfo.ConstraintVT == MVT::Other)
ValueVT = *RC->vt_begin();
// Get the actual register value type. This is important, because the user
@@ -5002,7 +5002,7 @@
// for this reference.
if (const TargetRegisterClass *RC = PhysReg.second) {
RegVT = *RC->vt_begin();
- if (OpInfo.ConstraintVT == EVT::Other)
+ if (OpInfo.ConstraintVT == MVT::Other)
ValueVT = RegVT;
// Create the appropriate number of virtual registers.
@@ -5116,7 +5116,7 @@
ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
- EVT OpVT = EVT::Other;
+ EVT OpVT = MVT::Other;
// Compute the value type for each operand.
switch (OpInfo.Type) {
@@ -5252,7 +5252,7 @@
std::vector<SDValue> AsmNodeOperands;
AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
AsmNodeOperands.push_back(
- DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), EVT::Other));
+ DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
// Loop over all of the inputs, copying the operand values into the
@@ -5440,7 +5440,7 @@
if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
- DAG.getVTList(EVT::Other, EVT::Flag),
+ DAG.getVTList(MVT::Other, MVT::Flag),
&AsmNodeOperands[0], AsmNodeOperands.size());
Flag = Chain.getValue(1);
@@ -5501,7 +5501,7 @@
getValue(StoresToEmit[i].second),
StoresToEmit[i].second, 0));
if (!OutChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
&OutChains[0], OutChains.size());
DAG.setRoot(Chain);
}
@@ -5518,7 +5518,7 @@
uint64_t ElementSize = TD->getTypeAllocSize(I.getType()->getElementType());
if (ElementSize != 1) {
// Src is always 32-bits, make sure the constant fits.
- assert(Src.getValueType() == EVT::i32);
+ assert(Src.getValueType() == MVT::i32);
ElementSize = (uint32_t)ElementSize;
Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(),
Src, DAG.getConstant(ElementSize, Src.getValueType()));
@@ -5572,7 +5572,7 @@
void SelectionDAGLowering::visitVAStart(CallInst &I) {
DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
- EVT::Other, getRoot(),
+ MVT::Other, getRoot(),
getValue(I.getOperand(1)),
DAG.getSrcValue(I.getOperand(1))));
}
@@ -5587,14 +5587,14 @@
void SelectionDAGLowering::visitVAEnd(CallInst &I) {
DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
- EVT::Other, getRoot(),
+ MVT::Other, getRoot(),
getValue(I.getOperand(1)),
DAG.getSrcValue(I.getOperand(1))));
}
void SelectionDAGLowering::visitVACopy(CallInst &I) {
DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
- EVT::Other, getRoot(),
+ MVT::Other, getRoot(),
getValue(I.getOperand(1)),
getValue(I.getOperand(2)),
DAG.getSrcValue(I.getOperand(1)),
@@ -5715,7 +5715,7 @@
Outs, Ins, dl, DAG, InVals);
// Verify that the target's LowerCall behaved as expected.
- assert(Chain.getNode() && Chain.getValueType() == EVT::Other &&
+ assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
"LowerCall didn't return a valid chain!");
assert((!isTailCall || InVals.empty()) &&
"LowerCall emitted a return value for a tail call!");
@@ -5871,7 +5871,7 @@
dl, DAG, InVals);
// Verify that the target's LowerFormalArguments behaved as expected.
- assert(NewRoot.getNode() && NewRoot.getValueType() == EVT::Other &&
+ assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
"LowerFormalArguments didn't return a valid chain!");
assert(InVals.size() == Ins.size() &&
"LowerFormalArguments didn't emit the correct number of values!");
@@ -6039,9 +6039,9 @@
// use CreateRegForValue to create registers, so it always creates
// exactly one register for each non-void instruction.
EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
- if (VT == EVT::Other || !TLI.isTypeLegal(VT)) {
- // Promote EVT::i1.
- if (VT == EVT::i1)
+ if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
+ // Promote MVT::i1.
+ if (VT == MVT::i1)
VT = TLI.getTypeToTransformTo(VT);
else {
SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Aug 11 15:47:22 2009
@@ -421,7 +421,7 @@
// Otherwise, add all chain operands to the worklist.
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
- if (N->getOperand(i).getValueType() == EVT::Other)
+ if (N->getOperand(i).getValueType() == MVT::Other)
Worklist.push_back(N->getOperand(i).getNode());
// If this is a CopyToReg with a vreg dest, process it.
@@ -1098,7 +1098,7 @@
Ops.push_back(InOps[1]); // input asm string.
unsigned i = 2, e = InOps.size();
- if (InOps[e-1].getValueType() == EVT::Flag)
+ if (InOps[e-1].getValueType() == MVT::Flag)
--e; // Don't process a flag operand if it is here.
while (i != e) {
@@ -1236,7 +1236,7 @@
// a cycle in the scheduling graph.
EVT VT = Root->getValueType(Root->getNumValues()-1);
- while (VT == EVT::Flag) {
+ while (VT == MVT::Flag) {
SDNode *FU = findFlagUse(Root);
if (FU == NULL)
break;
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp Tue Aug 11 15:47:22 2009
@@ -85,9 +85,9 @@
static std::string getEdgeAttributes(const void *Node, EdgeIter EI) {
SDValue Op = EI.getNode()->getOperand(EI.getOperand());
EVT VT = Op.getValueType();
- if (VT == EVT::Flag)
+ if (VT == MVT::Flag)
return "color=red,style=bold";
- else if (VT == EVT::Other)
+ else if (VT == MVT::Other)
return "color=blue,style=dashed";
return "";
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Tue Aug 11 15:47:22 2009
@@ -250,8 +250,8 @@
/// getFPEXT - Return the FPEXT_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
- if (OpVT == EVT::f32) {
- if (RetVT == EVT::f64)
+ if (OpVT == MVT::f32) {
+ if (RetVT == MVT::f64)
return FPEXT_F32_F64;
}
return UNKNOWN_LIBCALL;
@@ -260,17 +260,17 @@
/// getFPROUND - Return the FPROUND_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
- if (RetVT == EVT::f32) {
- if (OpVT == EVT::f64)
+ if (RetVT == MVT::f32) {
+ if (OpVT == MVT::f64)
return FPROUND_F64_F32;
- if (OpVT == EVT::f80)
+ if (OpVT == MVT::f80)
return FPROUND_F80_F32;
- if (OpVT == EVT::ppcf128)
+ if (OpVT == MVT::ppcf128)
return FPROUND_PPCF128_F32;
- } else if (RetVT == EVT::f64) {
- if (OpVT == EVT::f80)
+ } else if (RetVT == MVT::f64) {
+ if (OpVT == MVT::f80)
return FPROUND_F80_F64;
- if (OpVT == EVT::ppcf128)
+ if (OpVT == MVT::ppcf128)
return FPROUND_PPCF128_F64;
}
return UNKNOWN_LIBCALL;
@@ -279,37 +279,37 @@
/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
- if (OpVT == EVT::f32) {
- if (RetVT == EVT::i8)
+ if (OpVT == MVT::f32) {
+ if (RetVT == MVT::i8)
return FPTOSINT_F32_I8;
- if (RetVT == EVT::i16)
+ if (RetVT == MVT::i16)
return FPTOSINT_F32_I16;
- if (RetVT == EVT::i32)
+ if (RetVT == MVT::i32)
return FPTOSINT_F32_I32;
- if (RetVT == EVT::i64)
+ if (RetVT == MVT::i64)
return FPTOSINT_F32_I64;
- if (RetVT == EVT::i128)
+ if (RetVT == MVT::i128)
return FPTOSINT_F32_I128;
- } else if (OpVT == EVT::f64) {
- if (RetVT == EVT::i32)
+ } else if (OpVT == MVT::f64) {
+ if (RetVT == MVT::i32)
return FPTOSINT_F64_I32;
- if (RetVT == EVT::i64)
+ if (RetVT == MVT::i64)
return FPTOSINT_F64_I64;
- if (RetVT == EVT::i128)
+ if (RetVT == MVT::i128)
return FPTOSINT_F64_I128;
- } else if (OpVT == EVT::f80) {
- if (RetVT == EVT::i32)
+ } else if (OpVT == MVT::f80) {
+ if (RetVT == MVT::i32)
return FPTOSINT_F80_I32;
- if (RetVT == EVT::i64)
+ if (RetVT == MVT::i64)
return FPTOSINT_F80_I64;
- if (RetVT == EVT::i128)
+ if (RetVT == MVT::i128)
return FPTOSINT_F80_I128;
- } else if (OpVT == EVT::ppcf128) {
- if (RetVT == EVT::i32)
+ } else if (OpVT == MVT::ppcf128) {
+ if (RetVT == MVT::i32)
return FPTOSINT_PPCF128_I32;
- if (RetVT == EVT::i64)
+ if (RetVT == MVT::i64)
return FPTOSINT_PPCF128_I64;
- if (RetVT == EVT::i128)
+ if (RetVT == MVT::i128)
return FPTOSINT_PPCF128_I128;
}
return UNKNOWN_LIBCALL;
@@ -318,37 +318,37 @@
/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
- if (OpVT == EVT::f32) {
- if (RetVT == EVT::i8)
+ if (OpVT == MVT::f32) {
+ if (RetVT == MVT::i8)
return FPTOUINT_F32_I8;
- if (RetVT == EVT::i16)
+ if (RetVT == MVT::i16)
return FPTOUINT_F32_I16;
- if (RetVT == EVT::i32)
+ if (RetVT == MVT::i32)
return FPTOUINT_F32_I32;
- if (RetVT == EVT::i64)
+ if (RetVT == MVT::i64)
return FPTOUINT_F32_I64;
- if (RetVT == EVT::i128)
+ if (RetVT == MVT::i128)
return FPTOUINT_F32_I128;
- } else if (OpVT == EVT::f64) {
- if (RetVT == EVT::i32)
+ } else if (OpVT == MVT::f64) {
+ if (RetVT == MVT::i32)
return FPTOUINT_F64_I32;
- if (RetVT == EVT::i64)
+ if (RetVT == MVT::i64)
return FPTOUINT_F64_I64;
- if (RetVT == EVT::i128)
+ if (RetVT == MVT::i128)
return FPTOUINT_F64_I128;
- } else if (OpVT == EVT::f80) {
- if (RetVT == EVT::i32)
+ } else if (OpVT == MVT::f80) {
+ if (RetVT == MVT::i32)
return FPTOUINT_F80_I32;
- if (RetVT == EVT::i64)
+ if (RetVT == MVT::i64)
return FPTOUINT_F80_I64;
- if (RetVT == EVT::i128)
+ if (RetVT == MVT::i128)
return FPTOUINT_F80_I128;
- } else if (OpVT == EVT::ppcf128) {
- if (RetVT == EVT::i32)
+ } else if (OpVT == MVT::ppcf128) {
+ if (RetVT == MVT::i32)
return FPTOUINT_PPCF128_I32;
- if (RetVT == EVT::i64)
+ if (RetVT == MVT::i64)
return FPTOUINT_PPCF128_I64;
- if (RetVT == EVT::i128)
+ if (RetVT == MVT::i128)
return FPTOUINT_PPCF128_I128;
}
return UNKNOWN_LIBCALL;
@@ -357,32 +357,32 @@
/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
- if (OpVT == EVT::i32) {
- if (RetVT == EVT::f32)
+ if (OpVT == MVT::i32) {
+ if (RetVT == MVT::f32)
return SINTTOFP_I32_F32;
- else if (RetVT == EVT::f64)
+ else if (RetVT == MVT::f64)
return SINTTOFP_I32_F64;
- else if (RetVT == EVT::f80)
+ else if (RetVT == MVT::f80)
return SINTTOFP_I32_F80;
- else if (RetVT == EVT::ppcf128)
+ else if (RetVT == MVT::ppcf128)
return SINTTOFP_I32_PPCF128;
- } else if (OpVT == EVT::i64) {
- if (RetVT == EVT::f32)
+ } else if (OpVT == MVT::i64) {
+ if (RetVT == MVT::f32)
return SINTTOFP_I64_F32;
- else if (RetVT == EVT::f64)
+ else if (RetVT == MVT::f64)
return SINTTOFP_I64_F64;
- else if (RetVT == EVT::f80)
+ else if (RetVT == MVT::f80)
return SINTTOFP_I64_F80;
- else if (RetVT == EVT::ppcf128)
+ else if (RetVT == MVT::ppcf128)
return SINTTOFP_I64_PPCF128;
- } else if (OpVT == EVT::i128) {
- if (RetVT == EVT::f32)
+ } else if (OpVT == MVT::i128) {
+ if (RetVT == MVT::f32)
return SINTTOFP_I128_F32;
- else if (RetVT == EVT::f64)
+ else if (RetVT == MVT::f64)
return SINTTOFP_I128_F64;
- else if (RetVT == EVT::f80)
+ else if (RetVT == MVT::f80)
return SINTTOFP_I128_F80;
- else if (RetVT == EVT::ppcf128)
+ else if (RetVT == MVT::ppcf128)
return SINTTOFP_I128_PPCF128;
}
return UNKNOWN_LIBCALL;
@@ -391,32 +391,32 @@
/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
- if (OpVT == EVT::i32) {
- if (RetVT == EVT::f32)
+ if (OpVT == MVT::i32) {
+ if (RetVT == MVT::f32)
return UINTTOFP_I32_F32;
- else if (RetVT == EVT::f64)
+ else if (RetVT == MVT::f64)
return UINTTOFP_I32_F64;
- else if (RetVT == EVT::f80)
+ else if (RetVT == MVT::f80)
return UINTTOFP_I32_F80;
- else if (RetVT == EVT::ppcf128)
+ else if (RetVT == MVT::ppcf128)
return UINTTOFP_I32_PPCF128;
- } else if (OpVT == EVT::i64) {
- if (RetVT == EVT::f32)
+ } else if (OpVT == MVT::i64) {
+ if (RetVT == MVT::f32)
return UINTTOFP_I64_F32;
- else if (RetVT == EVT::f64)
+ else if (RetVT == MVT::f64)
return UINTTOFP_I64_F64;
- else if (RetVT == EVT::f80)
+ else if (RetVT == MVT::f80)
return UINTTOFP_I64_F80;
- else if (RetVT == EVT::ppcf128)
+ else if (RetVT == MVT::ppcf128)
return UINTTOFP_I64_PPCF128;
- } else if (OpVT == EVT::i128) {
- if (RetVT == EVT::f32)
+ } else if (OpVT == MVT::i128) {
+ if (RetVT == MVT::f32)
return UINTTOFP_I128_F32;
- else if (RetVT == EVT::f64)
+ else if (RetVT == MVT::f64)
return UINTTOFP_I128_F64;
- else if (RetVT == EVT::f80)
+ else if (RetVT == MVT::f80)
return UINTTOFP_I128_F80;
- else if (RetVT == EVT::ppcf128)
+ else if (RetVT == MVT::ppcf128)
return UINTTOFP_I128_PPCF128;
}
return UNKNOWN_LIBCALL;
@@ -456,48 +456,49 @@
memset(CondCodeActions, 0, sizeof(CondCodeActions));
// Set default actions for various operations.
- for (unsigned VT = 0; VT != (unsigned)EVT::LAST_VALUETYPE; ++VT) {
+ for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
// Default all indexed load / store to expand.
for (unsigned IM = (unsigned)ISD::PRE_INC;
IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
- setIndexedLoadAction(IM, (EVT::SimpleValueType)VT, Expand);
- setIndexedStoreAction(IM, (EVT::SimpleValueType)VT, Expand);
+ setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
+ setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
}
// These operations default to expand.
- setOperationAction(ISD::FGETSIGN, (EVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::CONCAT_VECTORS, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
}
// Most targets ignore the @llvm.prefetch intrinsic.
- setOperationAction(ISD::PREFETCH, EVT::Other, Expand);
+ setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
// ConstantFP nodes default to expand. Targets can either change this to
// Legal, in which case all fp constants are legal, or use addLegalFPImmediate
// to optimize expansions for certain constants.
- setOperationAction(ISD::ConstantFP, EVT::f32, Expand);
- setOperationAction(ISD::ConstantFP, EVT::f64, Expand);
- setOperationAction(ISD::ConstantFP, EVT::f80, Expand);
+ setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
+ setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
+ setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
// These library functions default to expand.
- setOperationAction(ISD::FLOG , EVT::f64, Expand);
- setOperationAction(ISD::FLOG2, EVT::f64, Expand);
- setOperationAction(ISD::FLOG10,EVT::f64, Expand);
- setOperationAction(ISD::FEXP , EVT::f64, Expand);
- setOperationAction(ISD::FEXP2, EVT::f64, Expand);
- setOperationAction(ISD::FLOG , EVT::f32, Expand);
- setOperationAction(ISD::FLOG2, EVT::f32, Expand);
- setOperationAction(ISD::FLOG10,EVT::f32, Expand);
- setOperationAction(ISD::FEXP , EVT::f32, Expand);
- setOperationAction(ISD::FEXP2, EVT::f32, Expand);
+ setOperationAction(ISD::FLOG , MVT::f64, Expand);
+ setOperationAction(ISD::FLOG2, MVT::f64, Expand);
+ setOperationAction(ISD::FLOG10,MVT::f64, Expand);
+ setOperationAction(ISD::FEXP , MVT::f64, Expand);
+ setOperationAction(ISD::FEXP2, MVT::f64, Expand);
+ setOperationAction(ISD::FLOG , MVT::f32, Expand);
+ setOperationAction(ISD::FLOG2, MVT::f32, Expand);
+ setOperationAction(ISD::FLOG10,MVT::f32, Expand);
+ setOperationAction(ISD::FEXP , MVT::f32, Expand);
+ setOperationAction(ISD::FEXP2, MVT::f32, Expand);
// Default ISD::TRAP to expand (which turns it into abort).
- setOperationAction(ISD::TRAP, EVT::Other, Expand);
+ setOperationAction(ISD::TRAP, MVT::Other, Expand);
IsLittleEndian = TD->isLittleEndian();
UsesGlobalOffsetTable = false;
- ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType()).getSimpleVT();
- memset(RegClassForVT, 0,EVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
+ ShiftAmountTy = PointerTy =
+ getValueType(TD->getIntPtrType()).getSimpleVT().SimpleTy;
+ memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
allowUnalignedMemoryAccesses = false;
@@ -524,7 +525,7 @@
// Tell Legalize whether the assembler supports DEBUG_LOC.
const TargetAsmInfo *TASM = TM.getTargetAsmInfo();
if (!TASM || !TASM->hasDotLocAndDotFile())
- setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
}
TargetLowering::~TargetLowering() {
@@ -534,31 +535,31 @@
/// computeRegisterProperties - Once all of the register classes are added,
/// this allows us to compute derived properties we expose.
void TargetLowering::computeRegisterProperties() {
- assert(EVT::LAST_VALUETYPE <= EVT::MAX_ALLOWED_VALUETYPE &&
+ assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
"Too many value types for ValueTypeActions to hold!");
// Everything defaults to needing one register.
- for (unsigned i = 0; i != EVT::LAST_VALUETYPE; ++i) {
+ for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
NumRegistersForVT[i] = 1;
- RegisterTypeForVT[i] = TransformToType[i] = (EVT::SimpleValueType)i;
+ RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
}
// ...except isVoid, which doesn't need any registers.
- NumRegistersForVT[EVT::isVoid] = 0;
+ NumRegistersForVT[MVT::isVoid] = 0;
// Find the largest integer register class.
- unsigned LargestIntReg = EVT::LAST_INTEGER_VALUETYPE;
+ unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
- assert(LargestIntReg != EVT::i1 && "No integer registers defined!");
+ assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
// Every integer value type larger than this largest register takes twice as
// many registers to represent as the previous ValueType.
for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
- EVT EVT = (EVT::SimpleValueType)ExpandedReg;
+ EVT EVT = (MVT::SimpleValueType)ExpandedReg;
if (!EVT.isInteger())
break;
NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
- RegisterTypeForVT[ExpandedReg] = (EVT::SimpleValueType)LargestIntReg;
- TransformToType[ExpandedReg] = (EVT::SimpleValueType)(ExpandedReg - 1);
+ RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
+ TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
ValueTypeActions.setTypeAction(EVT, Expand);
}
@@ -566,54 +567,54 @@
// register to see which ones need promotion.
unsigned LegalIntReg = LargestIntReg;
for (unsigned IntReg = LargestIntReg - 1;
- IntReg >= (unsigned)EVT::i1; --IntReg) {
- EVT IVT = (EVT::SimpleValueType)IntReg;
+ IntReg >= (unsigned)MVT::i1; --IntReg) {
+ EVT IVT = (MVT::SimpleValueType)IntReg;
if (isTypeLegal(IVT)) {
LegalIntReg = IntReg;
} else {
RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
- (EVT::SimpleValueType)LegalIntReg;
+ (MVT::SimpleValueType)LegalIntReg;
ValueTypeActions.setTypeAction(IVT, Promote);
}
}
// ppcf128 type is really two f64's.
- if (!isTypeLegal(EVT::ppcf128)) {
- NumRegistersForVT[EVT::ppcf128] = 2*NumRegistersForVT[EVT::f64];
- RegisterTypeForVT[EVT::ppcf128] = EVT::f64;
- TransformToType[EVT::ppcf128] = EVT::f64;
- ValueTypeActions.setTypeAction(EVT::ppcf128, Expand);
+ if (!isTypeLegal(MVT::ppcf128)) {
+ NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
+ RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
+ TransformToType[MVT::ppcf128] = MVT::f64;
+ ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
}
// Decide how to handle f64. If the target does not have native f64 support,
// expand it to i64 and we will be generating soft float library calls.
- if (!isTypeLegal(EVT::f64)) {
- NumRegistersForVT[EVT::f64] = NumRegistersForVT[EVT::i64];
- RegisterTypeForVT[EVT::f64] = RegisterTypeForVT[EVT::i64];
- TransformToType[EVT::f64] = EVT::i64;
- ValueTypeActions.setTypeAction(EVT::f64, Expand);
+ if (!isTypeLegal(MVT::f64)) {
+ NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
+ RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
+ TransformToType[MVT::f64] = MVT::i64;
+ ValueTypeActions.setTypeAction(MVT::f64, Expand);
}
// Decide how to handle f32. If the target does not have native support for
// f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
- if (!isTypeLegal(EVT::f32)) {
- if (isTypeLegal(EVT::f64)) {
- NumRegistersForVT[EVT::f32] = NumRegistersForVT[EVT::f64];
- RegisterTypeForVT[EVT::f32] = RegisterTypeForVT[EVT::f64];
- TransformToType[EVT::f32] = EVT::f64;
- ValueTypeActions.setTypeAction(EVT::f32, Promote);
+ if (!isTypeLegal(MVT::f32)) {
+ if (isTypeLegal(MVT::f64)) {
+ NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
+ RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
+ TransformToType[MVT::f32] = MVT::f64;
+ ValueTypeActions.setTypeAction(MVT::f32, Promote);
} else {
- NumRegistersForVT[EVT::f32] = NumRegistersForVT[EVT::i32];
- RegisterTypeForVT[EVT::f32] = RegisterTypeForVT[EVT::i32];
- TransformToType[EVT::f32] = EVT::i32;
- ValueTypeActions.setTypeAction(EVT::f32, Expand);
+ NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
+ RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
+ TransformToType[MVT::f32] = MVT::i32;
+ ValueTypeActions.setTypeAction(MVT::f32, Expand);
}
}
// Loop over all of the vector value types to see which need transformations.
- for (unsigned i = EVT::FIRST_VECTOR_VALUETYPE;
- i <= (unsigned)EVT::LAST_VECTOR_VALUETYPE; ++i) {
- EVT VT = (EVT::SimpleValueType)i;
+ for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
+ i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
+ EVT VT = (MVT::SimpleValueType)i;
if (!isTypeLegal(VT)) {
EVT IntermediateVT, RegisterVT;
unsigned NumIntermediates;
@@ -627,8 +628,8 @@
bool IsLegalWiderType = false;
EVT EltVT = VT.getVectorElementType();
unsigned NElts = VT.getVectorNumElements();
- for (unsigned nVT = i+1; nVT <= EVT::LAST_VECTOR_VALUETYPE; ++nVT) {
- EVT SVT = (EVT::SimpleValueType)nVT;
+ for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
+ EVT SVT = (MVT::SimpleValueType)nVT;
if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT &&
SVT.getVectorNumElements() > NElts) {
TransformToType[i] = SVT;
@@ -641,7 +642,7 @@
EVT NVT = VT.getPow2VectorType();
if (NVT == VT) {
// Type is already a power of 2. The default action is to split.
- TransformToType[i] = EVT::Other;
+ TransformToType[i] = MVT::Other;
ValueTypeActions.setTypeAction(VT, Expand);
} else {
TransformToType[i] = NVT;
@@ -657,15 +658,15 @@
}
-EVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
- return getValueType(TD->getIntPtrType()).getSimpleVT();
+MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
+ return getValueType(TD->getIntPtrType()).getSimpleVT().SimpleTy;
}
/// getVectorTypeBreakdown - Vector types are broken down into some number of
-/// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32
-/// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
-/// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
+/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
+/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
+/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
///
/// This method returns the number of registers needed, and the VT for each
/// register. It also returns the VT and quantity of the intermediate values
@@ -718,7 +719,7 @@
/// getWidenVectorType: given a vector type, returns the type to widen to
/// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
-/// If there is no vector type that we want to widen to, returns EVT::Other
+/// If there is no vector type that we want to widen to, returns MVT::Other
/// When and where to widen is target dependent based on the cost of
/// scalarizing vs using the wider vector type.
EVT TargetLowering::getWidenVectorType(EVT VT) const {
@@ -727,7 +728,7 @@
return VT;
// Default is not to widen until moved to LegalizeTypes
- return EVT::Other;
+ return MVT::Other;
}
/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
@@ -1393,8 +1394,8 @@
// If this is an FP->Int bitcast and if the sign bit is the only thing that
// is demanded, turn this into a FGETSIGN.
if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) &&
- EVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
- !EVT::isVector(Op.getOperand(0).getValueType())) {
+ MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
+ !MVT::isVector(Op.getOperand(0).getValueType())) {
// Only do this xform if FGETSIGN is valid or if before legalize.
if (!TLO.AfterLegalize ||
isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
@@ -2010,46 +2011,46 @@
// Fold away ALL boolean setcc's.
SDValue Temp;
- if (N0.getValueType() == EVT::i1 && foldBooleans) {
+ if (N0.getValueType() == MVT::i1 && foldBooleans) {
switch (Cond) {
default: llvm_unreachable("Unknown integer setcc!");
case ISD::SETEQ: // X == Y -> ~(X^Y)
- Temp = DAG.getNode(ISD::XOR, dl, EVT::i1, N0, N1);
- N0 = DAG.getNOT(dl, Temp, EVT::i1);
+ Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
+ N0 = DAG.getNOT(dl, Temp, MVT::i1);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETNE: // X != Y --> (X^Y)
- N0 = DAG.getNode(ISD::XOR, dl, EVT::i1, N0, N1);
+ N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
break;
case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
- Temp = DAG.getNOT(dl, N0, EVT::i1);
- N0 = DAG.getNode(ISD::AND, dl, EVT::i1, N1, Temp);
+ Temp = DAG.getNOT(dl, N0, MVT::i1);
+ N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
- Temp = DAG.getNOT(dl, N1, EVT::i1);
- N0 = DAG.getNode(ISD::AND, dl, EVT::i1, N0, Temp);
+ Temp = DAG.getNOT(dl, N1, MVT::i1);
+ N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
- Temp = DAG.getNOT(dl, N0, EVT::i1);
- N0 = DAG.getNode(ISD::OR, dl, EVT::i1, N1, Temp);
+ Temp = DAG.getNOT(dl, N0, MVT::i1);
+ N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
- Temp = DAG.getNOT(dl, N1, EVT::i1);
- N0 = DAG.getNode(ISD::OR, dl, EVT::i1, N0, Temp);
+ Temp = DAG.getNOT(dl, N1, MVT::i1);
+ N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
break;
}
- if (VT != EVT::i1) {
+ if (VT != MVT::i1) {
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(N0.getNode());
// FIXME: If running after legalize, we probably can't do this.
@@ -2245,7 +2246,7 @@
// now; without this it would get ZExt'd later in
// ScheduleDAGSDNodes::EmitNode, which is very generic.
Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
- EVT::i64));
+ MVT::i64));
return;
}
}
Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Aug 11 15:47:22 2009
@@ -63,7 +63,7 @@
/// getI32Imm - Return a target constant with the specified value, of type i32.
inline SDValue getI32Imm(unsigned Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i32);
+ return CurDAG->getTargetConstant(Imm, MVT::i32);
}
SDNode *Select(SDValue Op);
@@ -156,13 +156,13 @@
BaseReg = N.getOperand(0);
unsigned ShImmVal = 0;
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
- ShReg = CurDAG->getRegister(0, EVT::i32);
+ ShReg = CurDAG->getRegister(0, MVT::i32);
ShImmVal = RHS->getZExtValue() & 31;
} else {
ShReg = N.getOperand(1);
}
Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
- EVT::i32);
+ MVT::i32);
return true;
}
@@ -185,7 +185,7 @@
Base = Offset = N.getOperand(0);
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
ARM_AM::lsl),
- EVT::i32);
+ MVT::i32);
return true;
}
}
@@ -200,10 +200,10 @@
} else if (N.getOpcode() == ARMISD::Wrapper) {
Base = N.getOperand(0);
}
- Offset = CurDAG->getRegister(0, EVT::i32);
+ Offset = CurDAG->getRegister(0, MVT::i32);
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
ARM_AM::no_shift),
- EVT::i32);
+ MVT::i32);
return true;
}
@@ -218,7 +218,7 @@
int FI = cast<FrameIndexSDNode>(Base)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
}
- Offset = CurDAG->getRegister(0, EVT::i32);
+ Offset = CurDAG->getRegister(0, MVT::i32);
ARM_AM::AddrOpc AddSub = ARM_AM::add;
if (RHSC < 0) {
@@ -227,7 +227,7 @@
}
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
ARM_AM::no_shift),
- EVT::i32);
+ MVT::i32);
return true;
}
}
@@ -270,7 +270,7 @@
}
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
- EVT::i32);
+ MVT::i32);
return true;
}
@@ -285,10 +285,10 @@
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
int Val = (int)C->getZExtValue();
if (Val >= 0 && Val < 0x1000) { // 12 bits.
- Offset = CurDAG->getRegister(0, EVT::i32);
+ Offset = CurDAG->getRegister(0, MVT::i32);
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
ARM_AM::no_shift),
- EVT::i32);
+ MVT::i32);
return true;
}
}
@@ -308,7 +308,7 @@
}
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
- EVT::i32);
+ MVT::i32);
return true;
}
@@ -320,7 +320,7 @@
// X - C is canonicalize to X + -C, no need to handle it here.
Base = N.getOperand(0);
Offset = N.getOperand(1);
- Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),EVT::i32);
+ Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
return true;
}
@@ -330,8 +330,8 @@
int FI = cast<FrameIndexSDNode>(N)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
}
- Offset = CurDAG->getRegister(0, EVT::i32);
- Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),EVT::i32);
+ Offset = CurDAG->getRegister(0, MVT::i32);
+ Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
return true;
}
@@ -345,21 +345,21 @@
int FI = cast<FrameIndexSDNode>(Base)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
}
- Offset = CurDAG->getRegister(0, EVT::i32);
+ Offset = CurDAG->getRegister(0, MVT::i32);
ARM_AM::AddrOpc AddSub = ARM_AM::add;
if (RHSC < 0) {
AddSub = ARM_AM::sub;
RHSC = - RHSC;
}
- Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),EVT::i32);
+ Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
return true;
}
}
Base = N.getOperand(0);
Offset = N.getOperand(1);
- Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), EVT::i32);
+ Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
return true;
}
@@ -374,21 +374,21 @@
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
int Val = (int)C->getZExtValue();
if (Val >= 0 && Val < 256) {
- Offset = CurDAG->getRegister(0, EVT::i32);
- Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), EVT::i32);
+ Offset = CurDAG->getRegister(0, MVT::i32);
+ Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
return true;
}
}
Offset = N;
- Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), EVT::i32);
+ Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
return true;
}
bool ARMDAGToDAGISel::SelectAddrMode4(SDValue Op, SDValue N,
SDValue &Addr, SDValue &Mode) {
Addr = N;
- Mode = CurDAG->getTargetConstant(0, EVT::i32);
+ Mode = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
@@ -403,7 +403,7 @@
Base = N.getOperand(0);
}
Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
- EVT::i32);
+ MVT::i32);
return true;
}
@@ -426,7 +426,7 @@
RHSC = - RHSC;
}
Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
- EVT::i32);
+ MVT::i32);
return true;
}
}
@@ -434,7 +434,7 @@
Base = N;
Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
- EVT::i32);
+ MVT::i32);
return true;
}
@@ -443,8 +443,8 @@
SDValue &Opc) {
Addr = N;
// The optional writeback is handled in ARMLoadStoreOpt.
- Update = CurDAG->getRegister(0, EVT::i32);
- Opc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(false), EVT::i32);
+ Update = CurDAG->getRegister(0, MVT::i32);
+ Opc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(false), MVT::i32);
return true;
}
@@ -454,7 +454,7 @@
Offset = N.getOperand(0);
SDValue N1 = N.getOperand(1);
Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
- EVT::i32);
+ MVT::i32);
return true;
}
return false;
@@ -493,8 +493,8 @@
if (N.getOpcode() != ISD::ADD) {
Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
- Offset = CurDAG->getRegister(0, EVT::i32);
- OffImm = CurDAG->getTargetConstant(0, EVT::i32);
+ Offset = CurDAG->getRegister(0, MVT::i32);
+ OffImm = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
@@ -504,8 +504,8 @@
if ((LHSR && LHSR->getReg() == ARM::SP) ||
(RHSR && RHSR->getReg() == ARM::SP)) {
Base = N;
- Offset = CurDAG->getRegister(0, EVT::i32);
- OffImm = CurDAG->getTargetConstant(0, EVT::i32);
+ Offset = CurDAG->getRegister(0, MVT::i32);
+ OffImm = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
@@ -516,8 +516,8 @@
RHSC /= Scale;
if (RHSC >= 0 && RHSC < 32) {
Base = N.getOperand(0);
- Offset = CurDAG->getRegister(0, EVT::i32);
- OffImm = CurDAG->getTargetConstant(RHSC, EVT::i32);
+ Offset = CurDAG->getRegister(0, MVT::i32);
+ OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
return true;
}
}
@@ -525,7 +525,7 @@
Base = N.getOperand(0);
Offset = N.getOperand(1);
- OffImm = CurDAG->getTargetConstant(0, EVT::i32);
+ OffImm = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
@@ -552,7 +552,7 @@
if (N.getOpcode() == ISD::FrameIndex) {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
- OffImm = CurDAG->getTargetConstant(0, EVT::i32);
+ OffImm = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
@@ -573,7 +573,7 @@
int FI = cast<FrameIndexSDNode>(Base)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
}
- OffImm = CurDAG->getTargetConstant(RHSC, EVT::i32);
+ OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
return true;
}
}
@@ -613,7 +613,7 @@
// Match frame index...
int FI = cast<FrameIndexSDNode>(N)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
- OffImm = CurDAG->getTargetConstant(0, EVT::i32);
+ OffImm = CurDAG->getTargetConstant(0, MVT::i32);
return true;
} else if (N.getOpcode() == ARMISD::Wrapper) {
Base = N.getOperand(0);
@@ -621,7 +621,7 @@
return false; // We want to select t2LDRpci instead.
} else
Base = N;
- OffImm = CurDAG->getTargetConstant(0, EVT::i32);
+ OffImm = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
@@ -640,14 +640,14 @@
int FI = cast<FrameIndexSDNode>(Base)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
}
- OffImm = CurDAG->getTargetConstant(RHSC, EVT::i32);
+ OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
return true;
}
}
// Base only.
Base = N;
- OffImm = CurDAG->getTargetConstant(0, EVT::i32);
+ OffImm = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
@@ -666,7 +666,7 @@
int FI = cast<FrameIndexSDNode>(Base)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
}
- OffImm = CurDAG->getTargetConstant(RHSC, EVT::i32);
+ OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
return true;
}
}
@@ -685,8 +685,8 @@
int RHSC = (int)RHS->getZExtValue();
if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
- ? CurDAG->getTargetConstant(RHSC, EVT::i32)
- : CurDAG->getTargetConstant(-RHSC, EVT::i32);
+ ? CurDAG->getTargetConstant(RHSC, MVT::i32)
+ : CurDAG->getTargetConstant(-RHSC, MVT::i32);
return true;
}
}
@@ -702,7 +702,7 @@
if (((RHSC & 0x3) == 0) &&
((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) { // 8 bits.
Base = N.getOperand(0);
- OffImm = CurDAG->getTargetConstant(RHSC, EVT::i32);
+ OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
return true;
}
}
@@ -711,7 +711,7 @@
int RHSC = (int)RHS->getZExtValue();
if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) { // 8 bits.
Base = N.getOperand(0);
- OffImm = CurDAG->getTargetConstant(-RHSC, EVT::i32);
+ OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
return true;
}
}
@@ -764,7 +764,7 @@
}
}
- ShImm = CurDAG->getTargetConstant(ShAmt, EVT::i32);
+ ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
return true;
}
@@ -773,7 +773,7 @@
/// getAL - Returns a ARMCC::AL immediate node.
static inline SDValue getAL(SelectionDAG *CurDAG) {
- return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, EVT::i32);
+ return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
}
SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDValue Op) {
@@ -787,17 +787,17 @@
bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
unsigned Opcode = 0;
bool Match = false;
- if (LoadedVT == EVT::i32 &&
+ if (LoadedVT == MVT::i32 &&
SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
Match = true;
- } else if (LoadedVT == EVT::i16 &&
+ } else if (LoadedVT == MVT::i16 &&
SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
Match = true;
Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
: (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
- } else if (LoadedVT == EVT::i8 || LoadedVT == EVT::i1) {
+ } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
if (LD->getExtensionType() == ISD::SEXTLOAD) {
if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
Match = true;
@@ -815,9 +815,9 @@
SDValue Chain = LD->getChain();
SDValue Base = LD->getBasePtr();
SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
- CurDAG->getRegister(0, EVT::i32), Chain };
- return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), EVT::i32, EVT::i32,
- EVT::Other, Ops, 6);
+ CurDAG->getRegister(0, MVT::i32), Chain };
+ return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
+ MVT::Other, Ops, 6);
}
return NULL;
@@ -836,18 +836,18 @@
unsigned Opcode = 0;
bool Match = false;
if (SelectT2AddrModeImm8Offset(Op, LD->getOffset(), Offset)) {
- switch (LoadedVT.getSimpleVT()) {
- case EVT::i32:
+ switch (LoadedVT.getSimpleVT().SimpleTy) {
+ case MVT::i32:
Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
break;
- case EVT::i16:
+ case MVT::i16:
if (isSExtLd)
Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
else
Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
break;
- case EVT::i8:
- case EVT::i1:
+ case MVT::i8:
+ case MVT::i1:
if (isSExtLd)
Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
else
@@ -863,9 +863,9 @@
SDValue Chain = LD->getChain();
SDValue Base = LD->getBasePtr();
SDValue Ops[]= { Base, Offset, getAL(CurDAG),
- CurDAG->getRegister(0, EVT::i32), Chain };
- return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), EVT::i32, EVT::i32,
- EVT::Other, Ops, 5);
+ CurDAG->getRegister(0, MVT::i32), Chain };
+ return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
+ MVT::Other, Ops, 5);
}
return NULL;
@@ -878,7 +878,7 @@
SDValue Chain = Op.getOperand(0);
SDValue Size = Op.getOperand(1);
SDValue Align = Op.getOperand(2);
- SDValue SP = CurDAG->getRegister(ARM::SP, EVT::i32);
+ SDValue SP = CurDAG->getRegister(ARM::SP, MVT::i32);
int32_t AlignVal = cast<ConstantSDNode>(Align)->getSExtValue();
if (AlignVal < 0)
// We need to align the stack. Use Thumb1 tAND which is the only thumb
@@ -893,8 +893,8 @@
// tSUBspi - immediate is between 0 ... 508 inclusive.
if (C <= 508 && ((C & 3) == 0))
// FIXME: tSUBspi encode scale 4 implicitly.
- return CurDAG->SelectNodeTo(N, ARM::tSUBspi_, VT, EVT::Other, SP,
- CurDAG->getTargetConstant(C/4, EVT::i32),
+ return CurDAG->SelectNodeTo(N, ARM::tSUBspi_, VT, MVT::Other, SP,
+ CurDAG->getTargetConstant(C/4, MVT::i32),
Chain);
if (Subtarget->isThumb1Only()) {
@@ -902,22 +902,22 @@
// should have negated the size operand already. FIXME: We can't insert
// new target independent node at this stage so we are forced to negate
// it earlier. Is there a better solution?
- return CurDAG->SelectNodeTo(N, ARM::tADDspr_, VT, EVT::Other, SP, Size,
+ return CurDAG->SelectNodeTo(N, ARM::tADDspr_, VT, MVT::Other, SP, Size,
Chain);
} else if (Subtarget->isThumb2()) {
if (isC && Predicate_t2_so_imm(Size.getNode())) {
// t2SUBrSPi
- SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, EVT::i32), Chain };
- return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi_, VT, EVT::Other, Ops, 3);
+ SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
+ return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi_, VT, MVT::Other, Ops, 3);
} else if (isC && Predicate_imm0_4095(Size.getNode())) {
// t2SUBrSPi12
- SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, EVT::i32), Chain };
- return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi12_, VT, EVT::Other, Ops, 3);
+ SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
+ return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi12_, VT, MVT::Other, Ops, 3);
} else {
// t2SUBrSPs
SDValue Ops[] = { SP, Size,
getI32Imm(ARM_AM::getSORegOpc(ARM_AM::lsl,0)), Chain };
- return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPs_, VT, EVT::Other, Ops, 4);
+ return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPs_, VT, MVT::Other, Ops, 4);
}
}
@@ -957,21 +957,21 @@
SDNode *ResNode;
if (Subtarget->isThumb1Only()) {
- SDValue Pred = CurDAG->getTargetConstant(0xEULL, EVT::i32);
- SDValue PredReg = CurDAG->getRegister(0, EVT::i32);
+ SDValue Pred = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
- ResNode = CurDAG->getTargetNode(ARM::tLDRcp, dl, EVT::i32, EVT::Other,
+ ResNode = CurDAG->getTargetNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
Ops, 4);
} else {
SDValue Ops[] = {
CPIdx,
- CurDAG->getRegister(0, EVT::i32),
- CurDAG->getTargetConstant(0, EVT::i32),
+ CurDAG->getRegister(0, MVT::i32),
+ CurDAG->getTargetConstant(0, MVT::i32),
getAL(CurDAG),
- CurDAG->getRegister(0, EVT::i32),
+ CurDAG->getRegister(0, MVT::i32),
CurDAG->getEntryNode()
};
- ResNode=CurDAG->getTargetNode(ARM::LDRcp, dl, EVT::i32, EVT::Other,
+ ResNode=CurDAG->getTargetNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
Ops, 6);
}
ReplaceUses(Op, SDValue(ResNode, 0));
@@ -986,15 +986,15 @@
int FI = cast<FrameIndexSDNode>(N)->getIndex();
SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
if (Subtarget->isThumb1Only()) {
- return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, EVT::i32, TFI,
- CurDAG->getTargetConstant(0, EVT::i32));
+ return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
+ CurDAG->getTargetConstant(0, MVT::i32));
} else {
unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
ARM::t2ADDri : ARM::ADDri);
- SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, EVT::i32),
- getAL(CurDAG), CurDAG->getRegister(0, EVT::i32),
- CurDAG->getRegister(0, EVT::i32) };
- return CurDAG->SelectNodeTo(N, Opc, EVT::i32, Ops, 5);
+ SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
+ getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
+ CurDAG->getRegister(0, MVT::i32) };
+ return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
}
}
case ARMISD::DYN_ALLOC:
@@ -1011,14 +1011,14 @@
break;
SDValue V = Op.getOperand(0);
ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
- SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, EVT::i32);
- SDValue Reg0 = CurDAG->getRegister(0, EVT::i32);
+ SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
+ SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
if (Subtarget->isThumb()) {
SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
- return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, EVT::i32, Ops, 6);
+ return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
} else {
SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
- return CurDAG->SelectNodeTo(N, ARM::ADDrs, EVT::i32, Ops, 7);
+ return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
}
}
if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
@@ -1027,35 +1027,35 @@
break;
SDValue V = Op.getOperand(0);
ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
- SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, EVT::i32);
- SDValue Reg0 = CurDAG->getRegister(0, EVT::i32);
+ SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
+ SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
if (Subtarget->isThumb()) {
SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0 };
- return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, EVT::i32, Ops, 5);
+ return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 5);
} else {
SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
- return CurDAG->SelectNodeTo(N, ARM::RSBrs, EVT::i32, Ops, 7);
+ return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
}
}
}
break;
case ARMISD::FMRRD:
- return CurDAG->getTargetNode(ARM::FMRRD, dl, EVT::i32, EVT::i32,
+ return CurDAG->getTargetNode(ARM::FMRRD, dl, MVT::i32, MVT::i32,
Op.getOperand(0), getAL(CurDAG),
- CurDAG->getRegister(0, EVT::i32));
+ CurDAG->getRegister(0, MVT::i32));
case ISD::UMUL_LOHI: {
if (Subtarget->isThumb1Only())
break;
if (Subtarget->isThumb()) {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
- getAL(CurDAG), CurDAG->getRegister(0, EVT::i32),
- CurDAG->getRegister(0, EVT::i32) };
- return CurDAG->getTargetNode(ARM::t2UMULL, dl, EVT::i32, EVT::i32, Ops,4);
+ getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
+ CurDAG->getRegister(0, MVT::i32) };
+ return CurDAG->getTargetNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops,4);
} else {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
- getAL(CurDAG), CurDAG->getRegister(0, EVT::i32),
- CurDAG->getRegister(0, EVT::i32) };
- return CurDAG->getTargetNode(ARM::UMULL, dl, EVT::i32, EVT::i32, Ops, 5);
+ getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
+ CurDAG->getRegister(0, MVT::i32) };
+ return CurDAG->getTargetNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
}
}
case ISD::SMUL_LOHI: {
@@ -1063,13 +1063,13 @@
break;
if (Subtarget->isThumb()) {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
- getAL(CurDAG), CurDAG->getRegister(0, EVT::i32) };
- return CurDAG->getTargetNode(ARM::t2SMULL, dl, EVT::i32, EVT::i32, Ops,4);
+ getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
+ return CurDAG->getTargetNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops,4);
} else {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
- getAL(CurDAG), CurDAG->getRegister(0, EVT::i32),
- CurDAG->getRegister(0, EVT::i32) };
- return CurDAG->getTargetNode(ARM::SMULL, dl, EVT::i32, EVT::i32, Ops, 5);
+ getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
+ CurDAG->getRegister(0, MVT::i32) };
+ return CurDAG->getTargetNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
}
}
case ISD::LOAD: {
@@ -1109,10 +1109,10 @@
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getZExtValue()),
- EVT::i32);
+ MVT::i32);
SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
- SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, EVT::Other,
- EVT::Flag, Ops, 5);
+ SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, MVT::Other,
+ MVT::Flag, Ops, 5);
Chain = SDValue(ResNode, 0);
if (Op.getNode()->getNumValues() == 2) {
InFlag = SDValue(ResNode, 1);
@@ -1131,7 +1131,7 @@
assert(N2.getOpcode() == ISD::Constant);
assert(N3.getOpcode() == ISD::Register);
- if (!Subtarget->isThumb1Only() && VT == EVT::i32) {
+ if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
// Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
// Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
// Pattern complexity = 18 cost = 1 size = 0
@@ -1153,21 +1153,21 @@
break;
}
SDValue SOShImm =
- CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), EVT::i32);
+ CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getZExtValue()),
- EVT::i32);
+ MVT::i32);
SDValue Ops[] = { N0, CPTmp0, SOShImm, Tmp2, N3, InFlag };
- return CurDAG->SelectNodeTo(Op.getNode(), Opc, EVT::i32,Ops, 6);
+ return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32,Ops, 6);
}
} else {
if (SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getZExtValue()),
- EVT::i32);
+ MVT::i32);
SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
return CurDAG->SelectNodeTo(Op.getNode(),
- ARM::MOVCCs, EVT::i32, Ops, 7);
+ ARM::MOVCCs, MVT::i32, Ops, 7);
}
}
@@ -1182,25 +1182,25 @@
if (Predicate_t2_so_imm(N3.getNode())) {
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N1)->getZExtValue()),
- EVT::i32);
+ MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getZExtValue()),
- EVT::i32);
+ MVT::i32);
SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
return CurDAG->SelectNodeTo(Op.getNode(),
- ARM::t2MOVCCi, EVT::i32, Ops, 5);
+ ARM::t2MOVCCi, MVT::i32, Ops, 5);
}
} else {
if (Predicate_so_imm(N3.getNode())) {
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N1)->getZExtValue()),
- EVT::i32);
+ MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getZExtValue()),
- EVT::i32);
+ MVT::i32);
SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
return CurDAG->SelectNodeTo(Op.getNode(),
- ARM::MOVCCi, EVT::i32, Ops, 5);
+ ARM::MOVCCi, MVT::i32, Ops, 5);
}
}
}
@@ -1217,21 +1217,21 @@
// Also FCPYScc and FCPYDcc.
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getZExtValue()),
- EVT::i32);
+ MVT::i32);
SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
unsigned Opc = 0;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: assert(false && "Illegal conditional move type!");
break;
- case EVT::i32:
+ case MVT::i32:
Opc = Subtarget->isThumb()
? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr)
: ARM::MOVCCr;
break;
- case EVT::f32:
+ case MVT::f32:
Opc = ARM::FCPYScc;
break;
- case EVT::f64:
+ case MVT::f64:
Opc = ARM::FCPYDcc;
break;
}
@@ -1249,16 +1249,16 @@
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getZExtValue()),
- EVT::i32);
+ MVT::i32);
SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
unsigned Opc = 0;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: assert(false && "Illegal conditional move type!");
break;
- case EVT::f32:
+ case MVT::f32:
Opc = ARM::FNEGScc;
break;
- case EVT::f64:
+ case MVT::f64:
Opc = ARM::FNEGDcc;
break;
}
@@ -1303,7 +1303,7 @@
SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());
SDValue Ops[] = { Tmp1, Tmp2, Chain };
return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl,
- EVT::Other, Ops, 3);
+ MVT::Other, Ops, 3);
}
case ISD::VECTOR_SHUFFLE: {
@@ -1322,20 +1322,20 @@
EVT HalfVT;
unsigned Opc = 0;
- switch (VT.getVectorElementType().getSimpleVT()) {
+ switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled VDUP splat type");
- case EVT::i8: Opc = ARM::VDUPLN8q; HalfVT = EVT::v8i8; break;
- case EVT::i16: Opc = ARM::VDUPLN16q; HalfVT = EVT::v4i16; break;
- case EVT::i32: Opc = ARM::VDUPLN32q; HalfVT = EVT::v2i32; break;
- case EVT::f32: Opc = ARM::VDUPLNfq; HalfVT = EVT::v2f32; break;
+ case MVT::i8: Opc = ARM::VDUPLN8q; HalfVT = MVT::v8i8; break;
+ case MVT::i16: Opc = ARM::VDUPLN16q; HalfVT = MVT::v4i16; break;
+ case MVT::i32: Opc = ARM::VDUPLN32q; HalfVT = MVT::v2i32; break;
+ case MVT::f32: Opc = ARM::VDUPLNfq; HalfVT = MVT::v2f32; break;
}
// The source operand needs to be changed to a subreg of the original
// 128-bit operand, and the lane number needs to be adjusted accordingly.
unsigned NumElts = VT.getVectorNumElements() / 2;
unsigned SRVal = (LaneVal < NumElts ? arm_dsubreg_0 : arm_dsubreg_1);
- SDValue SR = CurDAG->getTargetConstant(SRVal, EVT::i32);
- SDValue NewLane = CurDAG->getTargetConstant(LaneVal % NumElts, EVT::i32);
+ SDValue SR = CurDAG->getTargetConstant(SRVal, MVT::i32);
+ SDValue NewLane = CurDAG->getTargetConstant(LaneVal % NumElts, MVT::i32);
SDNode *SubReg = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
dl, HalfVT, N->getOperand(0), SR);
return CurDAG->SelectNodeTo(N, Opc, VT, SDValue(SubReg, 0), NewLane);
@@ -1350,15 +1350,15 @@
return NULL;
unsigned Opc = 0;
EVT VT = Op.getValueType();
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled VLD2D type");
- case EVT::v8i8: Opc = ARM::VLD2d8; break;
- case EVT::v4i16: Opc = ARM::VLD2d16; break;
- case EVT::v2f32:
- case EVT::v2i32: Opc = ARM::VLD2d32; break;
+ case MVT::v8i8: Opc = ARM::VLD2d8; break;
+ case MVT::v4i16: Opc = ARM::VLD2d16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VLD2d32; break;
}
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
- return CurDAG->getTargetNode(Opc, dl, VT, VT, EVT::Other, Ops, 3);
+ return CurDAG->getTargetNode(Opc, dl, VT, VT, MVT::Other, Ops, 3);
}
case ARMISD::VLD3D: {
@@ -1367,15 +1367,15 @@
return NULL;
unsigned Opc = 0;
EVT VT = Op.getValueType();
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled VLD3D type");
- case EVT::v8i8: Opc = ARM::VLD3d8; break;
- case EVT::v4i16: Opc = ARM::VLD3d16; break;
- case EVT::v2f32:
- case EVT::v2i32: Opc = ARM::VLD3d32; break;
+ case MVT::v8i8: Opc = ARM::VLD3d8; break;
+ case MVT::v4i16: Opc = ARM::VLD3d16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VLD3d32; break;
}
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
- return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, EVT::Other, Ops, 3);
+ return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 3);
}
case ARMISD::VLD4D: {
@@ -1384,16 +1384,16 @@
return NULL;
unsigned Opc = 0;
EVT VT = Op.getValueType();
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled VLD4D type");
- case EVT::v8i8: Opc = ARM::VLD4d8; break;
- case EVT::v4i16: Opc = ARM::VLD4d16; break;
- case EVT::v2f32:
- case EVT::v2i32: Opc = ARM::VLD4d32; break;
+ case MVT::v8i8: Opc = ARM::VLD4d8; break;
+ case MVT::v4i16: Opc = ARM::VLD4d16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VLD4d32; break;
}
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
std::vector<EVT> ResTys(4, VT);
- ResTys.push_back(EVT::Other);
+ ResTys.push_back(MVT::Other);
return CurDAG->getTargetNode(Opc, dl, ResTys, Ops, 3);
}
@@ -1402,16 +1402,16 @@
if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
return NULL;
unsigned Opc = 0;
- switch (N->getOperand(2).getValueType().getSimpleVT()) {
+ switch (N->getOperand(2).getValueType().getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled VST2D type");
- case EVT::v8i8: Opc = ARM::VST2d8; break;
- case EVT::v4i16: Opc = ARM::VST2d16; break;
- case EVT::v2f32:
- case EVT::v2i32: Opc = ARM::VST2d32; break;
+ case MVT::v8i8: Opc = ARM::VST2d8; break;
+ case MVT::v4i16: Opc = ARM::VST2d16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VST2d32; break;
}
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
N->getOperand(2), N->getOperand(3) };
- return CurDAG->getTargetNode(Opc, dl, EVT::Other, Ops, 5);
+ return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 5);
}
case ARMISD::VST3D: {
@@ -1419,17 +1419,17 @@
if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
return NULL;
unsigned Opc = 0;
- switch (N->getOperand(2).getValueType().getSimpleVT()) {
+ switch (N->getOperand(2).getValueType().getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled VST3D type");
- case EVT::v8i8: Opc = ARM::VST3d8; break;
- case EVT::v4i16: Opc = ARM::VST3d16; break;
- case EVT::v2f32:
- case EVT::v2i32: Opc = ARM::VST3d32; break;
+ case MVT::v8i8: Opc = ARM::VST3d8; break;
+ case MVT::v4i16: Opc = ARM::VST3d16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VST3d32; break;
}
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
N->getOperand(2), N->getOperand(3),
N->getOperand(4) };
- return CurDAG->getTargetNode(Opc, dl, EVT::Other, Ops, 6);
+ return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 6);
}
case ARMISD::VST4D: {
@@ -1437,17 +1437,17 @@
if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
return NULL;
unsigned Opc = 0;
- switch (N->getOperand(2).getValueType().getSimpleVT()) {
+ switch (N->getOperand(2).getValueType().getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled VST4D type");
- case EVT::v8i8: Opc = ARM::VST4d8; break;
- case EVT::v4i16: Opc = ARM::VST4d16; break;
- case EVT::v2f32:
- case EVT::v2i32: Opc = ARM::VST4d32; break;
+ case MVT::v8i8: Opc = ARM::VST4d8; break;
+ case MVT::v4i16: Opc = ARM::VST4d16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VST4d32; break;
}
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
N->getOperand(2), N->getOperand(3),
N->getOperand(4), N->getOperand(5) };
- return CurDAG->getTargetNode(Opc, dl, EVT::Other, Ops, 7);
+ return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7);
}
case ISD::INTRINSIC_WO_CHAIN: {
@@ -1460,46 +1460,46 @@
default: break;
case Intrinsic::arm_neon_vtrn:
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: return NULL;
- case EVT::v8i8: Opc = ARM::VTRNd8; break;
- case EVT::v4i16: Opc = ARM::VTRNd16; break;
- case EVT::v2f32:
- case EVT::v2i32: Opc = ARM::VTRNd32; break;
- case EVT::v16i8: Opc = ARM::VTRNq8; break;
- case EVT::v8i16: Opc = ARM::VTRNq16; break;
- case EVT::v4f32:
- case EVT::v4i32: Opc = ARM::VTRNq32; break;
+ case MVT::v8i8: Opc = ARM::VTRNd8; break;
+ case MVT::v4i16: Opc = ARM::VTRNd16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VTRNd32; break;
+ case MVT::v16i8: Opc = ARM::VTRNq8; break;
+ case MVT::v8i16: Opc = ARM::VTRNq16; break;
+ case MVT::v4f32:
+ case MVT::v4i32: Opc = ARM::VTRNq32; break;
}
return CurDAG->getTargetNode(Opc, dl, VT, VT, N->getOperand(1),
N->getOperand(2));
case Intrinsic::arm_neon_vuzp:
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: return NULL;
- case EVT::v8i8: Opc = ARM::VUZPd8; break;
- case EVT::v4i16: Opc = ARM::VUZPd16; break;
- case EVT::v2f32:
- case EVT::v2i32: Opc = ARM::VUZPd32; break;
- case EVT::v16i8: Opc = ARM::VUZPq8; break;
- case EVT::v8i16: Opc = ARM::VUZPq16; break;
- case EVT::v4f32:
- case EVT::v4i32: Opc = ARM::VUZPq32; break;
+ case MVT::v8i8: Opc = ARM::VUZPd8; break;
+ case MVT::v4i16: Opc = ARM::VUZPd16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VUZPd32; break;
+ case MVT::v16i8: Opc = ARM::VUZPq8; break;
+ case MVT::v8i16: Opc = ARM::VUZPq16; break;
+ case MVT::v4f32:
+ case MVT::v4i32: Opc = ARM::VUZPq32; break;
}
return CurDAG->getTargetNode(Opc, dl, VT, VT, N->getOperand(1),
N->getOperand(2));
case Intrinsic::arm_neon_vzip:
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: return NULL;
- case EVT::v8i8: Opc = ARM::VZIPd8; break;
- case EVT::v4i16: Opc = ARM::VZIPd16; break;
- case EVT::v2f32:
- case EVT::v2i32: Opc = ARM::VZIPd32; break;
- case EVT::v16i8: Opc = ARM::VZIPq8; break;
- case EVT::v8i16: Opc = ARM::VZIPq16; break;
- case EVT::v4f32:
- case EVT::v4i32: Opc = ARM::VZIPq32; break;
+ case MVT::v8i8: Opc = ARM::VZIPd8; break;
+ case MVT::v4i16: Opc = ARM::VZIPd16; break;
+ case MVT::v2f32:
+ case MVT::v2i32: Opc = ARM::VZIPd32; break;
+ case MVT::v16i8: Opc = ARM::VZIPq8; break;
+ case MVT::v8i16: Opc = ARM::VZIPq16; break;
+ case MVT::v4f32:
+ case MVT::v4i32: Opc = ARM::VZIPq32; break;
}
return CurDAG->getTargetNode(Opc, dl, VT, VT, N->getOperand(1),
N->getOperand(2));
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Aug 11 15:47:22 2009
@@ -71,9 +71,9 @@
}
EVT ElemTy = VT.getVectorElementType();
- if (ElemTy != EVT::i64 && ElemTy != EVT::f64)
+ if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
- if (ElemTy == EVT::i8 || ElemTy == EVT::i16)
+ if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
@@ -101,12 +101,12 @@
void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
addRegisterClass(VT, ARM::DPRRegisterClass);
- addTypeForNEON(VT, EVT::f64, EVT::v2i32);
+ addTypeForNEON(VT, MVT::f64, MVT::v2i32);
}
void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
addRegisterClass(VT, ARM::QPRRegisterClass);
- addTypeForNEON(VT, EVT::v2f64, EVT::v4i32);
+ addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
}
static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
@@ -202,29 +202,29 @@
setLibcallName(RTLIB::SRA_I128, 0);
if (Subtarget->isThumb1Only())
- addRegisterClass(EVT::i32, ARM::tGPRRegisterClass);
+ addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
else
- addRegisterClass(EVT::i32, ARM::GPRRegisterClass);
+ addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
- addRegisterClass(EVT::f32, ARM::SPRRegisterClass);
- addRegisterClass(EVT::f64, ARM::DPRRegisterClass);
+ addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
+ addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
- setTruncStoreAction(EVT::f64, EVT::f32, Expand);
+ setTruncStoreAction(MVT::f64, MVT::f32, Expand);
}
if (Subtarget->hasNEON()) {
- addDRTypeForNEON(EVT::v2f32);
- addDRTypeForNEON(EVT::v8i8);
- addDRTypeForNEON(EVT::v4i16);
- addDRTypeForNEON(EVT::v2i32);
- addDRTypeForNEON(EVT::v1i64);
-
- addQRTypeForNEON(EVT::v4f32);
- addQRTypeForNEON(EVT::v2f64);
- addQRTypeForNEON(EVT::v16i8);
- addQRTypeForNEON(EVT::v8i16);
- addQRTypeForNEON(EVT::v4i32);
- addQRTypeForNEON(EVT::v2i64);
+ addDRTypeForNEON(MVT::v2f32);
+ addDRTypeForNEON(MVT::v8i8);
+ addDRTypeForNEON(MVT::v4i16);
+ addDRTypeForNEON(MVT::v2i32);
+ addDRTypeForNEON(MVT::v1i64);
+
+ addQRTypeForNEON(MVT::v4f32);
+ addQRTypeForNEON(MVT::v2f64);
+ addQRTypeForNEON(MVT::v16i8);
+ addQRTypeForNEON(MVT::v8i16);
+ addQRTypeForNEON(MVT::v4i32);
+ addQRTypeForNEON(MVT::v2i64);
setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
setTargetDAGCombine(ISD::SHL);
@@ -238,137 +238,137 @@
computeRegisterProperties();
// ARM does not have f32 extending load.
- setLoadExtAction(ISD::EXTLOAD, EVT::f32, Expand);
+ setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
// ARM does not have i1 sign extending load.
- setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
// ARM supports all 4 flavors of integer indexed load / store.
if (!Subtarget->isThumb1Only()) {
for (unsigned im = (unsigned)ISD::PRE_INC;
im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
- setIndexedLoadAction(im, EVT::i1, Legal);
- setIndexedLoadAction(im, EVT::i8, Legal);
- setIndexedLoadAction(im, EVT::i16, Legal);
- setIndexedLoadAction(im, EVT::i32, Legal);
- setIndexedStoreAction(im, EVT::i1, Legal);
- setIndexedStoreAction(im, EVT::i8, Legal);
- setIndexedStoreAction(im, EVT::i16, Legal);
- setIndexedStoreAction(im, EVT::i32, Legal);
+ setIndexedLoadAction(im, MVT::i1, Legal);
+ setIndexedLoadAction(im, MVT::i8, Legal);
+ setIndexedLoadAction(im, MVT::i16, Legal);
+ setIndexedLoadAction(im, MVT::i32, Legal);
+ setIndexedStoreAction(im, MVT::i1, Legal);
+ setIndexedStoreAction(im, MVT::i8, Legal);
+ setIndexedStoreAction(im, MVT::i16, Legal);
+ setIndexedStoreAction(im, MVT::i32, Legal);
}
}
// i64 operation support.
if (Subtarget->isThumb1Only()) {
- setOperationAction(ISD::MUL, EVT::i64, Expand);
- setOperationAction(ISD::MULHU, EVT::i32, Expand);
- setOperationAction(ISD::MULHS, EVT::i32, Expand);
- setOperationAction(ISD::UMUL_LOHI, EVT::i32, Expand);
- setOperationAction(ISD::SMUL_LOHI, EVT::i32, Expand);
+ setOperationAction(ISD::MUL, MVT::i64, Expand);
+ setOperationAction(ISD::MULHU, MVT::i32, Expand);
+ setOperationAction(ISD::MULHS, MVT::i32, Expand);
+ setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
+ setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
} else {
- setOperationAction(ISD::MUL, EVT::i64, Expand);
- setOperationAction(ISD::MULHU, EVT::i32, Expand);
+ setOperationAction(ISD::MUL, MVT::i64, Expand);
+ setOperationAction(ISD::MULHU, MVT::i32, Expand);
if (!Subtarget->hasV6Ops())
- setOperationAction(ISD::MULHS, EVT::i32, Expand);
+ setOperationAction(ISD::MULHS, MVT::i32, Expand);
}
- setOperationAction(ISD::SHL_PARTS, EVT::i32, Expand);
- setOperationAction(ISD::SRA_PARTS, EVT::i32, Expand);
- setOperationAction(ISD::SRL_PARTS, EVT::i32, Expand);
- setOperationAction(ISD::SRL, EVT::i64, Custom);
- setOperationAction(ISD::SRA, EVT::i64, Custom);
+ setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SRL, MVT::i64, Custom);
+ setOperationAction(ISD::SRA, MVT::i64, Custom);
// ARM does not have ROTL.
- setOperationAction(ISD::ROTL, EVT::i32, Expand);
- setOperationAction(ISD::CTTZ, EVT::i32, Expand);
- setOperationAction(ISD::CTPOP, EVT::i32, Expand);
+ setOperationAction(ISD::ROTL, MVT::i32, Expand);
+ setOperationAction(ISD::CTTZ, MVT::i32, Expand);
+ setOperationAction(ISD::CTPOP, MVT::i32, Expand);
if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
- setOperationAction(ISD::CTLZ, EVT::i32, Expand);
+ setOperationAction(ISD::CTLZ, MVT::i32, Expand);
// Only ARMv6 has BSWAP.
if (!Subtarget->hasV6Ops())
- setOperationAction(ISD::BSWAP, EVT::i32, Expand);
+ setOperationAction(ISD::BSWAP, MVT::i32, Expand);
// These are expanded into libcalls.
- setOperationAction(ISD::SDIV, EVT::i32, Expand);
- setOperationAction(ISD::UDIV, EVT::i32, Expand);
- setOperationAction(ISD::SREM, EVT::i32, Expand);
- setOperationAction(ISD::UREM, EVT::i32, Expand);
- setOperationAction(ISD::SDIVREM, EVT::i32, Expand);
- setOperationAction(ISD::UDIVREM, EVT::i32, Expand);
+ setOperationAction(ISD::SDIV, MVT::i32, Expand);
+ setOperationAction(ISD::UDIV, MVT::i32, Expand);
+ setOperationAction(ISD::SREM, MVT::i32, Expand);
+ setOperationAction(ISD::UREM, MVT::i32, Expand);
+ setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
+ setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
// Support label based line numbers.
- setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand);
+ setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
- setOperationAction(ISD::GlobalAddress, EVT::i32, Custom);
- setOperationAction(ISD::ConstantPool, EVT::i32, Custom);
- setOperationAction(ISD::GLOBAL_OFFSET_TABLE, EVT::i32, Custom);
- setOperationAction(ISD::GlobalTLSAddress, EVT::i32, Custom);
+ setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
+ setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
+ setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
+ setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
// Use the default implementation.
- setOperationAction(ISD::VASTART, EVT::Other, Custom);
- setOperationAction(ISD::VAARG, EVT::Other, Expand);
- setOperationAction(ISD::VACOPY, EVT::Other, Expand);
- setOperationAction(ISD::VAEND, EVT::Other, Expand);
- setOperationAction(ISD::STACKSAVE, EVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE, EVT::Other, Expand);
+ setOperationAction(ISD::VASTART, MVT::Other, Custom);
+ setOperationAction(ISD::VAARG, MVT::Other, Expand);
+ setOperationAction(ISD::VACOPY, MVT::Other, Expand);
+ setOperationAction(ISD::VAEND, MVT::Other, Expand);
+ setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
if (Subtarget->isThumb())
- setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32, Custom);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
else
- setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32, Expand);
- setOperationAction(ISD::MEMBARRIER, EVT::Other, Expand);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
+ setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
if (!Subtarget->hasV6Ops() && !Subtarget->isThumb2()) {
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i16, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i8, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
}
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only())
// Turn f64->i64 into FMRRD, i64 -> f64 to FMDRR iff target supports vfp2.
- setOperationAction(ISD::BIT_CONVERT, EVT::i64, Custom);
+ setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
// We want to custom lower some of our intrinsics.
- setOperationAction(ISD::INTRINSIC_WO_CHAIN, EVT::Other, Custom);
- setOperationAction(ISD::INTRINSIC_W_CHAIN, EVT::Other, Custom);
- setOperationAction(ISD::INTRINSIC_VOID, EVT::Other, Custom);
-
- setOperationAction(ISD::SETCC, EVT::i32, Expand);
- setOperationAction(ISD::SETCC, EVT::f32, Expand);
- setOperationAction(ISD::SETCC, EVT::f64, Expand);
- setOperationAction(ISD::SELECT, EVT::i32, Expand);
- setOperationAction(ISD::SELECT, EVT::f32, Expand);
- setOperationAction(ISD::SELECT, EVT::f64, Expand);
- setOperationAction(ISD::SELECT_CC, EVT::i32, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::f32, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::f64, Custom);
-
- setOperationAction(ISD::BRCOND, EVT::Other, Expand);
- setOperationAction(ISD::BR_CC, EVT::i32, Custom);
- setOperationAction(ISD::BR_CC, EVT::f32, Custom);
- setOperationAction(ISD::BR_CC, EVT::f64, Custom);
- setOperationAction(ISD::BR_JT, EVT::Other, Custom);
+ setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
+ setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
+ setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
+
+ setOperationAction(ISD::SETCC, MVT::i32, Expand);
+ setOperationAction(ISD::SETCC, MVT::f32, Expand);
+ setOperationAction(ISD::SETCC, MVT::f64, Expand);
+ setOperationAction(ISD::SELECT, MVT::i32, Expand);
+ setOperationAction(ISD::SELECT, MVT::f32, Expand);
+ setOperationAction(ISD::SELECT, MVT::f64, Expand);
+ setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
+
+ setOperationAction(ISD::BRCOND, MVT::Other, Expand);
+ setOperationAction(ISD::BR_CC, MVT::i32, Custom);
+ setOperationAction(ISD::BR_CC, MVT::f32, Custom);
+ setOperationAction(ISD::BR_CC, MVT::f64, Custom);
+ setOperationAction(ISD::BR_JT, MVT::Other, Custom);
// We don't support sin/cos/fmod/copysign/pow
- setOperationAction(ISD::FSIN, EVT::f64, Expand);
- setOperationAction(ISD::FSIN, EVT::f32, Expand);
- setOperationAction(ISD::FCOS, EVT::f32, Expand);
- setOperationAction(ISD::FCOS, EVT::f64, Expand);
- setOperationAction(ISD::FREM, EVT::f64, Expand);
- setOperationAction(ISD::FREM, EVT::f32, Expand);
+ setOperationAction(ISD::FSIN, MVT::f64, Expand);
+ setOperationAction(ISD::FSIN, MVT::f32, Expand);
+ setOperationAction(ISD::FCOS, MVT::f32, Expand);
+ setOperationAction(ISD::FCOS, MVT::f64, Expand);
+ setOperationAction(ISD::FREM, MVT::f64, Expand);
+ setOperationAction(ISD::FREM, MVT::f32, Expand);
if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
- setOperationAction(ISD::FCOPYSIGN, EVT::f64, Custom);
- setOperationAction(ISD::FCOPYSIGN, EVT::f32, Custom);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
}
- setOperationAction(ISD::FPOW, EVT::f64, Expand);
- setOperationAction(ISD::FPOW, EVT::f32, Expand);
+ setOperationAction(ISD::FPOW, MVT::f64, Expand);
+ setOperationAction(ISD::FPOW, MVT::f32, Expand);
// int <-> fp are custom expanded into bit_convert + ARMISD ops.
if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
- setOperationAction(ISD::SINT_TO_FP, EVT::i32, Custom);
- setOperationAction(ISD::UINT_TO_FP, EVT::i32, Custom);
- setOperationAction(ISD::FP_TO_UINT, EVT::i32, Custom);
- setOperationAction(ISD::FP_TO_SINT, EVT::i32, Custom);
+ setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
+ setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
+ setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
}
// We have target-specific dag combine patterns for the following nodes:
@@ -585,7 +585,7 @@
CCState &State) {
if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
return false;
- if (LocVT == EVT::v2f64 &&
+ if (LocVT == MVT::v2f64 &&
!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
return false;
return true; // we handled it
@@ -628,7 +628,7 @@
CCState &State) {
if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
return false;
- if (LocVT == EVT::v2f64 &&
+ if (LocVT == MVT::v2f64 &&
!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
return false;
return true; // we handled it
@@ -660,7 +660,7 @@
CCState &State) {
if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
return false;
- if (LocVT == EVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
+ if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
return false;
return true; // we handled it
}
@@ -725,33 +725,33 @@
SDValue Val;
if (VA.needsCustom()) {
// Handle f64 or half of a v2f64.
- SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), EVT::i32,
+ SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
InFlag);
Chain = Lo.getValue(1);
InFlag = Lo.getValue(2);
VA = RVLocs[++i]; // skip ahead to next loc
- SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), EVT::i32,
+ SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
InFlag);
Chain = Hi.getValue(1);
InFlag = Hi.getValue(2);
- Val = DAG.getNode(ARMISD::FMDRR, dl, EVT::f64, Lo, Hi);
+ Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
- if (VA.getLocVT() == EVT::v2f64) {
- SDValue Vec = DAG.getNode(ISD::UNDEF, dl, EVT::v2f64);
- Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v2f64, Vec, Val,
- DAG.getConstant(0, EVT::i32));
+ if (VA.getLocVT() == MVT::v2f64) {
+ SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
+ Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
+ DAG.getConstant(0, MVT::i32));
VA = RVLocs[++i]; // skip ahead to next loc
- Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), EVT::i32, InFlag);
+ Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
Chain = Lo.getValue(1);
InFlag = Lo.getValue(2);
VA = RVLocs[++i]; // skip ahead to next loc
- Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), EVT::i32, InFlag);
+ Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
Chain = Hi.getValue(1);
InFlag = Hi.getValue(2);
- Val = DAG.getNode(ARMISD::FMDRR, dl, EVT::f64, Lo, Hi);
- Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v2f64, Vec, Val,
- DAG.getConstant(1, EVT::i32));
+ Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
+ Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
+ DAG.getConstant(1, MVT::i32));
}
} else {
Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
@@ -784,7 +784,7 @@
CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
DebugLoc dl) {
- SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), EVT::i32);
+ SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
/*AlwaysInline=*/false, NULL, 0, NULL, 0);
}
@@ -815,7 +815,7 @@
ISD::ArgFlagsTy Flags) {
SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
- DAG.getVTList(EVT::i32, EVT::i32), Arg);
+ DAG.getVTList(MVT::i32, MVT::i32), Arg);
RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
if (NextVA.isRegLoc())
@@ -858,7 +858,7 @@
// These operations are automatically eliminated by the prolog/epilog pass
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
- SDValue StackPtr = DAG.getRegister(ARM::SP, EVT::i32);
+ SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
RegsToPassVector RegsToPass;
SmallVector<SDValue, 8> MemOpChains;
@@ -892,11 +892,11 @@
// f64 and v2f64 might be passed in i32 pairs and must be split into pieces
if (VA.needsCustom()) {
- if (VA.getLocVT() == EVT::v2f64) {
- SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f64, Arg,
- DAG.getConstant(0, EVT::i32));
- SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f64, Arg,
- DAG.getConstant(1, EVT::i32));
+ if (VA.getLocVT() == MVT::v2f64) {
+ SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
+ DAG.getConstant(0, MVT::i32));
+ SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
+ DAG.getConstant(1, MVT::i32));
PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
@@ -930,7 +930,7 @@
}
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token chain
@@ -962,10 +962,10 @@
ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
ARMCP::CPStub, 4);
SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
- CPAddr = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, CPAddr);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
Callee = DAG.getLoad(getPointerTy(), dl,
DAG.getEntryNode(), CPAddr, NULL, 0);
- SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, EVT::i32);
+ SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
getPointerTy(), Callee, PICLabel);
} else
@@ -981,10 +981,10 @@
ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
ARMCP::CPStub, 4);
SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
- CPAddr = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, CPAddr);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
Callee = DAG.getLoad(getPointerTy(), dl,
DAG.getEntryNode(), CPAddr, NULL, 0);
- SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, EVT::i32);
+ SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
getPointerTy(), Callee, PICLabel);
} else
@@ -1005,7 +1005,7 @@
}
if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb1Only()) {
// implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
- Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(EVT::i32),InFlag);
+ Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
InFlag = Chain.getValue(1);
}
@@ -1022,7 +1022,7 @@
if (InFlag.getNode())
Ops.push_back(InFlag);
// Returns a chain and a flag for retval copy to use.
- Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(EVT::Other, EVT::Flag),
+ Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
&Ops[0], Ops.size());
InFlag = Chain.getValue(1);
@@ -1082,12 +1082,12 @@
}
if (VA.needsCustom()) {
- if (VA.getLocVT() == EVT::v2f64) {
+ if (VA.getLocVT() == MVT::v2f64) {
// Extract the first half and return it in two registers.
- SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f64, Arg,
- DAG.getConstant(0, EVT::i32));
+ SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
+ DAG.getConstant(0, MVT::i32));
SDValue HalfGPRs = DAG.getNode(ARMISD::FMRRD, dl,
- DAG.getVTList(EVT::i32, EVT::i32), Half);
+ DAG.getVTList(MVT::i32, MVT::i32), Half);
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
Flag = Chain.getValue(1);
@@ -1098,13 +1098,13 @@
VA = RVLocs[++i]; // skip ahead to next loc
// Extract the 2nd half and fall through to handle it as an f64 value.
- Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f64, Arg,
- DAG.getConstant(1, EVT::i32));
+ Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
+ DAG.getConstant(1, MVT::i32));
}
// Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
// available.
SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
- DAG.getVTList(EVT::i32, EVT::i32), &Arg, 1);
+ DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
Flag = Chain.getValue(1);
VA = RVLocs[++i]; // skip ahead to next loc
@@ -1120,9 +1120,9 @@
SDValue result;
if (Flag.getNode())
- result = DAG.getNode(ARMISD::RET_FLAG, dl, EVT::Other, Chain, Flag);
+ result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
else // Return Void
- result = DAG.getNode(ARMISD::RET_FLAG, dl, EVT::Other, Chain);
+ result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
return result;
}
@@ -1145,7 +1145,7 @@
else
Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
CP->getAlignment());
- return DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, Res);
+ return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
}
// Lower ISD::GlobalTLSAddress using the "general dynamic" model
@@ -1159,11 +1159,11 @@
new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
PCAdj, "tlsgd", true);
SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
- Argument = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, Argument);
+ Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0);
SDValue Chain = Argument.getValue(1);
- SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, EVT::i32);
+ SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
// call __tls_get_addr.
@@ -1200,11 +1200,11 @@
new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
PCAdj, "gottpoff", true);
Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
- Offset = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, Offset);
+ Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
Chain = Offset.getValue(1);
- SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, EVT::i32);
+ SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
@@ -1213,7 +1213,7 @@
ARMConstantPoolValue *CPV =
new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
- Offset = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, Offset);
+ Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
}
@@ -1247,7 +1247,7 @@
ARMConstantPoolValue *CPV =
new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
- CPAddr = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, CPAddr);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
CPAddr, NULL, 0);
SDValue Chain = Result.getValue(1);
@@ -1258,7 +1258,7 @@
return Result;
} else {
SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
- CPAddr = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, CPAddr);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
}
}
@@ -1293,13 +1293,13 @@
Kind, PCAdj);
CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
}
- CPAddr = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, CPAddr);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
SDValue Chain = Result.getValue(1);
if (RelocM == Reloc::PIC_) {
- SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, EVT::i32);
+ SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
}
if (IsIndirect)
@@ -1319,9 +1319,9 @@
ARMPCLabelIndex,
ARMCP::CPValue, PCAdj);
SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
- CPAddr = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, CPAddr);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
- SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, EVT::i32);
+ SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
}
@@ -1353,7 +1353,7 @@
Ops.push_back(Node->getOperand(2));
for (unsigned N = 0; N < NumVecs; ++N)
Ops.push_back(Node->getOperand(N + 3));
- return DAG.getNode(Opcode, dl, EVT::Other, Ops.data(), Ops.size());
+ return DAG.getNode(Opcode, dl, MVT::Other, Ops.data(), Ops.size());
}
SDValue
@@ -1406,19 +1406,19 @@
ARMConstantPoolValue *CPV =
new ARMConstantPoolValue(LSDAName.c_str(), ARMPCLabelIndex, Kind, PCAdj);
CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
- CPAddr = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, CPAddr);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
SDValue Result =
DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
SDValue Chain = Result.getValue(1);
if (RelocM == Reloc::PIC_) {
- SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, EVT::i32);
+ SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
}
return Result;
}
case Intrinsic::eh_sjlj_setjmp:
- return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, EVT::i32, Op.getOperand(1));
+ return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(1));
}
}
@@ -1470,7 +1470,7 @@
Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
}
- SDVTList VTList = DAG.getVTList(VT, EVT::Other);
+ SDVTList VTList = DAG.getVTList(VT, MVT::Other);
SDValue Ops1[] = { Chain, Size, Align };
SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
Chain = Res.getValue(1);
@@ -1495,7 +1495,7 @@
// Transform the arguments stored in physical registers into virtual ones.
unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
- SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, EVT::i32);
+ SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
SDValue ArgValue2;
if (NextVA.isMemLoc()) {
@@ -1505,13 +1505,13 @@
// Create load node to retrieve arguments from the stack.
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
- ArgValue2 = DAG.getLoad(EVT::i32, dl, Root, FIN, NULL, 0);
+ ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0);
} else {
Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
- ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, EVT::i32);
+ ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
}
- return DAG.getNode(ARMISD::FMDRR, dl, EVT::f64, ArgValue, ArgValue2);
+ return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2);
}
SDValue
@@ -1548,18 +1548,18 @@
if (VA.needsCustom()) {
// f64 and vector types are split up into multiple registers or
// combinations of registers and stack slots.
- RegVT = EVT::i32;
+ RegVT = MVT::i32;
- if (VA.getLocVT() == EVT::v2f64) {
+ if (VA.getLocVT() == MVT::v2f64) {
SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
Chain, DAG, dl);
VA = ArgLocs[++i]; // skip ahead to next loc
SDValue ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
Chain, DAG, dl);
- ArgValue = DAG.getNode(ISD::UNDEF, dl, EVT::v2f64);
- ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v2f64,
+ ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
+ ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
- ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v2f64,
+ ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
} else
ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
@@ -1567,13 +1567,13 @@
} else {
TargetRegisterClass *RC;
- if (RegVT == EVT::f32)
+ if (RegVT == MVT::f32)
RC = ARM::SPRRegisterClass;
- else if (RegVT == EVT::f64)
+ else if (RegVT == MVT::f64)
RC = ARM::DPRRegisterClass;
- else if (RegVT == EVT::v2f64)
+ else if (RegVT == MVT::v2f64)
RC = ARM::QPRRegisterClass;
- else if (RegVT == EVT::i32)
+ else if (RegVT == MVT::i32)
RC = (AFI->isThumb1OnlyFunction() ?
ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
else
@@ -1611,7 +1611,7 @@
// sanity check
assert(VA.isMemLoc());
- assert(VA.getValVT() != EVT::i64 && "i64 should already be lowered");
+ assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset());
@@ -1654,14 +1654,14 @@
RC = ARM::GPRRegisterClass;
unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
- SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, EVT::i32);
+ SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
MemOps.push_back(Store);
FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
DAG.getConstant(4, getPointerTy()));
}
if (!MemOps.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOps[0], MemOps.size());
} else
// This will point to the next argument passed via stack.
@@ -1707,28 +1707,28 @@
case ISD::SETGE:
if (isLegalCmpImmediate(C-1, isThumb1Only)) {
CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
- RHS = DAG.getConstant(C-1, EVT::i32);
+ RHS = DAG.getConstant(C-1, MVT::i32);
}
break;
case ISD::SETULT:
case ISD::SETUGE:
if (C > 0 && isLegalCmpImmediate(C-1, isThumb1Only)) {
CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
- RHS = DAG.getConstant(C-1, EVT::i32);
+ RHS = DAG.getConstant(C-1, MVT::i32);
}
break;
case ISD::SETLE:
case ISD::SETGT:
if (isLegalCmpImmediate(C+1, isThumb1Only)) {
CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
- RHS = DAG.getConstant(C+1, EVT::i32);
+ RHS = DAG.getConstant(C+1, MVT::i32);
}
break;
case ISD::SETULE:
case ISD::SETUGT:
if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb1Only)) {
CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
- RHS = DAG.getConstant(C+1, EVT::i32);
+ RHS = DAG.getConstant(C+1, MVT::i32);
}
break;
}
@@ -1747,8 +1747,8 @@
CompareType = ARMISD::CMPZ;
break;
}
- ARMCC = DAG.getConstant(CondCode, EVT::i32);
- return DAG.getNode(CompareType, dl, EVT::Flag, LHS, RHS);
+ ARMCC = DAG.getConstant(CondCode, MVT::i32);
+ return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
}
/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
@@ -1756,10 +1756,10 @@
DebugLoc dl) {
SDValue Cmp;
if (!isFloatingPointZero(RHS))
- Cmp = DAG.getNode(ARMISD::CMPFP, dl, EVT::Flag, LHS, RHS);
+ Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
else
- Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, EVT::Flag, LHS);
- return DAG.getNode(ARMISD::FMSTAT, dl, EVT::Flag, Cmp);
+ Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
+ return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
}
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
@@ -1772,9 +1772,9 @@
SDValue FalseVal = Op.getOperand(3);
DebugLoc dl = Op.getDebugLoc();
- if (LHS.getValueType() == EVT::i32) {
+ if (LHS.getValueType() == MVT::i32) {
SDValue ARMCC;
- SDValue CCR = DAG.getRegister(ARM::CPSR, EVT::i32);
+ SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl);
return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
}
@@ -1783,13 +1783,13 @@
if (FPCCToARMCC(CC, CondCode, CondCode2))
std::swap(TrueVal, FalseVal);
- SDValue ARMCC = DAG.getConstant(CondCode, EVT::i32);
- SDValue CCR = DAG.getRegister(ARM::CPSR, EVT::i32);
+ SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
+ SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
ARMCC, CCR, Cmp);
if (CondCode2 != ARMCC::AL) {
- SDValue ARMCC2 = DAG.getConstant(CondCode2, EVT::i32);
+ SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
// FIXME: Needs another CMP because flag can have but one use.
SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
Result = DAG.getNode(ARMISD::CMOV, dl, VT,
@@ -1807,28 +1807,28 @@
SDValue Dest = Op.getOperand(4);
DebugLoc dl = Op.getDebugLoc();
- if (LHS.getValueType() == EVT::i32) {
+ if (LHS.getValueType() == MVT::i32) {
SDValue ARMCC;
- SDValue CCR = DAG.getRegister(ARM::CPSR, EVT::i32);
+ SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl);
- return DAG.getNode(ARMISD::BRCOND, dl, EVT::Other,
+ return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
Chain, Dest, ARMCC, CCR,Cmp);
}
- assert(LHS.getValueType() == EVT::f32 || LHS.getValueType() == EVT::f64);
+ assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
ARMCC::CondCodes CondCode, CondCode2;
if (FPCCToARMCC(CC, CondCode, CondCode2))
// Swap the LHS/RHS of the comparison if needed.
std::swap(LHS, RHS);
SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
- SDValue ARMCC = DAG.getConstant(CondCode, EVT::i32);
- SDValue CCR = DAG.getRegister(ARM::CPSR, EVT::i32);
- SDVTList VTList = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
+ SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
+ SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
if (CondCode2 != ARMCC::AL) {
- ARMCC = DAG.getConstant(CondCode2, EVT::i32);
+ ARMCC = DAG.getConstant(CondCode2, MVT::i32);
SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
}
@@ -1846,7 +1846,7 @@
ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
- Table = DAG.getNode(ARMISD::WrapperJT, dl, EVT::i32, JTI, UId);
+ Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
if (Subtarget->isThumb2()) {
@@ -1854,18 +1854,18 @@
// which does another jump to the destination. This also makes it easier
// to translate it to TBB / TBH later.
// FIXME: This might not work if the function is extremely large.
- return DAG.getNode(ARMISD::BR2_JT, dl, EVT::Other, Chain,
+ return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
Addr, Op.getOperand(2), JTI, UId);
}
if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
- Addr = DAG.getLoad((EVT)EVT::i32, dl, Chain, Addr, NULL, 0);
+ Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, NULL, 0);
Chain = Addr.getValue(1);
Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
- return DAG.getNode(ARMISD::BR_JT, dl, EVT::Other, Chain, Addr, JTI, UId);
+ return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
} else {
Addr = DAG.getLoad(PTy, dl, Chain, Addr, NULL, 0);
Chain = Addr.getValue(1);
- return DAG.getNode(ARMISD::BR_JT, dl, EVT::Other, Chain, Addr, JTI, UId);
+ return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
}
}
@@ -1873,8 +1873,8 @@
DebugLoc dl = Op.getDebugLoc();
unsigned Opc =
Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
- Op = DAG.getNode(Opc, dl, EVT::f32, Op.getOperand(0));
- return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op);
+ Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
+ return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
}
static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
@@ -1883,7 +1883,7 @@
unsigned Opc =
Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
- Op = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, Op.getOperand(0));
+ Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
return DAG.getNode(Opc, dl, VT, Op);
}
@@ -1896,8 +1896,8 @@
EVT SrcVT = Tmp1.getValueType();
SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
- SDValue ARMCC = DAG.getConstant(ARMCC::LT, EVT::i32);
- SDValue CCR = DAG.getRegister(ARM::CPSR, EVT::i32);
+ SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
+ SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
}
@@ -1939,7 +1939,7 @@
unsigned BytesLeft = SizeVal & 3;
unsigned NumMemOps = SizeVal >> 2;
unsigned EmittedNumMemOps = 0;
- EVT VT = EVT::i32;
+ EVT VT = MVT::i32;
unsigned VTSize = 4;
unsigned i = 0;
const unsigned MAX_LOADS_IN_LDM = 6;
@@ -1954,23 +1954,23 @@
for (i = 0;
i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
Loads[i] = DAG.getLoad(VT, dl, Chain,
- DAG.getNode(ISD::ADD, dl, EVT::i32, Src,
- DAG.getConstant(SrcOff, EVT::i32)),
+ DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
+ DAG.getConstant(SrcOff, MVT::i32)),
SrcSV, SrcSVOff + SrcOff);
TFOps[i] = Loads[i].getValue(1);
SrcOff += VTSize;
}
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &TFOps[0], i);
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
for (i = 0;
i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
- DAG.getNode(ISD::ADD, dl, EVT::i32, Dst,
- DAG.getConstant(DstOff, EVT::i32)),
+ DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
+ DAG.getConstant(DstOff, MVT::i32)),
DstSV, DstSVOff + DstOff);
DstOff += VTSize;
}
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &TFOps[0], i);
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
EmittedNumMemOps += i;
}
@@ -1983,64 +1983,64 @@
i = 0;
while (BytesLeft) {
if (BytesLeft >= 2) {
- VT = EVT::i16;
+ VT = MVT::i16;
VTSize = 2;
} else {
- VT = EVT::i8;
+ VT = MVT::i8;
VTSize = 1;
}
Loads[i] = DAG.getLoad(VT, dl, Chain,
- DAG.getNode(ISD::ADD, dl, EVT::i32, Src,
- DAG.getConstant(SrcOff, EVT::i32)),
+ DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
+ DAG.getConstant(SrcOff, MVT::i32)),
SrcSV, SrcSVOff + SrcOff);
TFOps[i] = Loads[i].getValue(1);
++i;
SrcOff += VTSize;
BytesLeft -= VTSize;
}
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &TFOps[0], i);
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
i = 0;
BytesLeft = BytesLeftSave;
while (BytesLeft) {
if (BytesLeft >= 2) {
- VT = EVT::i16;
+ VT = MVT::i16;
VTSize = 2;
} else {
- VT = EVT::i8;
+ VT = MVT::i8;
VTSize = 1;
}
TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
- DAG.getNode(ISD::ADD, dl, EVT::i32, Dst,
- DAG.getConstant(DstOff, EVT::i32)),
+ DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
+ DAG.getConstant(DstOff, MVT::i32)),
DstSV, DstSVOff + DstOff);
++i;
DstOff += VTSize;
BytesLeft -= VTSize;
}
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &TFOps[0], i);
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
}
static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
SDValue Op = N->getOperand(0);
DebugLoc dl = N->getDebugLoc();
- if (N->getValueType(0) == EVT::f64) {
+ if (N->getValueType(0) == MVT::f64) {
// Turn i64->f64 into FMDRR.
- SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Op,
- DAG.getConstant(0, EVT::i32));
- SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Op,
- DAG.getConstant(1, EVT::i32));
- return DAG.getNode(ARMISD::FMDRR, dl, EVT::f64, Lo, Hi);
+ SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
+ DAG.getConstant(0, MVT::i32));
+ SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
+ DAG.getConstant(1, MVT::i32));
+ return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
}
// Turn f64->i64 into FMRRD.
SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl,
- DAG.getVTList(EVT::i32, EVT::i32), &Op, 1);
+ DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
// Merge the pieces into a single i64 value.
- return DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i64, Cvt, Cvt.getValue(1));
+ return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
}
/// getZeroVector - Returns a vector of specified type with all zero elements.
@@ -2055,11 +2055,11 @@
// the future, always build zero vectors as <4 x i32> or <2 x i32> bitcasted
// to their dest type. This ensures they get CSE'd.
SDValue Vec;
- SDValue Cst = DAG.getTargetConstant(0, EVT::i32);
+ SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
if (VT.getSizeInBits() == 64)
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v2i32, Cst, Cst);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
else
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, Cst, Cst, Cst, Cst);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
}
@@ -2072,11 +2072,11 @@
// Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
// type. This ensures they get CSE'd.
SDValue Vec;
- SDValue Cst = DAG.getTargetConstant(~0U, EVT::i32);
+ SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
if (VT.getSizeInBits() == 64)
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v2i32, Cst, Cst);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
else
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, Cst, Cst, Cst, Cst);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
}
@@ -2093,7 +2093,7 @@
// Left shifts translate directly to the vshiftu intrinsic.
if (N->getOpcode() == ISD::SHL)
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
- DAG.getConstant(Intrinsic::arm_neon_vshiftu, EVT::i32),
+ DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
N->getOperand(0), N->getOperand(1));
assert((N->getOpcode() == ISD::SRA ||
@@ -2110,11 +2110,11 @@
Intrinsic::arm_neon_vshifts :
Intrinsic::arm_neon_vshiftu);
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
- DAG.getConstant(vshiftInt, EVT::i32),
+ DAG.getConstant(vshiftInt, MVT::i32),
N->getOperand(0), NegatedCount);
}
- assert(VT == EVT::i64 &&
+ assert(VT == MVT::i64 &&
(N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
"Unknown shift to lower!");
@@ -2127,21 +2127,21 @@
if (ST->isThumb1Only()) return SDValue();
// Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
- SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, N->getOperand(0),
- DAG.getConstant(0, EVT::i32));
- SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, N->getOperand(0),
- DAG.getConstant(1, EVT::i32));
+ SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
+ DAG.getConstant(0, MVT::i32));
+ SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
+ DAG.getConstant(1, MVT::i32));
// First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
// captures the result into a carry flag.
unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
- Hi = DAG.getNode(Opc, dl, DAG.getVTList(EVT::i32, EVT::Flag), &Hi, 1);
+ Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
// The low part is an ARMISD::RRX operand, which shifts the carry in.
- Lo = DAG.getNode(ARMISD::RRX, dl, EVT::i32, Lo, Hi.getValue(1));
+ Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
// Merge the pieces into a single i64 value.
- return DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i64, Lo, Hi);
+ return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
}
static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
@@ -2252,13 +2252,13 @@
case 8:
// Any 1-byte value is OK.
assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
- return DAG.getTargetConstant(SplatBits, EVT::i8);
+ return DAG.getTargetConstant(SplatBits, MVT::i8);
case 16:
// NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
if ((SplatBits & ~0xff) == 0 ||
(SplatBits & ~0xff00) == 0)
- return DAG.getTargetConstant(SplatBits, EVT::i16);
+ return DAG.getTargetConstant(SplatBits, MVT::i16);
break;
case 32:
@@ -2270,15 +2270,15 @@
(SplatBits & ~0xff00) == 0 ||
(SplatBits & ~0xff0000) == 0 ||
(SplatBits & ~0xff000000) == 0)
- return DAG.getTargetConstant(SplatBits, EVT::i32);
+ return DAG.getTargetConstant(SplatBits, MVT::i32);
if ((SplatBits & ~0xffff) == 0 &&
((SplatBits | SplatUndef) & 0xff) == 0xff)
- return DAG.getTargetConstant(SplatBits | 0xff, EVT::i32);
+ return DAG.getTargetConstant(SplatBits | 0xff, MVT::i32);
if ((SplatBits & ~0xffffff) == 0 &&
((SplatBits | SplatUndef) & 0xffff) == 0xffff)
- return DAG.getTargetConstant(SplatBits | 0xffff, EVT::i32);
+ return DAG.getTargetConstant(SplatBits | 0xffff, MVT::i32);
// Note: there are a few 32-bit splat values (specifically: 00ffff00,
// ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
@@ -2298,7 +2298,7 @@
return SDValue();
BitMask <<= 8;
}
- return DAG.getTargetConstant(Val, EVT::i64);
+ return DAG.getTargetConstant(Val, MVT::i64);
}
default:
@@ -2364,19 +2364,19 @@
EVT CanonicalVT;
if (VT.is64BitVector()) {
switch (Val.getValueType().getSizeInBits()) {
- case 8: CanonicalVT = EVT::v8i8; break;
- case 16: CanonicalVT = EVT::v4i16; break;
- case 32: CanonicalVT = EVT::v2i32; break;
- case 64: CanonicalVT = EVT::v1i64; break;
+ case 8: CanonicalVT = MVT::v8i8; break;
+ case 16: CanonicalVT = MVT::v4i16; break;
+ case 32: CanonicalVT = MVT::v2i32; break;
+ case 64: CanonicalVT = MVT::v1i64; break;
default: llvm_unreachable("unexpected splat element type"); break;
}
} else {
assert(VT.is128BitVector() && "unknown splat vector size");
switch (Val.getValueType().getSizeInBits()) {
- case 8: CanonicalVT = EVT::v16i8; break;
- case 16: CanonicalVT = EVT::v8i16; break;
- case 32: CanonicalVT = EVT::v4i32; break;
- case 64: CanonicalVT = EVT::v2i64; break;
+ case 8: CanonicalVT = MVT::v16i8; break;
+ case 16: CanonicalVT = MVT::v8i16; break;
+ case 32: CanonicalVT = MVT::v4i32; break;
+ case 64: CanonicalVT = MVT::v2i64; break;
default: llvm_unreachable("unexpected splat element type"); break;
}
}
@@ -2438,12 +2438,12 @@
static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
EVT VT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
- assert((VT == EVT::i8 || VT == EVT::i16) &&
+ assert((VT == MVT::i8 || VT == MVT::i16) &&
"unexpected type for custom-lowering vector extract");
SDValue Vec = Op.getOperand(0);
SDValue Lane = Op.getOperand(1);
- Op = DAG.getNode(ARMISD::VGETLANEu, dl, EVT::i32, Vec, Lane);
- Op = DAG.getNode(ISD::AssertZext, dl, EVT::i32, Op, DAG.getValueType(VT));
+ Op = DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
+ Op = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Op, DAG.getValueType(VT));
return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
}
@@ -2453,16 +2453,16 @@
assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
"unexpected CONCAT_VECTORS");
DebugLoc dl = Op.getDebugLoc();
- SDValue Val = DAG.getUNDEF(EVT::v2f64);
+ SDValue Val = DAG.getUNDEF(MVT::v2f64);
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
if (Op0.getOpcode() != ISD::UNDEF)
- Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v2f64, Val,
- DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f64, Op0),
+ Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
DAG.getIntPtrConstant(0));
if (Op1.getOpcode() != ISD::UNDEF)
- Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v2f64, Val,
- DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f64, Op1),
+ Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
DAG.getIntPtrConstant(1));
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
}
@@ -2955,7 +2955,7 @@
}
return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
- N->getOperand(1), DAG.getConstant(Cnt, EVT::i32));
+ N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
}
case Intrinsic::arm_neon_vshiftins: {
@@ -2973,7 +2973,7 @@
return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
N->getOperand(1), N->getOperand(2),
- DAG.getConstant(Cnt, EVT::i32));
+ DAG.getConstant(Cnt, MVT::i32));
}
case Intrinsic::arm_neon_vqrshifts:
@@ -3007,7 +3007,7 @@
case ISD::SHL:
if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
- DAG.getConstant(Cnt, EVT::i32));
+ DAG.getConstant(Cnt, MVT::i32));
break;
case ISD::SRA:
@@ -3016,7 +3016,7 @@
unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
ARMISD::VSHRs : ARMISD::VSHRu);
return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
- DAG.getConstant(Cnt, EVT::i32));
+ DAG.getConstant(Cnt, MVT::i32));
}
}
return SDValue();
@@ -3039,8 +3039,8 @@
EVT EltVT = N0.getValueType();
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
- if (VT == EVT::i32 &&
- (EltVT == EVT::i8 || EltVT == EVT::i16) &&
+ if (VT == MVT::i32 &&
+ (EltVT == MVT::i8 || EltVT == MVT::i16) &&
TLI.isTypeLegal(Vec.getValueType())) {
unsigned Opc = 0;
@@ -3098,17 +3098,17 @@
return false;
unsigned Scale = 1;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: return false;
- case EVT::i1:
- case EVT::i8:
+ case MVT::i1:
+ case MVT::i8:
// Scale == 1;
break;
- case EVT::i16:
+ case MVT::i16:
// Scale == 2;
Scale = 2;
break;
- case EVT::i32:
+ case MVT::i32:
// Scale == 4;
Scale = 4;
break;
@@ -3122,18 +3122,18 @@
if (V < 0)
V = - V;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: return false;
- case EVT::i1:
- case EVT::i8:
- case EVT::i32:
+ case MVT::i1:
+ case MVT::i8:
+ case MVT::i32:
// +- imm12
return V == (V & ((1LL << 12) - 1));
- case EVT::i16:
+ case MVT::i16:
// +- imm8
return V == (V & ((1LL << 8) - 1));
- case EVT::f32:
- case EVT::f64:
+ case MVT::f32:
+ case MVT::f64:
if (!Subtarget->hasVFP2())
return false;
if ((V & 3) != 0)
@@ -3171,12 +3171,12 @@
return false;
int Scale = AM.Scale;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: return false;
- case EVT::i1:
- case EVT::i8:
- case EVT::i32:
- case EVT::i64:
+ case MVT::i1:
+ case MVT::i8:
+ case MVT::i32:
+ case MVT::i64:
// This assumes i64 is legalized to a pair of i32. If not (i.e.
// ldrd / strd are used, then its address mode is same as i16.
// r + r
@@ -3185,13 +3185,13 @@
return true;
// r + r << imm
return isPowerOf2_32(Scale & ~1);
- case EVT::i16:
+ case MVT::i16:
// r + r
if (((unsigned)AM.HasBaseReg + Scale) <= 2)
return true;
return false;
- case EVT::isVoid:
+ case MVT::isVoid:
// Note, we allow "void" uses (basically, uses that aren't loads or
// stores), because arm allows folding a scale into many arithmetic
// operations. This should be made more precise and revisited later.
@@ -3212,7 +3212,7 @@
if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
return false;
- if (VT == EVT::i16 || ((VT == EVT::i8 || VT == EVT::i1) && isSEXTLoad)) {
+ if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
// AddressingMode 3
Base = Ptr->getOperand(0);
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
@@ -3227,7 +3227,7 @@
isInc = (Ptr->getOpcode() == ISD::ADD);
Offset = Ptr->getOperand(1);
return true;
- } else if (VT == EVT::i32 || VT == EVT::i8 || VT == EVT::i1) {
+ } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
// AddressingMode 2
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
int RHSC = (int)RHS->getZExtValue();
@@ -3420,9 +3420,9 @@
case 'r':
return std::make_pair(0U, ARM::GPRRegisterClass);
case 'w':
- if (VT == EVT::f32)
+ if (VT == MVT::f32)
return std::make_pair(0U, ARM::SPRRegisterClass);
- if (VT == EVT::f64)
+ if (VT == MVT::f64)
return std::make_pair(0U, ARM::DPRRegisterClass);
break;
}
@@ -3448,7 +3448,7 @@
ARM::R8, ARM::R9, ARM::R10, ARM::R11,
ARM::R12, ARM::LR, 0);
case 'w':
- if (VT == EVT::f32)
+ if (VT == MVT::f32)
return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
ARM::S4, ARM::S5, ARM::S6, ARM::S7,
ARM::S8, ARM::S9, ARM::S10, ARM::S11,
@@ -3457,7 +3457,7 @@
ARM::S20,ARM::S21,ARM::S22,ARM::S23,
ARM::S24,ARM::S25,ARM::S26,ARM::S27,
ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
- if (VT == EVT::f64)
+ if (VT == MVT::f64)
return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
ARM::D4, ARM::D5, ARM::D6, ARM::D7,
ARM::D8, ARM::D9, ARM::D10,ARM::D11,
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Aug 11 15:47:22 2009
@@ -129,13 +129,13 @@
// so_imm_neg_XFORM - Return a so_imm value packed into the format described for
// so_imm_neg def below.
def so_imm_neg_XFORM : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(-(int)N->getZExtValue(), EVT::i32);
+ return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
}]>;
// so_imm_not_XFORM - Return a so_imm value packed into the format described for
// so_imm_not def below.
def so_imm_not_XFORM : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(~(int)N->getZExtValue(), EVT::i32);
+ return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
}]>;
// rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
@@ -254,12 +254,12 @@
def so_imm2part_1 : SDNodeXForm<imm, [{
unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
- return CurDAG->getTargetConstant(V, EVT::i32);
+ return CurDAG->getTargetConstant(V, MVT::i32);
}]>;
def so_imm2part_2 : SDNodeXForm<imm, [{
unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
- return CurDAG->getTargetConstant(V, EVT::i32);
+ return CurDAG->getTargetConstant(V, MVT::i32);
}]>;
Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Aug 11 15:47:22 2009
@@ -277,33 +277,33 @@
// Extract D sub-registers of Q registers.
// (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
def DSubReg_i8_reg : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, EVT::i32);
+ return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
}]>;
def DSubReg_i16_reg : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, EVT::i32);
+ return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
}]>;
def DSubReg_i32_reg : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, EVT::i32);
+ return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
}]>;
def DSubReg_f64_reg : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(5 + N->getZExtValue(), EVT::i32);
+ return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
}]>;
// Extract S sub-registers of Q registers.
// (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
def SSubReg_f32_reg : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(1 + N->getZExtValue(), EVT::i32);
+ return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
}]>;
// Translate lane numbers from Q registers to D subregs.
def SubReg_i8_lane : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(N->getZExtValue() & 7, EVT::i32);
+ return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
}]>;
def SubReg_i16_lane : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(N->getZExtValue() & 3, EVT::i32);
+ return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
}]>;
def SubReg_i32_lane : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(N->getZExtValue() & 1, EVT::i32);
+ return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
}]>;
//===----------------------------------------------------------------------===//
@@ -1772,7 +1772,7 @@
def SHUFFLE_get_splat_lane : SDNodeXForm<vector_shuffle, [{
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
- return CurDAG->getTargetConstant(SVOp->getSplatIndex(), EVT::i32);
+ return CurDAG->getTargetConstant(SVOp->getSplatIndex(), MVT::i32);
}]>;
def splat_lane : PatFrag<(ops node:$lhs, node:$rhs),
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Aug 11 15:47:22 2009
@@ -19,10 +19,10 @@
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def imm_neg_XFORM : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(-(int)N->getZExtValue(), EVT::i32);
+ return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
}]>;
def imm_comp_XFORM : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), EVT::i32);
+ return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
}]>;
@@ -58,12 +58,12 @@
def thumb_immshifted_val : SDNodeXForm<imm, [{
unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
- return CurDAG->getTargetConstant(V, EVT::i32);
+ return CurDAG->getTargetConstant(V, MVT::i32);
}]>;
def thumb_immshifted_shamt : SDNodeXForm<imm, [{
unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
- return CurDAG->getTargetConstant(V, EVT::i32);
+ return CurDAG->getTargetConstant(V, MVT::i32);
}]>;
// Define Thumb specific addressing modes.
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Aug 11 15:47:22 2009
@@ -37,12 +37,12 @@
// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), EVT::i32);
+ return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
}]>;
// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(-((int)N->getZExtValue()), EVT::i32);
+ return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
}]>;
// t2_so_imm - Match a 32-bit immediate operand, which is an
@@ -97,11 +97,11 @@
/// Split a 32-bit immediate into two 16 bit parts.
def t2_lo16 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
- EVT::i32);
+ MVT::i32);
}]>;
def t2_hi16 : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, EVT::i32);
+ return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
}]>;
def t2_lo16AllZero : PatLeaf<(i32 imm), [{
Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.h?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.h Tue Aug 11 15:47:22 2009
@@ -38,7 +38,7 @@
/// Code Generation virtual methods...
const TargetRegisterClass *
- getPhysicalRegisterRegClass(unsigned Reg, EVT VT = EVT::Other) const;
+ getPhysicalRegisterRegClass(unsigned Reg, EVT VT = MVT::Other) const;
bool requiresRegisterScavenging(const MachineFunction &MF) const;
Modified: llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Tue Aug 11 15:47:22 2009
@@ -152,7 +152,7 @@
/// getI64Imm - Return a target constant with the specified value, of type
/// i64.
inline SDValue getI64Imm(int64_t Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i64);
+ return CurDAG->getTargetConstant(Imm, MVT::i64);
}
// Select - Convert the specified operand from a target-independent to a
@@ -251,8 +251,8 @@
case ISD::FrameIndex: {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
- return CurDAG->SelectNodeTo(N, Alpha::LDA, EVT::i64,
- CurDAG->getTargetFrameIndex(FI, EVT::i32),
+ return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
+ CurDAG->getTargetFrameIndex(FI, MVT::i32),
getI64Imm(0));
}
case ISD::GLOBAL_OFFSET_TABLE:
@@ -272,16 +272,16 @@
Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, N0,
Chain.getValue(1));
SDNode *CNode =
- CurDAG->getTargetNode(Alpha::JSRs, dl, EVT::Other, EVT::Flag,
+ CurDAG->getTargetNode(Alpha::JSRs, dl, MVT::Other, MVT::Flag,
Chain, Chain.getValue(1));
- Chain = CurDAG->getCopyFromReg(Chain, dl, Alpha::R27, EVT::i64,
+ Chain = CurDAG->getCopyFromReg(Chain, dl, Alpha::R27, MVT::i64,
SDValue(CNode, 1));
- return CurDAG->SelectNodeTo(N, Alpha::BISr, EVT::i64, Chain, Chain);
+ return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain);
}
case ISD::READCYCLECOUNTER: {
SDValue Chain = N->getOperand(0);
- return CurDAG->getTargetNode(Alpha::RPCC, dl, EVT::i64, EVT::Other,
+ return CurDAG->getTargetNode(Alpha::RPCC, dl, MVT::i64, MVT::Other,
Chain);
}
@@ -290,7 +290,7 @@
if (uval == 0) {
SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
- Alpha::R31, EVT::i64);
+ Alpha::R31, MVT::i64);
ReplaceUses(Op, Result);
return NULL;
}
@@ -306,17 +306,17 @@
break; //(zext (LDAH (LDA)))
//Else use the constant pool
ConstantInt *C = ConstantInt::get(Type::Int64Ty, uval);
- SDValue CPI = CurDAG->getTargetConstantPool(C, EVT::i64);
- SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, dl, EVT::i64, CPI,
+ SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
+ SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, dl, MVT::i64, CPI,
SDValue(getGlobalBaseReg(), 0));
- return CurDAG->SelectNodeTo(N, Alpha::LDQr, EVT::i64, EVT::Other,
+ return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
CPI, SDValue(Tmp, 0), CurDAG->getEntryNode());
}
case ISD::TargetConstantFP:
case ISD::ConstantFP: {
ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
- bool isDouble = N->getValueType(0) == EVT::f64;
- EVT T = isDouble ? EVT::f64 : EVT::f32;
+ bool isDouble = N->getValueType(0) == MVT::f64;
+ EVT T = isDouble ? MVT::f64 : MVT::f32;
if (CN->getValueAPF().isPosZero()) {
return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
T, CurDAG->getRegister(Alpha::F31, T),
@@ -359,18 +359,18 @@
};
SDValue tmp1 = N->getOperand(rev?1:0);
SDValue tmp2 = N->getOperand(rev?0:1);
- SDNode *cmp = CurDAG->getTargetNode(Opc, dl, EVT::f64, tmp1, tmp2);
+ SDNode *cmp = CurDAG->getTargetNode(Opc, dl, MVT::f64, tmp1, tmp2);
if (inv)
cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, dl,
- EVT::f64, SDValue(cmp, 0),
- CurDAG->getRegister(Alpha::F31, EVT::f64));
+ MVT::f64, SDValue(cmp, 0),
+ CurDAG->getRegister(Alpha::F31, MVT::f64));
switch(CC) {
case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE:
case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE:
{
- SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, dl, EVT::f64,
+ SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, dl, MVT::f64,
tmp1, tmp2);
- cmp = CurDAG->getTargetNode(Alpha::ADDT, dl, EVT::f64,
+ cmp = CurDAG->getTargetNode(Alpha::ADDT, dl, MVT::f64,
SDValue(cmp2, 0), SDValue(cmp, 0));
break;
}
@@ -378,9 +378,9 @@
}
SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, dl,
- EVT::i64, SDValue(cmp, 0));
- return CurDAG->getTargetNode(Alpha::CMPULT, dl, EVT::i64,
- CurDAG->getRegister(Alpha::R31, EVT::i64),
+ MVT::i64, SDValue(cmp, 0));
+ return CurDAG->getTargetNode(Alpha::CMPULT, dl, MVT::i64,
+ CurDAG->getRegister(Alpha::R31, MVT::i64),
SDValue(LD,0));
}
break;
@@ -406,10 +406,10 @@
if (get_zapImm(mask)) {
SDValue Z =
- SDValue(CurDAG->getTargetNode(Alpha::ZAPNOTi, dl, EVT::i64,
+ SDValue(CurDAG->getTargetNode(Alpha::ZAPNOTi, dl, MVT::i64,
N->getOperand(0).getOperand(0),
getI64Imm(get_zapImm(mask))), 0);
- return CurDAG->getTargetNode(Alpha::SRLr, dl, EVT::i64, Z,
+ return CurDAG->getTargetNode(Alpha::SRLr, dl, MVT::i64, Z,
getI64Imm(sval));
}
}
@@ -434,14 +434,14 @@
SDValue GOT = SDValue(getGlobalBaseReg(), 0);
Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R29, GOT, InFlag);
InFlag = Chain.getValue(1);
- Chain = SDValue(CurDAG->getTargetNode(Alpha::BSR, dl, EVT::Other,
- EVT::Flag, Addr.getOperand(0),
+ Chain = SDValue(CurDAG->getTargetNode(Alpha::BSR, dl, MVT::Other,
+ MVT::Flag, Addr.getOperand(0),
Chain, InFlag), 0);
} else {
Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, Addr, InFlag);
InFlag = Chain.getValue(1);
- Chain = SDValue(CurDAG->getTargetNode(Alpha::JSR, dl, EVT::Other,
- EVT::Flag, Chain, InFlag), 0);
+ Chain = SDValue(CurDAG->getTargetNode(Alpha::JSR, dl, MVT::Other,
+ MVT::Flag, Chain, InFlag), 0);
}
InFlag = Chain.getValue(1);
Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Tue Aug 11 15:47:22 2009
@@ -46,114 +46,114 @@
: TargetLowering(TM, new TargetLoweringObjectFileELF()) {
// Set up the TargetLowering object.
//I am having problems with shr n i8 1
- setShiftAmountType(EVT::i64);
+ setShiftAmountType(MVT::i64);
setBooleanContents(ZeroOrOneBooleanContent);
setUsesGlobalOffsetTable(true);
- addRegisterClass(EVT::i64, Alpha::GPRCRegisterClass);
- addRegisterClass(EVT::f64, Alpha::F8RCRegisterClass);
- addRegisterClass(EVT::f32, Alpha::F4RCRegisterClass);
+ addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
+ addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
+ addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
// We want to custom lower some of our intrinsics.
- setOperationAction(ISD::INTRINSIC_WO_CHAIN, EVT::Other, Custom);
+ setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
- setLoadExtAction(ISD::EXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::EXTLOAD, EVT::f32, Expand);
+ setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
- setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::ZEXTLOAD, EVT::i32, Expand);
+ setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Expand);
- setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::SEXTLOAD, EVT::i8, Expand);
- setLoadExtAction(ISD::SEXTLOAD, EVT::i16, Expand);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
- setTruncStoreAction(EVT::f64, EVT::f32, Expand);
+ setTruncStoreAction(MVT::f64, MVT::f32, Expand);
- // setOperationAction(ISD::BRIND, EVT::Other, Expand);
- setOperationAction(ISD::BR_JT, EVT::Other, Expand);
- setOperationAction(ISD::BR_CC, EVT::Other, Expand);
- setOperationAction(ISD::SELECT_CC, EVT::Other, Expand);
+ // setOperationAction(ISD::BRIND, MVT::Other, Expand);
+ setOperationAction(ISD::BR_JT, MVT::Other, Expand);
+ setOperationAction(ISD::BR_CC, MVT::Other, Expand);
+ setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
- setOperationAction(ISD::FREM, EVT::f32, Expand);
- setOperationAction(ISD::FREM, EVT::f64, Expand);
+ setOperationAction(ISD::FREM, MVT::f32, Expand);
+ setOperationAction(ISD::FREM, MVT::f64, Expand);
- setOperationAction(ISD::UINT_TO_FP, EVT::i64, Expand);
- setOperationAction(ISD::SINT_TO_FP, EVT::i64, Custom);
- setOperationAction(ISD::FP_TO_UINT, EVT::i64, Expand);
- setOperationAction(ISD::FP_TO_SINT, EVT::i64, Custom);
+ setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
+ setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
+ setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
- setOperationAction(ISD::CTPOP , EVT::i64 , Expand);
- setOperationAction(ISD::CTTZ , EVT::i64 , Expand);
- setOperationAction(ISD::CTLZ , EVT::i64 , Expand);
- }
- setOperationAction(ISD::BSWAP , EVT::i64, Expand);
- setOperationAction(ISD::ROTL , EVT::i64, Expand);
- setOperationAction(ISD::ROTR , EVT::i64, Expand);
-
- setOperationAction(ISD::SREM , EVT::i64, Custom);
- setOperationAction(ISD::UREM , EVT::i64, Custom);
- setOperationAction(ISD::SDIV , EVT::i64, Custom);
- setOperationAction(ISD::UDIV , EVT::i64, Custom);
-
- setOperationAction(ISD::ADDC , EVT::i64, Expand);
- setOperationAction(ISD::ADDE , EVT::i64, Expand);
- setOperationAction(ISD::SUBC , EVT::i64, Expand);
- setOperationAction(ISD::SUBE , EVT::i64, Expand);
-
- setOperationAction(ISD::UMUL_LOHI, EVT::i64, Expand);
- setOperationAction(ISD::SMUL_LOHI, EVT::i64, Expand);
-
- setOperationAction(ISD::SRL_PARTS, EVT::i64, Custom);
- setOperationAction(ISD::SRA_PARTS, EVT::i64, Expand);
- setOperationAction(ISD::SHL_PARTS, EVT::i64, Expand);
+ setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
+ setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
+ setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
+ }
+ setOperationAction(ISD::BSWAP , MVT::i64, Expand);
+ setOperationAction(ISD::ROTL , MVT::i64, Expand);
+ setOperationAction(ISD::ROTR , MVT::i64, Expand);
+
+ setOperationAction(ISD::SREM , MVT::i64, Custom);
+ setOperationAction(ISD::UREM , MVT::i64, Custom);
+ setOperationAction(ISD::SDIV , MVT::i64, Custom);
+ setOperationAction(ISD::UDIV , MVT::i64, Custom);
+
+ setOperationAction(ISD::ADDC , MVT::i64, Expand);
+ setOperationAction(ISD::ADDE , MVT::i64, Expand);
+ setOperationAction(ISD::SUBC , MVT::i64, Expand);
+ setOperationAction(ISD::SUBE , MVT::i64, Expand);
+
+ setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
+ setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
+
+ setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
+ setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
+ setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
// We don't support sin/cos/sqrt/pow
- setOperationAction(ISD::FSIN , EVT::f64, Expand);
- setOperationAction(ISD::FCOS , EVT::f64, Expand);
- setOperationAction(ISD::FSIN , EVT::f32, Expand);
- setOperationAction(ISD::FCOS , EVT::f32, Expand);
+ setOperationAction(ISD::FSIN , MVT::f64, Expand);
+ setOperationAction(ISD::FCOS , MVT::f64, Expand);
+ setOperationAction(ISD::FSIN , MVT::f32, Expand);
+ setOperationAction(ISD::FCOS , MVT::f32, Expand);
- setOperationAction(ISD::FSQRT, EVT::f64, Expand);
- setOperationAction(ISD::FSQRT, EVT::f32, Expand);
+ setOperationAction(ISD::FSQRT, MVT::f64, Expand);
+ setOperationAction(ISD::FSQRT, MVT::f32, Expand);
- setOperationAction(ISD::FPOW , EVT::f32, Expand);
- setOperationAction(ISD::FPOW , EVT::f64, Expand);
+ setOperationAction(ISD::FPOW , MVT::f32, Expand);
+ setOperationAction(ISD::FPOW , MVT::f64, Expand);
- setOperationAction(ISD::SETCC, EVT::f32, Promote);
+ setOperationAction(ISD::SETCC, MVT::f32, Promote);
- setOperationAction(ISD::BIT_CONVERT, EVT::f32, Promote);
+ setOperationAction(ISD::BIT_CONVERT, MVT::f32, Promote);
// We don't have line number support yet.
- setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand);
- setOperationAction(ISD::DBG_LABEL, EVT::Other, Expand);
- setOperationAction(ISD::EH_LABEL, EVT::Other, Expand);
+ setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
+ setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
// Not implemented yet.
- setOperationAction(ISD::STACKSAVE, EVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE, EVT::Other, Expand);
- setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i64, Expand);
+ setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
// We want to legalize GlobalAddress and ConstantPool and
// ExternalSymbols nodes into the appropriate instructions to
// materialize the address.
- setOperationAction(ISD::GlobalAddress, EVT::i64, Custom);
- setOperationAction(ISD::ConstantPool, EVT::i64, Custom);
- setOperationAction(ISD::ExternalSymbol, EVT::i64, Custom);
- setOperationAction(ISD::GlobalTLSAddress, EVT::i64, Custom);
-
- setOperationAction(ISD::VASTART, EVT::Other, Custom);
- setOperationAction(ISD::VAEND, EVT::Other, Expand);
- setOperationAction(ISD::VACOPY, EVT::Other, Custom);
- setOperationAction(ISD::VAARG, EVT::Other, Custom);
- setOperationAction(ISD::VAARG, EVT::i32, Custom);
+ setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
+ setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
+ setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
+ setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
+
+ setOperationAction(ISD::VASTART, MVT::Other, Custom);
+ setOperationAction(ISD::VAEND, MVT::Other, Expand);
+ setOperationAction(ISD::VACOPY, MVT::Other, Custom);
+ setOperationAction(ISD::VAARG, MVT::Other, Custom);
+ setOperationAction(ISD::VAARG, MVT::i32, Custom);
- setOperationAction(ISD::JumpTable, EVT::i64, Custom);
- setOperationAction(ISD::JumpTable, EVT::i32, Custom);
+ setOperationAction(ISD::JumpTable, MVT::i64, Custom);
+ setOperationAction(ISD::JumpTable, MVT::i32, Custom);
setStackPointerRegisterToSaveRestore(Alpha::R30);
@@ -168,8 +168,8 @@
computeRegisterProperties();
}
-EVT::SimpleValueType AlphaTargetLowering::getSetCCResultType(EVT VT) const {
- return EVT::i64;
+MVT::SimpleValueType AlphaTargetLowering::getSetCCResultType(EVT VT) const {
+ return MVT::i64;
}
const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
@@ -203,9 +203,9 @@
// FIXME there isn't really any debug info here
DebugLoc dl = Op.getDebugLoc();
- SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, EVT::i64, JTI,
- DAG.getGLOBAL_OFFSET_TABLE(EVT::i64));
- SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, EVT::i64, JTI, Hi);
+ SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, JTI,
+ DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
+ SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, JTI, Hi);
return Lo;
}
@@ -285,7 +285,7 @@
assert(VA.isMemLoc());
if (StackPtr.getNode() == 0)
- StackPtr = DAG.getCopyFromReg(Chain, dl, Alpha::R30, EVT::i64);
+ StackPtr = DAG.getCopyFromReg(Chain, dl, Alpha::R30, MVT::i64);
SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
StackPtr,
@@ -299,7 +299,7 @@
// Transform all store nodes into one single node because all store nodes are
// independent of each other.
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token chain and
@@ -313,7 +313,7 @@
}
// Returns a chain & a flag for retval copy to use.
- SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
@@ -410,23 +410,23 @@
SDValue ArgVal;
if (ArgNo < 6) {
- switch (ObjectVT.getSimpleVT()) {
+ switch (ObjectVT.getSimpleVT().SimpleTy) {
default:
assert(false && "Invalid value type!");
- case EVT::f64:
+ case MVT::f64:
args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
&Alpha::F8RCRegClass);
ArgVal = DAG.getCopyFromReg(Chain, dl, args_float[ArgNo], ObjectVT);
break;
- case EVT::f32:
+ case MVT::f32:
args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
&Alpha::F4RCRegClass);
ArgVal = DAG.getCopyFromReg(Chain, dl, args_float[ArgNo], ObjectVT);
break;
- case EVT::i64:
+ case MVT::i64:
args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
&Alpha::GPRCRegClass);
- ArgVal = DAG.getCopyFromReg(Chain, dl, args_int[ArgNo], EVT::i64);
+ ArgVal = DAG.getCopyFromReg(Chain, dl, args_int[ArgNo], MVT::i64);
break;
}
} else { //more args
@@ -435,7 +435,7 @@
// Create the SelectionDAG nodes corresponding to a load
//from this parameter
- SDValue FIN = DAG.getFrameIndex(FI, EVT::i64);
+ SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0);
}
InVals.push_back(ArgVal);
@@ -448,22 +448,22 @@
for (int i = 0; i < 6; ++i) {
if (TargetRegisterInfo::isPhysicalRegister(args_int[i]))
args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
- SDValue argt = DAG.getCopyFromReg(Chain, dl, args_int[i], EVT::i64);
+ SDValue argt = DAG.getCopyFromReg(Chain, dl, args_int[i], MVT::i64);
int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
if (i == 0) VarArgsBase = FI;
- SDValue SDFI = DAG.getFrameIndex(FI, EVT::i64);
+ SDValue SDFI = DAG.getFrameIndex(FI, MVT::i64);
LS.push_back(DAG.getStore(Chain, dl, argt, SDFI, NULL, 0));
if (TargetRegisterInfo::isPhysicalRegister(args_float[i]))
args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
- argt = DAG.getCopyFromReg(Chain, dl, args_float[i], EVT::f64);
+ argt = DAG.getCopyFromReg(Chain, dl, args_float[i], MVT::f64);
FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
- SDFI = DAG.getFrameIndex(FI, EVT::i64);
+ SDFI = DAG.getFrameIndex(FI, MVT::i64);
LS.push_back(DAG.getStore(Chain, dl, argt, SDFI, NULL, 0));
}
//Set up a token factor with all the stack traffic
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &LS[0], LS.size());
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LS[0], LS.size());
}
return Chain;
@@ -478,7 +478,7 @@
SDValue Copy = DAG.getCopyToReg(Chain, dl, Alpha::R26,
DAG.getNode(AlphaISD::GlobalRetAddr,
DebugLoc::getUnknownLoc(),
- EVT::i64),
+ MVT::i64),
SDValue());
switch (Outs.size()) {
default:
@@ -528,7 +528,7 @@
}
}
return DAG.getNode(AlphaISD::RET_FLAG, dl,
- EVT::Other, Copy, Copy.getValue(1));
+ MVT::Other, Copy, Copy.getValue(1));
}
void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain,
@@ -538,26 +538,26 @@
const Value *VAListS = cast<SrcValueSDNode>(N->getOperand(2))->getValue();
DebugLoc dl = N->getDebugLoc();
- SDValue Base = DAG.getLoad(EVT::i64, dl, Chain, VAListP, VAListS, 0);
- SDValue Tmp = DAG.getNode(ISD::ADD, dl, EVT::i64, VAListP,
- DAG.getConstant(8, EVT::i64));
- SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, dl, EVT::i64, Base.getValue(1),
- Tmp, NULL, 0, EVT::i32);
- DataPtr = DAG.getNode(ISD::ADD, dl, EVT::i64, Base, Offset);
+ SDValue Base = DAG.getLoad(MVT::i64, dl, Chain, VAListP, VAListS, 0);
+ SDValue Tmp = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP,
+ DAG.getConstant(8, MVT::i64));
+ SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Base.getValue(1),
+ Tmp, NULL, 0, MVT::i32);
+ DataPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Base, Offset);
if (N->getValueType(0).isFloatingPoint())
{
//if fp && Offset < 6*8, then subtract 6*8 from DataPtr
- SDValue FPDataPtr = DAG.getNode(ISD::SUB, dl, EVT::i64, DataPtr,
- DAG.getConstant(8*6, EVT::i64));
- SDValue CC = DAG.getSetCC(dl, EVT::i64, Offset,
- DAG.getConstant(8*6, EVT::i64), ISD::SETLT);
- DataPtr = DAG.getNode(ISD::SELECT, dl, EVT::i64, CC, FPDataPtr, DataPtr);
+ SDValue FPDataPtr = DAG.getNode(ISD::SUB, dl, MVT::i64, DataPtr,
+ DAG.getConstant(8*6, MVT::i64));
+ SDValue CC = DAG.getSetCC(dl, MVT::i64, Offset,
+ DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
+ DataPtr = DAG.getNode(ISD::SELECT, dl, MVT::i64, CC, FPDataPtr, DataPtr);
}
- SDValue NewOffset = DAG.getNode(ISD::ADD, dl, EVT::i64, Offset,
- DAG.getConstant(8, EVT::i64));
+ SDValue NewOffset = DAG.getNode(ISD::ADD, dl, MVT::i64, Offset,
+ DAG.getConstant(8, MVT::i64));
Chain = DAG.getTruncStore(Offset.getValue(1), dl, NewOffset, Tmp, NULL, 0,
- EVT::i32);
+ MVT::i32);
}
/// LowerOperation - Provide custom lowering hooks for some operations.
@@ -573,7 +573,7 @@
switch (IntNo) {
default: break; // Don't custom lower most intrinsics.
case Intrinsic::alpha_umulh:
- return DAG.getNode(ISD::MULHU, dl, EVT::i64,
+ return DAG.getNode(ISD::MULHU, dl, MVT::i64,
Op.getOperand(1), Op.getOperand(2));
}
}
@@ -582,23 +582,23 @@
SDValue ShOpLo = Op.getOperand(0);
SDValue ShOpHi = Op.getOperand(1);
SDValue ShAmt = Op.getOperand(2);
- SDValue bm = DAG.getNode(ISD::SUB, dl, EVT::i64,
- DAG.getConstant(64, EVT::i64), ShAmt);
- SDValue BMCC = DAG.getSetCC(dl, EVT::i64, bm,
- DAG.getConstant(0, EVT::i64), ISD::SETLE);
+ SDValue bm = DAG.getNode(ISD::SUB, dl, MVT::i64,
+ DAG.getConstant(64, MVT::i64), ShAmt);
+ SDValue BMCC = DAG.getSetCC(dl, MVT::i64, bm,
+ DAG.getConstant(0, MVT::i64), ISD::SETLE);
// if 64 - shAmt <= 0
- SDValue Hi_Neg = DAG.getConstant(0, EVT::i64);
- SDValue ShAmt_Neg = DAG.getNode(ISD::SUB, dl, EVT::i64,
- DAG.getConstant(0, EVT::i64), bm);
- SDValue Lo_Neg = DAG.getNode(ISD::SRL, dl, EVT::i64, ShOpHi, ShAmt_Neg);
+ SDValue Hi_Neg = DAG.getConstant(0, MVT::i64);
+ SDValue ShAmt_Neg = DAG.getNode(ISD::SUB, dl, MVT::i64,
+ DAG.getConstant(0, MVT::i64), bm);
+ SDValue Lo_Neg = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpHi, ShAmt_Neg);
// else
- SDValue carries = DAG.getNode(ISD::SHL, dl, EVT::i64, ShOpHi, bm);
- SDValue Hi_Pos = DAG.getNode(ISD::SRL, dl, EVT::i64, ShOpHi, ShAmt);
- SDValue Lo_Pos = DAG.getNode(ISD::SRL, dl, EVT::i64, ShOpLo, ShAmt);
- Lo_Pos = DAG.getNode(ISD::OR, dl, EVT::i64, Lo_Pos, carries);
+ SDValue carries = DAG.getNode(ISD::SHL, dl, MVT::i64, ShOpHi, bm);
+ SDValue Hi_Pos = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpHi, ShAmt);
+ SDValue Lo_Pos = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpLo, ShAmt);
+ Lo_Pos = DAG.getNode(ISD::OR, dl, MVT::i64, Lo_Pos, carries);
// Merge
- SDValue Hi = DAG.getNode(ISD::SELECT, dl, EVT::i64, BMCC, Hi_Neg, Hi_Pos);
- SDValue Lo = DAG.getNode(ISD::SELECT, dl, EVT::i64, BMCC, Lo_Neg, Lo_Pos);
+ SDValue Hi = DAG.getNode(ISD::SELECT, dl, MVT::i64, BMCC, Hi_Neg, Hi_Pos);
+ SDValue Lo = DAG.getNode(ISD::SELECT, dl, MVT::i64, BMCC, Lo_Neg, Lo_Pos);
SDValue Ops[2] = { Lo, Hi };
return DAG.getMergeValues(Ops, 2, dl);
}
@@ -608,35 +608,35 @@
case ISD::SINT_TO_FP: {
- assert(Op.getOperand(0).getValueType() == EVT::i64 &&
+ assert(Op.getOperand(0).getValueType() == MVT::i64 &&
"Unhandled SINT_TO_FP type in custom expander!");
SDValue LD;
- bool isDouble = Op.getValueType() == EVT::f64;
- LD = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f64, Op.getOperand(0));
+ bool isDouble = Op.getValueType() == MVT::f64;
+ LD = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op.getOperand(0));
SDValue FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_, dl,
- isDouble?EVT::f64:EVT::f32, LD);
+ isDouble?MVT::f64:MVT::f32, LD);
return FP;
}
case ISD::FP_TO_SINT: {
- bool isDouble = Op.getOperand(0).getValueType() == EVT::f64;
+ bool isDouble = Op.getOperand(0).getValueType() == MVT::f64;
SDValue src = Op.getOperand(0);
if (!isDouble) //Promote
- src = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, src);
+ src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, src);
- src = DAG.getNode(AlphaISD::CVTTQ_, dl, EVT::f64, src);
+ src = DAG.getNode(AlphaISD::CVTTQ_, dl, MVT::f64, src);
- return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i64, src);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, src);
}
case ISD::ConstantPool: {
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
Constant *C = CP->getConstVal();
- SDValue CPI = DAG.getTargetConstantPool(C, EVT::i64, CP->getAlignment());
+ SDValue CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
// FIXME there isn't really any debug info here
- SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, EVT::i64, CPI,
- DAG.getGLOBAL_OFFSET_TABLE(EVT::i64));
- SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, EVT::i64, CPI, Hi);
+ SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, CPI,
+ DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
+ SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, CPI, Hi);
return Lo;
}
case ISD::GlobalTLSAddress:
@@ -644,24 +644,24 @@
case ISD::GlobalAddress: {
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
GlobalValue *GV = GSDN->getGlobal();
- SDValue GA = DAG.getTargetGlobalAddress(GV, EVT::i64, GSDN->getOffset());
+ SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
// FIXME there isn't really any debug info here
// if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) {
if (GV->hasLocalLinkage()) {
- SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, EVT::i64, GA,
- DAG.getGLOBAL_OFFSET_TABLE(EVT::i64));
- SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, EVT::i64, GA, Hi);
+ SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, GA,
+ DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
+ SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, GA, Hi);
return Lo;
} else
- return DAG.getNode(AlphaISD::RelLit, dl, EVT::i64, GA,
- DAG.getGLOBAL_OFFSET_TABLE(EVT::i64));
+ return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64, GA,
+ DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
}
case ISD::ExternalSymbol: {
- return DAG.getNode(AlphaISD::RelLit, dl, EVT::i64,
+ return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64,
DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
- ->getSymbol(), EVT::i64),
- DAG.getGLOBAL_OFFSET_TABLE(EVT::i64));
+ ->getSymbol(), MVT::i64),
+ DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
}
case ISD::UREM:
@@ -692,8 +692,8 @@
}
SDValue Tmp1 = Op.getOperand(0),
Tmp2 = Op.getOperand(1),
- Addr = DAG.getExternalSymbol(opstr, EVT::i64);
- return DAG.getNode(AlphaISD::DivCall, dl, EVT::i64, Addr, Tmp1, Tmp2);
+ Addr = DAG.getExternalSymbol(opstr, MVT::i64);
+ return DAG.getNode(AlphaISD::DivCall, dl, MVT::i64, Addr, Tmp1, Tmp2);
}
break;
@@ -702,9 +702,9 @@
LowerVAARG(Op.getNode(), Chain, DataPtr, DAG);
SDValue Result;
- if (Op.getValueType() == EVT::i32)
- Result = DAG.getExtLoad(ISD::SEXTLOAD, dl, EVT::i64, Chain, DataPtr,
- NULL, 0, EVT::i32);
+ if (Op.getValueType() == MVT::i32)
+ Result = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Chain, DataPtr,
+ NULL, 0, MVT::i32);
else
Result = DAG.getLoad(Op.getValueType(), dl, Chain, DataPtr, NULL, 0);
return Result;
@@ -718,13 +718,13 @@
SDValue Val = DAG.getLoad(getPointerTy(), dl, Chain, SrcP, SrcS, 0);
SDValue Result = DAG.getStore(Val.getValue(1), dl, Val, DestP, DestS, 0);
- SDValue NP = DAG.getNode(ISD::ADD, dl, EVT::i64, SrcP,
- DAG.getConstant(8, EVT::i64));
- Val = DAG.getExtLoad(ISD::SEXTLOAD, dl, EVT::i64, Result,
- NP, NULL,0, EVT::i32);
- SDValue NPD = DAG.getNode(ISD::ADD, dl, EVT::i64, DestP,
- DAG.getConstant(8, EVT::i64));
- return DAG.getTruncStore(Val.getValue(1), dl, Val, NPD, NULL, 0, EVT::i32);
+ SDValue NP = DAG.getNode(ISD::ADD, dl, MVT::i64, SrcP,
+ DAG.getConstant(8, MVT::i64));
+ Val = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Result,
+ NP, NULL,0, MVT::i32);
+ SDValue NPD = DAG.getNode(ISD::ADD, dl, MVT::i64, DestP,
+ DAG.getConstant(8, MVT::i64));
+ return DAG.getTruncStore(Val.getValue(1), dl, Val, NPD, NULL, 0, MVT::i32);
}
case ISD::VASTART: {
SDValue Chain = Op.getOperand(0);
@@ -732,16 +732,16 @@
const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
// vastart stores the address of the VarArgsBase and VarArgsOffset
- SDValue FR = DAG.getFrameIndex(VarArgsBase, EVT::i64);
+ SDValue FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
SDValue S1 = DAG.getStore(Chain, dl, FR, VAListP, VAListS, 0);
- SDValue SA2 = DAG.getNode(ISD::ADD, dl, EVT::i64, VAListP,
- DAG.getConstant(8, EVT::i64));
- return DAG.getTruncStore(S1, dl, DAG.getConstant(VarArgsOffset, EVT::i64),
- SA2, NULL, 0, EVT::i32);
+ SDValue SA2 = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP,
+ DAG.getConstant(8, MVT::i64));
+ return DAG.getTruncStore(S1, dl, DAG.getConstant(VarArgsOffset, MVT::i64),
+ SA2, NULL, 0, MVT::i32);
}
case ISD::RETURNADDR:
return DAG.getNode(AlphaISD::GlobalRetAddr, DebugLoc::getUnknownLoc(),
- EVT::i64);
+ MVT::i64);
//FIXME: implement
case ISD::FRAMEADDR: break;
}
@@ -753,7 +753,7 @@
SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) {
DebugLoc dl = N->getDebugLoc();
- assert(N->getValueType(0) == EVT::i32 &&
+ assert(N->getValueType(0) == MVT::i32 &&
N->getOpcode() == ISD::VAARG &&
"Unknown node to custom promote!");
Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h Tue Aug 11 15:47:22 2009
@@ -67,7 +67,7 @@
explicit AlphaTargetLowering(TargetMachine &TM);
/// getSetCCResultType - Get the SETCC result ValueType
- virtual EVT::SimpleValueType getSetCCResultType(EVT VT) const;
+ virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
/// LowerOperation - Provide custom lowering hooks for some operations.
///
Modified: llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp Tue Aug 11 15:47:22 2009
@@ -94,9 +94,9 @@
// Selects to ADDpp FI, 0 which in turn will become ADDimm7 SP, imm or ADDpp
// SP, Px
int FI = cast<FrameIndexSDNode>(N)->getIndex();
- SDValue TFI = CurDAG->getTargetFrameIndex(FI, EVT::i32);
- return CurDAG->SelectNodeTo(N, BF::ADDpp, EVT::i32, TFI,
- CurDAG->getTargetConstant(0, EVT::i32));
+ SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);
+ return CurDAG->SelectNodeTo(N, BF::ADDpp, MVT::i32, TFI,
+ CurDAG->getTargetConstant(0, MVT::i32));
}
}
@@ -109,8 +109,8 @@
SDValue &Offset) {
FrameIndexSDNode *FIN = 0;
if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) {
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i32);
- Offset = CurDAG->getTargetConstant(0, EVT::i32);
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
+ Offset = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
if (Addr.getOpcode() == ISD::ADD) {
@@ -119,8 +119,8 @@
(CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) &&
(CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {
// Constant positive word offset from frame index
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i32);
- Offset = CurDAG->getTargetConstant(CN->getSExtValue(), EVT::i32);
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
+ Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
return true;
}
}
@@ -179,9 +179,9 @@
SDNode *Copy =
DAG.getTargetNode(TargetInstrInfo::COPY_TO_REGCLASS,
NI->getDebugLoc(),
- EVT::i32,
+ MVT::i32,
UI.getUse().get(),
- DAG.getTargetConstant(BF::DRegClassID, EVT::i32));
+ DAG.getTargetConstant(BF::DRegClassID, MVT::i32));
UpdateNodeOperand(DAG, *UI, UI.getOperandNo(), SDValue(Copy, 0));
}
}
Modified: llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp Tue Aug 11 15:47:22 2009
@@ -40,92 +40,92 @@
BlackfinTargetLowering::BlackfinTargetLowering(TargetMachine &TM)
: TargetLowering(TM, new TargetLoweringObjectFileELF()) {
- setShiftAmountType(EVT::i16);
+ setShiftAmountType(MVT::i16);
setBooleanContents(ZeroOrOneBooleanContent);
setStackPointerRegisterToSaveRestore(BF::SP);
setIntDivIsCheap(false);
// Set up the legal register classes.
- addRegisterClass(EVT::i32, BF::DRegisterClass);
- addRegisterClass(EVT::i16, BF::D16RegisterClass);
+ addRegisterClass(MVT::i32, BF::DRegisterClass);
+ addRegisterClass(MVT::i16, BF::D16RegisterClass);
computeRegisterProperties();
// Blackfin doesn't have i1 loads or stores
- setLoadExtAction(ISD::EXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
-
- setOperationAction(ISD::GlobalAddress, EVT::i32, Custom);
- setOperationAction(ISD::JumpTable, EVT::i32, Custom);
-
- setOperationAction(ISD::SELECT_CC, EVT::Other, Expand);
- setOperationAction(ISD::BR_JT, EVT::Other, Expand);
- setOperationAction(ISD::BR_CC, EVT::Other, Expand);
+ setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
+
+ setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
+ setOperationAction(ISD::JumpTable, MVT::i32, Custom);
+
+ setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
+ setOperationAction(ISD::BR_JT, MVT::Other, Expand);
+ setOperationAction(ISD::BR_CC, MVT::Other, Expand);
// i16 registers don't do much
- setOperationAction(ISD::AND, EVT::i16, Promote);
- setOperationAction(ISD::OR, EVT::i16, Promote);
- setOperationAction(ISD::XOR, EVT::i16, Promote);
- setOperationAction(ISD::CTPOP, EVT::i16, Promote);
+ setOperationAction(ISD::AND, MVT::i16, Promote);
+ setOperationAction(ISD::OR, MVT::i16, Promote);
+ setOperationAction(ISD::XOR, MVT::i16, Promote);
+ setOperationAction(ISD::CTPOP, MVT::i16, Promote);
// The expansion of CTLZ/CTTZ uses AND/OR, so we might as well promote
// immediately.
- setOperationAction(ISD::CTLZ, EVT::i16, Promote);
- setOperationAction(ISD::CTTZ, EVT::i16, Promote);
- setOperationAction(ISD::SETCC, EVT::i16, Promote);
+ setOperationAction(ISD::CTLZ, MVT::i16, Promote);
+ setOperationAction(ISD::CTTZ, MVT::i16, Promote);
+ setOperationAction(ISD::SETCC, MVT::i16, Promote);
// Blackfin has no division
- setOperationAction(ISD::SDIV, EVT::i16, Expand);
- setOperationAction(ISD::SDIV, EVT::i32, Expand);
- setOperationAction(ISD::SDIVREM, EVT::i16, Expand);
- setOperationAction(ISD::SDIVREM, EVT::i32, Expand);
- setOperationAction(ISD::SREM, EVT::i16, Expand);
- setOperationAction(ISD::SREM, EVT::i32, Expand);
- setOperationAction(ISD::UDIV, EVT::i16, Expand);
- setOperationAction(ISD::UDIV, EVT::i32, Expand);
- setOperationAction(ISD::UDIVREM, EVT::i16, Expand);
- setOperationAction(ISD::UDIVREM, EVT::i32, Expand);
- setOperationAction(ISD::UREM, EVT::i16, Expand);
- setOperationAction(ISD::UREM, EVT::i32, Expand);
-
- setOperationAction(ISD::SMUL_LOHI, EVT::i32, Expand);
- setOperationAction(ISD::UMUL_LOHI, EVT::i32, Expand);
- setOperationAction(ISD::MULHU, EVT::i32, Expand);
- setOperationAction(ISD::MULHS, EVT::i32, Expand);
+ setOperationAction(ISD::SDIV, MVT::i16, Expand);
+ setOperationAction(ISD::SDIV, MVT::i32, Expand);
+ setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
+ setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
+ setOperationAction(ISD::SREM, MVT::i16, Expand);
+ setOperationAction(ISD::SREM, MVT::i32, Expand);
+ setOperationAction(ISD::UDIV, MVT::i16, Expand);
+ setOperationAction(ISD::UDIV, MVT::i32, Expand);
+ setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
+ setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
+ setOperationAction(ISD::UREM, MVT::i16, Expand);
+ setOperationAction(ISD::UREM, MVT::i32, Expand);
+
+ setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
+ setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
+ setOperationAction(ISD::MULHU, MVT::i32, Expand);
+ setOperationAction(ISD::MULHS, MVT::i32, Expand);
// No carry-in operations.
- setOperationAction(ISD::ADDE, EVT::i32, Custom);
- setOperationAction(ISD::SUBE, EVT::i32, Custom);
+ setOperationAction(ISD::ADDE, MVT::i32, Custom);
+ setOperationAction(ISD::SUBE, MVT::i32, Custom);
// Blackfin has no intrinsics for these particular operations.
- setOperationAction(ISD::MEMBARRIER, EVT::Other, Expand);
- setOperationAction(ISD::BSWAP, EVT::i32, Expand);
+ setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
+ setOperationAction(ISD::BSWAP, MVT::i32, Expand);
- setOperationAction(ISD::SHL_PARTS, EVT::i32, Expand);
- setOperationAction(ISD::SRA_PARTS, EVT::i32, Expand);
- setOperationAction(ISD::SRL_PARTS, EVT::i32, Expand);
+ setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
// i32 has native CTPOP, but not CTLZ/CTTZ
- setOperationAction(ISD::CTLZ, EVT::i32, Expand);
- setOperationAction(ISD::CTTZ, EVT::i32, Expand);
+ setOperationAction(ISD::CTLZ, MVT::i32, Expand);
+ setOperationAction(ISD::CTTZ, MVT::i32, Expand);
// READCYCLECOUNTER needs special type legalization.
- setOperationAction(ISD::READCYCLECOUNTER, EVT::i64, Custom);
+ setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
// We don't have line number support yet.
- setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand);
- setOperationAction(ISD::DBG_LABEL, EVT::Other, Expand);
- setOperationAction(ISD::EH_LABEL, EVT::Other, Expand);
- setOperationAction(ISD::DECLARE, EVT::Other, Expand);
+ setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
+ setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::DECLARE, MVT::Other, Expand);
// Use the default implementation.
- setOperationAction(ISD::VACOPY, EVT::Other, Expand);
- setOperationAction(ISD::VAEND, EVT::Other, Expand);
- setOperationAction(ISD::STACKSAVE, EVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE, EVT::Other, Expand);
+ setOperationAction(ISD::VACOPY, MVT::Other, Expand);
+ setOperationAction(ISD::VAEND, MVT::Other, Expand);
+ setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
}
const char *BlackfinTargetLowering::getTargetNodeName(unsigned Opcode) const {
@@ -137,10 +137,10 @@
}
}
-EVT::SimpleValueType BlackfinTargetLowering::getSetCCResultType(EVT VT) const {
+MVT::SimpleValueType BlackfinTargetLowering::getSetCCResultType(EVT VT) const {
// SETCC always sets the CC register. Technically that is an i1 register, but
// that type is not legal, so we treat it as an i32 register.
- return EVT::i32;
+ return MVT::i32;
}
SDValue BlackfinTargetLowering::LowerGlobalAddress(SDValue Op,
@@ -148,16 +148,16 @@
DebugLoc DL = Op.getDebugLoc();
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
- Op = DAG.getTargetGlobalAddress(GV, EVT::i32);
- return DAG.getNode(BFISD::Wrapper, DL, EVT::i32, Op);
+ Op = DAG.getTargetGlobalAddress(GV, MVT::i32);
+ return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
}
SDValue BlackfinTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
DebugLoc DL = Op.getDebugLoc();
int JTI = cast<JumpTableSDNode>(Op)->getIndex();
- Op = DAG.getTargetJumpTable(JTI, EVT::i32);
- return DAG.getNode(BFISD::Wrapper, DL, EVT::i32, Op);
+ Op = DAG.getTargetJumpTable(JTI, MVT::i32);
+ return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
}
SDValue
@@ -209,7 +209,7 @@
assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
unsigned ObjSize = VA.getLocVT().getStoreSizeInBits()/8;
int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset());
- SDValue FIN = DAG.getFrameIndex(FI, EVT::i32);
+ SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
}
}
@@ -268,9 +268,9 @@
}
if (Flag.getNode()) {
- return DAG.getNode(BFISD::RET_FLAG, dl, EVT::Other, Chain, Flag);
+ return DAG.getNode(BFISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
} else {
- return DAG.getNode(BFISD::RET_FLAG, dl, EVT::Other, Chain);
+ return DAG.getNode(BFISD::RET_FLAG, dl, MVT::Other, Chain);
}
}
@@ -325,10 +325,10 @@
assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
int Offset = VA.getLocMemOffset();
assert(Offset%4 == 0 && "Unaligned LocMemOffset");
- assert(VA.getLocVT()==EVT::i32 && "Illegal CCValAssign type");
- SDValue SPN = DAG.getCopyFromReg(Chain, dl, BF::SP, EVT::i32);
+ assert(VA.getLocVT()==MVT::i32 && "Illegal CCValAssign type");
+ SDValue SPN = DAG.getCopyFromReg(Chain, dl, BF::SP, MVT::i32);
SDValue OffsetN = DAG.getIntPtrConstant(Offset);
- OffsetN = DAG.getNode(ISD::ADD, dl, EVT::i32, SPN, OffsetN);
+ OffsetN = DAG.getNode(ISD::ADD, dl, MVT::i32, SPN, OffsetN);
MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, OffsetN,
PseudoSourceValue::getStack(),
Offset));
@@ -338,7 +338,7 @@
// Transform all store nodes into one single node because
// all store nodes are independent of each other.
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token
@@ -356,13 +356,13 @@
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
// Likewise ExternalSymbol -> TargetExternalSymbol.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
- Callee = DAG.getTargetGlobalAddress(G->getGlobal(), EVT::i32);
+ Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
- Callee = DAG.getTargetExternalSymbol(E->getSymbol(), EVT::i32);
+ Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
std::vector<EVT> NodeTys;
- NodeTys.push_back(EVT::Other); // Returns a chain
- NodeTys.push_back(EVT::Flag); // Returns a flag for retval copy to use.
+ NodeTys.push_back(MVT::Other); // Returns a chain
+ NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
SDValue Ops[] = { Chain, Callee, InFlag };
Chain = DAG.getNode(BFISD::CALL, dl, NodeTys, Ops,
InFlag.getNode() ? 3 : 2);
@@ -423,25 +423,25 @@
unsigned Opcode = Op.getOpcode()==ISD::ADDE ? BF::ADD : BF::SUB;
// zext incoming carry flag in AC0 to 32 bits
- SDNode* CarryIn = DAG.getTargetNode(BF::MOVE_cc_ac0, dl, EVT::i32,
+ SDNode* CarryIn = DAG.getTargetNode(BF::MOVE_cc_ac0, dl, MVT::i32,
/* flag= */ Op.getOperand(2));
- CarryIn = DAG.getTargetNode(BF::MOVECC_zext, dl, EVT::i32,
+ CarryIn = DAG.getTargetNode(BF::MOVECC_zext, dl, MVT::i32,
SDValue(CarryIn, 0));
// Add operands, produce sum and carry flag
- SDNode *Sum = DAG.getTargetNode(Opcode, dl, EVT::i32, EVT::Flag,
+ SDNode *Sum = DAG.getTargetNode(Opcode, dl, MVT::i32, MVT::Flag,
Op.getOperand(0), Op.getOperand(1));
// Store intermediate carry from Sum
- SDNode* Carry1 = DAG.getTargetNode(BF::MOVE_cc_ac0, dl, EVT::i32,
+ SDNode* Carry1 = DAG.getTargetNode(BF::MOVE_cc_ac0, dl, MVT::i32,
/* flag= */ SDValue(Sum, 1));
// Add incoming carry, again producing an output flag
- Sum = DAG.getTargetNode(Opcode, dl, EVT::i32, EVT::Flag,
+ Sum = DAG.getTargetNode(Opcode, dl, MVT::i32, MVT::Flag,
SDValue(Sum, 0), SDValue(CarryIn, 0));
// Update AC0 with the intermediate carry, producing a flag.
- SDNode *CarryOut = DAG.getTargetNode(BF::OR_ac0_cc, dl, EVT::Flag,
+ SDNode *CarryOut = DAG.getTargetNode(BF::OR_ac0_cc, dl, MVT::Flag,
SDValue(Carry1, 0));
// Compose (i32, flag) pair
@@ -480,10 +480,10 @@
// CYCLES2. Reading CYCLES will latch the value of CYCLES2, so we must read
// CYCLES2 last.
SDValue TheChain = N->getOperand(0);
- SDValue lo = DAG.getCopyFromReg(TheChain, dl, BF::CYCLES, EVT::i32);
- SDValue hi = DAG.getCopyFromReg(lo.getValue(1), dl, BF::CYCLES2, EVT::i32);
+ SDValue lo = DAG.getCopyFromReg(TheChain, dl, BF::CYCLES, MVT::i32);
+ SDValue hi = DAG.getCopyFromReg(lo.getValue(1), dl, BF::CYCLES2, MVT::i32);
// Use a buildpair to merge the two 32-bit values into a 64-bit one.
- Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i64, lo, hi));
+ Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, lo, hi));
// Outgoing chain. If we were to use the chain from lo instead, it would be
// possible to entirely eliminate the CYCLES2 read in (i32 (trunc
// readcyclecounter)). Unfortunately this could possibly delay the CYCLES2
@@ -559,7 +559,7 @@
switch (Constraint[0]) {
// Standard constraints
case 'r':
- return Pair(0U, VT == EVT::i16 ? D16RegisterClass : DPRegisterClass);
+ return Pair(0U, VT == MVT::i16 ? D16RegisterClass : DPRegisterClass);
// Blackfin-specific constraints
case 'a': return Pair(0U, PRegisterClass);
Modified: llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.h?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.h (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.h Tue Aug 11 15:47:22 2009
@@ -33,7 +33,7 @@
int VarArgsFrameOffset; // Frame offset to start of varargs area.
public:
BlackfinTargetLowering(TargetMachine &TM);
- virtual EVT::SimpleValueType getSetCCResultType(EVT VT) const;
+ virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
virtual void ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue> &Results,
Modified: llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.td?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.td Tue Aug 11 15:47:22 2009
@@ -42,21 +42,21 @@
def trailingZeros_xform : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getAPIntValue().countTrailingZeros(),
- EVT::i32);
+ MVT::i32);
}]>;
def trailingOnes_xform : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getAPIntValue().countTrailingOnes(),
- EVT::i32);
+ MVT::i32);
}]>;
def LO16 : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant((unsigned short)N->getZExtValue(), EVT::i16);
+ return CurDAG->getTargetConstant((unsigned short)N->getZExtValue(), MVT::i16);
}]>;
def HI16 : SDNodeXForm<imm, [{
// Transformation function: shift the immediate value down into the low bits.
- return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 16, EVT::i16);
+ return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 16, MVT::i16);
}]>;
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp Tue Aug 11 15:47:22 2009
@@ -96,7 +96,7 @@
for (regclass_iterator I = regclass_begin(), E = regclass_end();
I != E; ++I) {
const TargetRegisterClass* RC = *I;
- if ((VT == EVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
+ if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
(!BestRC || RC->getNumRegs() < BestRC->getNumRegs()))
BestRC = RC;
}
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Tue Aug 11 15:47:22 2009
@@ -105,9 +105,9 @@
{
EVT vt = CN->getValueType(0);
Imm = (short) CN->getZExtValue();
- if (vt.getSimpleVT() >= EVT::i1 && vt.getSimpleVT() <= EVT::i16) {
+ if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
return true;
- } else if (vt == EVT::i32) {
+ } else if (vt == MVT::i32) {
int32_t i_val = (int32_t) CN->getZExtValue();
short s_val = (short) i_val;
return i_val == s_val;
@@ -133,7 +133,7 @@
isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
{
EVT vt = FPN->getValueType(0);
- if (vt == EVT::f32) {
+ if (vt == MVT::f32) {
int val = FloatToBits(FPN->getValueAPF().convertToFloat());
int sval = (int) ((val << 16) >> 16);
Imm = (short) val;
@@ -164,19 +164,19 @@
};
const valtype_map_s valtype_map[] = {
- { EVT::i8, SPU::ORBIr8, true, SPU::LRr8 },
- { EVT::i16, SPU::ORHIr16, true, SPU::LRr16 },
- { EVT::i32, SPU::ORIr32, true, SPU::LRr32 },
- { EVT::i64, SPU::ORr64, false, SPU::LRr64 },
- { EVT::f32, SPU::ORf32, false, SPU::LRf32 },
- { EVT::f64, SPU::ORf64, false, SPU::LRf64 },
+ { MVT::i8, SPU::ORBIr8, true, SPU::LRr8 },
+ { MVT::i16, SPU::ORHIr16, true, SPU::LRr16 },
+ { MVT::i32, SPU::ORIr32, true, SPU::LRr32 },
+ { MVT::i64, SPU::ORr64, false, SPU::LRr64 },
+ { MVT::f32, SPU::ORf32, false, SPU::LRf32 },
+ { MVT::f64, SPU::ORf64, false, SPU::LRf64 },
// vector types... (sigh!)
- { EVT::v16i8, 0, false, SPU::LRv16i8 },
- { EVT::v8i16, 0, false, SPU::LRv8i16 },
- { EVT::v4i32, 0, false, SPU::LRv4i32 },
- { EVT::v2i64, 0, false, SPU::LRv2i64 },
- { EVT::v4f32, 0, false, SPU::LRv4f32 },
- { EVT::v2f64, 0, false, SPU::LRv2f64 }
+ { MVT::v16i8, 0, false, SPU::LRv16i8 },
+ { MVT::v8i16, 0, false, SPU::LRv8i16 },
+ { MVT::v4i32, 0, false, SPU::LRv4i32 },
+ { MVT::v2i64, 0, false, SPU::LRv2i64 },
+ { MVT::v4f32, 0, false, SPU::LRv4f32 },
+ { MVT::v2f64, 0, false, SPU::LRv2f64 }
};
const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
@@ -211,12 +211,12 @@
// Create the shuffle mask for "rotating" the borrow up one register slot
// once the borrow is generated.
- ShufBytes.push_back(DAG.getConstant(0x04050607, EVT::i32));
- ShufBytes.push_back(DAG.getConstant(0x80808080, EVT::i32));
- ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, EVT::i32));
- ShufBytes.push_back(DAG.getConstant(0x80808080, EVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
- return DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
&ShufBytes[0], ShufBytes.size());
}
@@ -226,12 +226,12 @@
// Create the shuffle mask for "rotating" the borrow up one register slot
// once the borrow is generated.
- ShufBytes.push_back(DAG.getConstant(0x04050607, EVT::i32));
- ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, EVT::i32));
- ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, EVT::i32));
- ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, EVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
- return DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
&ShufBytes[0], ShufBytes.size());
}
@@ -263,13 +263,13 @@
/// getI32Imm - Return a target constant with the specified value, of type
/// i32.
inline SDValue getI32Imm(uint32_t Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i32);
+ return CurDAG->getTargetConstant(Imm, MVT::i32);
}
/// getI64Imm - Return a target constant with the specified value, of type
/// i64.
inline SDValue getI64Imm(uint64_t Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i64);
+ return CurDAG->getTargetConstant(Imm, MVT::i64);
}
/// getSmallIPtrImm - Return a target constant of pointer type.
@@ -285,17 +285,17 @@
// Check to see if this vector can be represented as a CellSPU immediate
// constant by invoking all of the instruction selection predicates:
- if (((vecVT == EVT::v8i16) &&
- (SPU::get_vec_i16imm(bvNode, *CurDAG, EVT::i16).getNode() != 0)) ||
- ((vecVT == EVT::v4i32) &&
- ((SPU::get_vec_i16imm(bvNode, *CurDAG, EVT::i32).getNode() != 0) ||
- (SPU::get_ILHUvec_imm(bvNode, *CurDAG, EVT::i32).getNode() != 0) ||
- (SPU::get_vec_u18imm(bvNode, *CurDAG, EVT::i32).getNode() != 0) ||
+ if (((vecVT == MVT::v8i16) &&
+ (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0)) ||
+ ((vecVT == MVT::v4i32) &&
+ ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
+ (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
+ (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
(SPU::get_v4i32_imm(bvNode, *CurDAG).getNode() != 0))) ||
- ((vecVT == EVT::v2i64) &&
- ((SPU::get_vec_i16imm(bvNode, *CurDAG, EVT::i64).getNode() != 0) ||
- (SPU::get_ILHUvec_imm(bvNode, *CurDAG, EVT::i64).getNode() != 0) ||
- (SPU::get_vec_u18imm(bvNode, *CurDAG, EVT::i64).getNode() != 0))))
+ ((vecVT == MVT::v2i64) &&
+ ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
+ (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
+ (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0))))
return Select(build_vec);
// No, need to emit a constant pool spill:
@@ -434,7 +434,7 @@
SPUDAGToDAGISel::SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
SDValue &Index) {
// These match the addr256k operand type:
- EVT OffsVT = EVT::i16;
+ EVT OffsVT = MVT::i16;
SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
switch (N.getOpcode()) {
@@ -717,45 +717,45 @@
TFI, Imm0), 0);
n_ops = 2;
}
- } else if (Opc == ISD::Constant && OpVT == EVT::i64) {
+ } else if (Opc == ISD::Constant && OpVT == MVT::i64) {
// Catch the i64 constants that end up here. Note: The backend doesn't
// attempt to legalize the constant (it's useless because DAGCombiner
// will insert 64-bit constants and we can't stop it).
return SelectI64Constant(Op, OpVT, Op.getDebugLoc());
} else if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND)
- && OpVT == EVT::i64) {
+ && OpVT == MVT::i64) {
SDValue Op0 = Op.getOperand(0);
EVT Op0VT = Op0.getValueType();
EVT Op0VecVT = EVT::getVectorVT(Op0VT, (128 / Op0VT.getSizeInBits()));
EVT OpVecVT = EVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
SDValue shufMask;
- switch (Op0VT.getSimpleVT()) {
+ switch (Op0VT.getSimpleVT().SimpleTy) {
default:
llvm_report_error("CellSPU Select: Unhandled zero/any extend EVT");
/*NOTREACHED*/
- case EVT::i32:
- shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
- CurDAG->getConstant(0x80808080, EVT::i32),
- CurDAG->getConstant(0x00010203, EVT::i32),
- CurDAG->getConstant(0x80808080, EVT::i32),
- CurDAG->getConstant(0x08090a0b, EVT::i32));
+ case MVT::i32:
+ shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ CurDAG->getConstant(0x80808080, MVT::i32),
+ CurDAG->getConstant(0x00010203, MVT::i32),
+ CurDAG->getConstant(0x80808080, MVT::i32),
+ CurDAG->getConstant(0x08090a0b, MVT::i32));
break;
- case EVT::i16:
- shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
- CurDAG->getConstant(0x80808080, EVT::i32),
- CurDAG->getConstant(0x80800203, EVT::i32),
- CurDAG->getConstant(0x80808080, EVT::i32),
- CurDAG->getConstant(0x80800a0b, EVT::i32));
+ case MVT::i16:
+ shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ CurDAG->getConstant(0x80808080, MVT::i32),
+ CurDAG->getConstant(0x80800203, MVT::i32),
+ CurDAG->getConstant(0x80808080, MVT::i32),
+ CurDAG->getConstant(0x80800a0b, MVT::i32));
break;
- case EVT::i8:
- shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
- CurDAG->getConstant(0x80808080, EVT::i32),
- CurDAG->getConstant(0x80808003, EVT::i32),
- CurDAG->getConstant(0x80808080, EVT::i32),
- CurDAG->getConstant(0x8080800b, EVT::i32));
+ case MVT::i8:
+ shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ CurDAG->getConstant(0x80808080, MVT::i32),
+ CurDAG->getConstant(0x80808003, MVT::i32),
+ CurDAG->getConstant(0x80808080, MVT::i32),
+ CurDAG->getConstant(0x8080800b, MVT::i32));
break;
}
@@ -775,21 +775,21 @@
SelectCode(CurDAG->getNode(ISD::BIT_CONVERT, dl, OpVecVT, zextShuffle));
return SelectCode(CurDAG->getNode(SPUISD::VEC2PREFSLOT, dl, OpVT,
zextShuffle));
- } else if (Opc == ISD::ADD && (OpVT == EVT::i64 || OpVT == EVT::v2i64)) {
+ } else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
SDNode *CGLoad =
emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl));
return SelectCode(CurDAG->getNode(SPUISD::ADD64_MARKER, dl, OpVT,
Op.getOperand(0), Op.getOperand(1),
SDValue(CGLoad, 0)));
- } else if (Opc == ISD::SUB && (OpVT == EVT::i64 || OpVT == EVT::v2i64)) {
+ } else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
SDNode *CGLoad =
emitBuildVector(getBorrowGenerateShufMask(*CurDAG, dl));
return SelectCode(CurDAG->getNode(SPUISD::SUB64_MARKER, dl, OpVT,
Op.getOperand(0), Op.getOperand(1),
SDValue(CGLoad, 0)));
- } else if (Opc == ISD::MUL && (OpVT == EVT::i64 || OpVT == EVT::v2i64)) {
+ } else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
SDNode *CGLoad =
emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl));
@@ -799,8 +799,8 @@
} else if (Opc == ISD::TRUNCATE) {
SDValue Op0 = Op.getOperand(0);
if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
- && OpVT == EVT::i32
- && Op0.getValueType() == EVT::i64) {
+ && OpVT == MVT::i32
+ && Op0.getValueType() == MVT::i64) {
// Catch (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32
//
// Take advantage of the fact that the upper 32 bits are in the
@@ -817,7 +817,7 @@
shift_amt -= 32;
if (shift_amt > 0) {
// Take care of the additional shift, if present:
- SDValue shift = CurDAG->getTargetConstant(shift_amt, EVT::i32);
+ SDValue shift = CurDAG->getTargetConstant(shift_amt, MVT::i32);
unsigned Opc = SPU::ROTMAIr32_i32;
if (Op0.getOpcode() == ISD::SRL)
@@ -832,19 +832,19 @@
}
}
} else if (Opc == ISD::SHL) {
- if (OpVT == EVT::i64) {
+ if (OpVT == MVT::i64) {
return SelectSHLi64(Op, OpVT);
}
} else if (Opc == ISD::SRL) {
- if (OpVT == EVT::i64) {
+ if (OpVT == MVT::i64) {
return SelectSRLi64(Op, OpVT);
}
} else if (Opc == ISD::SRA) {
- if (OpVT == EVT::i64) {
+ if (OpVT == MVT::i64) {
return SelectSRAi64(Op, OpVT);
}
} else if (Opc == ISD::FNEG
- && (OpVT == EVT::f64 || OpVT == EVT::v2f64)) {
+ && (OpVT == MVT::f64 || OpVT == MVT::v2f64)) {
DebugLoc dl = Op.getDebugLoc();
// Check if the pattern is a special form of DFNMS:
// (fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))
@@ -853,7 +853,7 @@
SDValue Op00 = Op0.getOperand(0);
if (Op00.getOpcode() == ISD::FMUL) {
unsigned Opc = SPU::DFNMSf64;
- if (OpVT == EVT::v2f64)
+ if (OpVT == MVT::v2f64)
Opc = SPU::DFNMSv2f64;
return CurDAG->getTargetNode(Opc, dl, OpVT,
@@ -863,29 +863,29 @@
}
}
- SDValue negConst = CurDAG->getConstant(0x8000000000000000ULL, EVT::i64);
+ SDValue negConst = CurDAG->getConstant(0x8000000000000000ULL, MVT::i64);
SDNode *signMask = 0;
unsigned Opc = SPU::XORfneg64;
- if (OpVT == EVT::f64) {
- signMask = SelectI64Constant(negConst, EVT::i64, dl);
- } else if (OpVT == EVT::v2f64) {
+ if (OpVT == MVT::f64) {
+ signMask = SelectI64Constant(negConst, MVT::i64, dl);
+ } else if (OpVT == MVT::v2f64) {
Opc = SPU::XORfnegvec;
signMask = emitBuildVector(CurDAG->getNode(ISD::BUILD_VECTOR, dl,
- EVT::v2i64,
+ MVT::v2i64,
negConst, negConst));
}
return CurDAG->getTargetNode(Opc, dl, OpVT,
Op.getOperand(0), SDValue(signMask, 0));
} else if (Opc == ISD::FABS) {
- if (OpVT == EVT::f64) {
- SDNode *signMask = SelectI64Constant(0x7fffffffffffffffULL, EVT::i64, dl);
+ if (OpVT == MVT::f64) {
+ SDNode *signMask = SelectI64Constant(0x7fffffffffffffffULL, MVT::i64, dl);
return CurDAG->getTargetNode(SPU::ANDfabs64, dl, OpVT,
Op.getOperand(0), SDValue(signMask, 0));
- } else if (OpVT == EVT::v2f64) {
- SDValue absConst = CurDAG->getConstant(0x7fffffffffffffffULL, EVT::i64);
- SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, EVT::v2i64,
+ } else if (OpVT == MVT::v2f64) {
+ SDValue absConst = CurDAG->getConstant(0x7fffffffffffffffULL, MVT::i64);
+ SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
absConst, absConst);
SDNode *signMask = emitBuildVector(absVec);
return CurDAG->getTargetNode(SPU::ANDfabsvec, dl, OpVT,
@@ -911,9 +911,9 @@
if (vtm->ldresult_imm) {
SDValue Zero = CurDAG->getTargetConstant(0, VT);
- Result = CurDAG->getTargetNode(Opc, dl, VT, EVT::Other, Arg, Zero, Chain);
+ Result = CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Arg, Zero, Chain);
} else {
- Result = CurDAG->getTargetNode(Opc, dl, VT, EVT::Other, Arg, Arg, Chain);
+ Result = CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Arg, Arg, Chain);
}
return Result;
@@ -977,7 +977,7 @@
DebugLoc dl = Op.getDebugLoc();
VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, dl, VecVT, Op0);
- SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, EVT::i16);
+ SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16);
SelMask = CurDAG->getTargetNode(SPU::FSMBIv2i64, dl, VecVT, SelMaskVal);
ZeroFill = CurDAG->getTargetNode(SPU::ILv2i64, dl, VecVT,
CurDAG->getTargetConstant(0, OpVT));
@@ -1110,16 +1110,16 @@
SDValue SignRotAmt = CurDAG->getTargetConstant(31, ShiftAmtVT);
SDNode *SignRot =
- CurDAG->getTargetNode(SPU::ROTMAIv2i64_i32, dl, EVT::v2i64,
+ CurDAG->getTargetNode(SPU::ROTMAIv2i64_i32, dl, MVT::v2i64,
SDValue(VecOp0, 0), SignRotAmt);
SDNode *UpperHalfSign =
- CurDAG->getTargetNode(SPU::ORi32_v4i32, dl, EVT::i32, SDValue(SignRot, 0));
+ CurDAG->getTargetNode(SPU::ORi32_v4i32, dl, MVT::i32, SDValue(SignRot, 0));
SDNode *UpperHalfSignMask =
CurDAG->getTargetNode(SPU::FSM64r32, dl, VecVT, SDValue(UpperHalfSign, 0));
SDNode *UpperLowerMask =
CurDAG->getTargetNode(SPU::FSMBIv2i64, dl, VecVT,
- CurDAG->getTargetConstant(0xff00ULL, EVT::i16));
+ CurDAG->getTargetConstant(0xff00ULL, MVT::i16));
SDNode *UpperLowerSelect =
CurDAG->getTargetNode(SPU::SELBv2i64, dl, VecVT,
SDValue(UpperHalfSignMask, 0),
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Tue Aug 11 15:47:22 2009
@@ -47,14 +47,14 @@
};
const valtype_map_s valtype_map[] = {
- { EVT::i1, 3 },
- { EVT::i8, 3 },
- { EVT::i16, 2 },
- { EVT::i32, 0 },
- { EVT::f32, 0 },
- { EVT::i64, 0 },
- { EVT::f64, 0 },
- { EVT::i128, 0 }
+ { MVT::i1, 3 },
+ { MVT::i8, 3 },
+ { MVT::i16, 2 },
+ { MVT::i32, 0 },
+ { MVT::f32, 0 },
+ { MVT::i64, 0 },
+ { MVT::f64, 0 },
+ { MVT::i128, 0 }
};
const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
@@ -138,37 +138,37 @@
setLibcallName(RTLIB::DIV_F64, "__fast_divdf3");
// Set up the SPU's register classes:
- addRegisterClass(EVT::i8, SPU::R8CRegisterClass);
- addRegisterClass(EVT::i16, SPU::R16CRegisterClass);
- addRegisterClass(EVT::i32, SPU::R32CRegisterClass);
- addRegisterClass(EVT::i64, SPU::R64CRegisterClass);
- addRegisterClass(EVT::f32, SPU::R32FPRegisterClass);
- addRegisterClass(EVT::f64, SPU::R64FPRegisterClass);
- addRegisterClass(EVT::i128, SPU::GPRCRegisterClass);
+ addRegisterClass(MVT::i8, SPU::R8CRegisterClass);
+ addRegisterClass(MVT::i16, SPU::R16CRegisterClass);
+ addRegisterClass(MVT::i32, SPU::R32CRegisterClass);
+ addRegisterClass(MVT::i64, SPU::R64CRegisterClass);
+ addRegisterClass(MVT::f32, SPU::R32FPRegisterClass);
+ addRegisterClass(MVT::f64, SPU::R64FPRegisterClass);
+ addRegisterClass(MVT::i128, SPU::GPRCRegisterClass);
// SPU has no sign or zero extended loads for i1, i8, i16:
- setLoadExtAction(ISD::EXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote);
-
- setLoadExtAction(ISD::EXTLOAD, EVT::f32, Expand);
- setLoadExtAction(ISD::EXTLOAD, EVT::f64, Expand);
-
- setTruncStoreAction(EVT::i128, EVT::i64, Expand);
- setTruncStoreAction(EVT::i128, EVT::i32, Expand);
- setTruncStoreAction(EVT::i128, EVT::i16, Expand);
- setTruncStoreAction(EVT::i128, EVT::i8, Expand);
+ setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
+
+ setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
+ setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
+
+ setTruncStoreAction(MVT::i128, MVT::i64, Expand);
+ setTruncStoreAction(MVT::i128, MVT::i32, Expand);
+ setTruncStoreAction(MVT::i128, MVT::i16, Expand);
+ setTruncStoreAction(MVT::i128, MVT::i8, Expand);
- setTruncStoreAction(EVT::f64, EVT::f32, Expand);
+ setTruncStoreAction(MVT::f64, MVT::f32, Expand);
// SPU constant load actions are custom lowered:
- setOperationAction(ISD::ConstantFP, EVT::f32, Legal);
- setOperationAction(ISD::ConstantFP, EVT::f64, Custom);
+ setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
+ setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
// SPU's loads and stores have to be custom lowered:
- for (unsigned sctype = (unsigned) EVT::i8; sctype < (unsigned) EVT::i128;
+ for (unsigned sctype = (unsigned) MVT::i8; sctype < (unsigned) MVT::i128;
++sctype) {
- EVT::SimpleValueType VT = (EVT::SimpleValueType)sctype;
+ MVT::SimpleValueType VT = (MVT::SimpleValueType)sctype;
setOperationAction(ISD::LOAD, VT, Custom);
setOperationAction(ISD::STORE, VT, Custom);
@@ -176,222 +176,222 @@
setLoadExtAction(ISD::ZEXTLOAD, VT, Custom);
setLoadExtAction(ISD::SEXTLOAD, VT, Custom);
- for (unsigned stype = sctype - 1; stype >= (unsigned) EVT::i8; --stype) {
- EVT::SimpleValueType StoreVT = (EVT::SimpleValueType) stype;
+ for (unsigned stype = sctype - 1; stype >= (unsigned) MVT::i8; --stype) {
+ MVT::SimpleValueType StoreVT = (MVT::SimpleValueType) stype;
setTruncStoreAction(VT, StoreVT, Expand);
}
}
- for (unsigned sctype = (unsigned) EVT::f32; sctype < (unsigned) EVT::f64;
+ for (unsigned sctype = (unsigned) MVT::f32; sctype < (unsigned) MVT::f64;
++sctype) {
- EVT::SimpleValueType VT = (EVT::SimpleValueType) sctype;
+ MVT::SimpleValueType VT = (MVT::SimpleValueType) sctype;
setOperationAction(ISD::LOAD, VT, Custom);
setOperationAction(ISD::STORE, VT, Custom);
- for (unsigned stype = sctype - 1; stype >= (unsigned) EVT::f32; --stype) {
- EVT::SimpleValueType StoreVT = (EVT::SimpleValueType) stype;
+ for (unsigned stype = sctype - 1; stype >= (unsigned) MVT::f32; --stype) {
+ MVT::SimpleValueType StoreVT = (MVT::SimpleValueType) stype;
setTruncStoreAction(VT, StoreVT, Expand);
}
}
// Expand the jumptable branches
- setOperationAction(ISD::BR_JT, EVT::Other, Expand);
- setOperationAction(ISD::BR_CC, EVT::Other, Expand);
+ setOperationAction(ISD::BR_JT, MVT::Other, Expand);
+ setOperationAction(ISD::BR_CC, MVT::Other, Expand);
// Custom lower SELECT_CC for most cases, but expand by default
- setOperationAction(ISD::SELECT_CC, EVT::Other, Expand);
- setOperationAction(ISD::SELECT_CC, EVT::i8, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::i16, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::i32, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::i64, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
+ setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
// SPU has no intrinsics for these particular operations:
- setOperationAction(ISD::MEMBARRIER, EVT::Other, Expand);
+ setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
// SPU has no division/remainder instructions
- setOperationAction(ISD::SREM, EVT::i8, Expand);
- setOperationAction(ISD::UREM, EVT::i8, Expand);
- setOperationAction(ISD::SDIV, EVT::i8, Expand);
- setOperationAction(ISD::UDIV, EVT::i8, Expand);
- setOperationAction(ISD::SDIVREM, EVT::i8, Expand);
- setOperationAction(ISD::UDIVREM, EVT::i8, Expand);
- setOperationAction(ISD::SREM, EVT::i16, Expand);
- setOperationAction(ISD::UREM, EVT::i16, Expand);
- setOperationAction(ISD::SDIV, EVT::i16, Expand);
- setOperationAction(ISD::UDIV, EVT::i16, Expand);
- setOperationAction(ISD::SDIVREM, EVT::i16, Expand);
- setOperationAction(ISD::UDIVREM, EVT::i16, Expand);
- setOperationAction(ISD::SREM, EVT::i32, Expand);
- setOperationAction(ISD::UREM, EVT::i32, Expand);
- setOperationAction(ISD::SDIV, EVT::i32, Expand);
- setOperationAction(ISD::UDIV, EVT::i32, Expand);
- setOperationAction(ISD::SDIVREM, EVT::i32, Expand);
- setOperationAction(ISD::UDIVREM, EVT::i32, Expand);
- setOperationAction(ISD::SREM, EVT::i64, Expand);
- setOperationAction(ISD::UREM, EVT::i64, Expand);
- setOperationAction(ISD::SDIV, EVT::i64, Expand);
- setOperationAction(ISD::UDIV, EVT::i64, Expand);
- setOperationAction(ISD::SDIVREM, EVT::i64, Expand);
- setOperationAction(ISD::UDIVREM, EVT::i64, Expand);
- setOperationAction(ISD::SREM, EVT::i128, Expand);
- setOperationAction(ISD::UREM, EVT::i128, Expand);
- setOperationAction(ISD::SDIV, EVT::i128, Expand);
- setOperationAction(ISD::UDIV, EVT::i128, Expand);
- setOperationAction(ISD::SDIVREM, EVT::i128, Expand);
- setOperationAction(ISD::UDIVREM, EVT::i128, Expand);
+ setOperationAction(ISD::SREM, MVT::i8, Expand);
+ setOperationAction(ISD::UREM, MVT::i8, Expand);
+ setOperationAction(ISD::SDIV, MVT::i8, Expand);
+ setOperationAction(ISD::UDIV, MVT::i8, Expand);
+ setOperationAction(ISD::SDIVREM, MVT::i8, Expand);
+ setOperationAction(ISD::UDIVREM, MVT::i8, Expand);
+ setOperationAction(ISD::SREM, MVT::i16, Expand);
+ setOperationAction(ISD::UREM, MVT::i16, Expand);
+ setOperationAction(ISD::SDIV, MVT::i16, Expand);
+ setOperationAction(ISD::UDIV, MVT::i16, Expand);
+ setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
+ setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
+ setOperationAction(ISD::SREM, MVT::i32, Expand);
+ setOperationAction(ISD::UREM, MVT::i32, Expand);
+ setOperationAction(ISD::SDIV, MVT::i32, Expand);
+ setOperationAction(ISD::UDIV, MVT::i32, Expand);
+ setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
+ setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
+ setOperationAction(ISD::SREM, MVT::i64, Expand);
+ setOperationAction(ISD::UREM, MVT::i64, Expand);
+ setOperationAction(ISD::SDIV, MVT::i64, Expand);
+ setOperationAction(ISD::UDIV, MVT::i64, Expand);
+ setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
+ setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
+ setOperationAction(ISD::SREM, MVT::i128, Expand);
+ setOperationAction(ISD::UREM, MVT::i128, Expand);
+ setOperationAction(ISD::SDIV, MVT::i128, Expand);
+ setOperationAction(ISD::UDIV, MVT::i128, Expand);
+ setOperationAction(ISD::SDIVREM, MVT::i128, Expand);
+ setOperationAction(ISD::UDIVREM, MVT::i128, Expand);
// We don't support sin/cos/sqrt/fmod
- setOperationAction(ISD::FSIN , EVT::f64, Expand);
- setOperationAction(ISD::FCOS , EVT::f64, Expand);
- setOperationAction(ISD::FREM , EVT::f64, Expand);
- setOperationAction(ISD::FSIN , EVT::f32, Expand);
- setOperationAction(ISD::FCOS , EVT::f32, Expand);
- setOperationAction(ISD::FREM , EVT::f32, Expand);
+ setOperationAction(ISD::FSIN , MVT::f64, Expand);
+ setOperationAction(ISD::FCOS , MVT::f64, Expand);
+ setOperationAction(ISD::FREM , MVT::f64, Expand);
+ setOperationAction(ISD::FSIN , MVT::f32, Expand);
+ setOperationAction(ISD::FCOS , MVT::f32, Expand);
+ setOperationAction(ISD::FREM , MVT::f32, Expand);
// Expand fsqrt to the appropriate libcall (NOTE: should use h/w fsqrt
// for f32!)
- setOperationAction(ISD::FSQRT, EVT::f64, Expand);
- setOperationAction(ISD::FSQRT, EVT::f32, Expand);
+ setOperationAction(ISD::FSQRT, MVT::f64, Expand);
+ setOperationAction(ISD::FSQRT, MVT::f32, Expand);
- setOperationAction(ISD::FCOPYSIGN, EVT::f64, Expand);
- setOperationAction(ISD::FCOPYSIGN, EVT::f32, Expand);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
// SPU can do rotate right and left, so legalize it... but customize for i8
// because instructions don't exist.
// FIXME: Change from "expand" to appropriate type once ROTR is supported in
// .td files.
- setOperationAction(ISD::ROTR, EVT::i32, Expand /*Legal*/);
- setOperationAction(ISD::ROTR, EVT::i16, Expand /*Legal*/);
- setOperationAction(ISD::ROTR, EVT::i8, Expand /*Custom*/);
-
- setOperationAction(ISD::ROTL, EVT::i32, Legal);
- setOperationAction(ISD::ROTL, EVT::i16, Legal);
- setOperationAction(ISD::ROTL, EVT::i8, Custom);
+ setOperationAction(ISD::ROTR, MVT::i32, Expand /*Legal*/);
+ setOperationAction(ISD::ROTR, MVT::i16, Expand /*Legal*/);
+ setOperationAction(ISD::ROTR, MVT::i8, Expand /*Custom*/);
+
+ setOperationAction(ISD::ROTL, MVT::i32, Legal);
+ setOperationAction(ISD::ROTL, MVT::i16, Legal);
+ setOperationAction(ISD::ROTL, MVT::i8, Custom);
// SPU has no native version of shift left/right for i8
- setOperationAction(ISD::SHL, EVT::i8, Custom);
- setOperationAction(ISD::SRL, EVT::i8, Custom);
- setOperationAction(ISD::SRA, EVT::i8, Custom);
+ setOperationAction(ISD::SHL, MVT::i8, Custom);
+ setOperationAction(ISD::SRL, MVT::i8, Custom);
+ setOperationAction(ISD::SRA, MVT::i8, Custom);
// Make these operations legal and handle them during instruction selection:
- setOperationAction(ISD::SHL, EVT::i64, Legal);
- setOperationAction(ISD::SRL, EVT::i64, Legal);
- setOperationAction(ISD::SRA, EVT::i64, Legal);
+ setOperationAction(ISD::SHL, MVT::i64, Legal);
+ setOperationAction(ISD::SRL, MVT::i64, Legal);
+ setOperationAction(ISD::SRA, MVT::i64, Legal);
// Custom lower i8, i32 and i64 multiplications
- setOperationAction(ISD::MUL, EVT::i8, Custom);
- setOperationAction(ISD::MUL, EVT::i32, Legal);
- setOperationAction(ISD::MUL, EVT::i64, Legal);
+ setOperationAction(ISD::MUL, MVT::i8, Custom);
+ setOperationAction(ISD::MUL, MVT::i32, Legal);
+ setOperationAction(ISD::MUL, MVT::i64, Legal);
// Expand double-width multiplication
// FIXME: It would probably be reasonable to support some of these operations
- setOperationAction(ISD::UMUL_LOHI, EVT::i8, Expand);
- setOperationAction(ISD::SMUL_LOHI, EVT::i8, Expand);
- setOperationAction(ISD::MULHU, EVT::i8, Expand);
- setOperationAction(ISD::MULHS, EVT::i8, Expand);
- setOperationAction(ISD::UMUL_LOHI, EVT::i16, Expand);
- setOperationAction(ISD::SMUL_LOHI, EVT::i16, Expand);
- setOperationAction(ISD::MULHU, EVT::i16, Expand);
- setOperationAction(ISD::MULHS, EVT::i16, Expand);
- setOperationAction(ISD::UMUL_LOHI, EVT::i32, Expand);
- setOperationAction(ISD::SMUL_LOHI, EVT::i32, Expand);
- setOperationAction(ISD::MULHU, EVT::i32, Expand);
- setOperationAction(ISD::MULHS, EVT::i32, Expand);
- setOperationAction(ISD::UMUL_LOHI, EVT::i64, Expand);
- setOperationAction(ISD::SMUL_LOHI, EVT::i64, Expand);
- setOperationAction(ISD::MULHU, EVT::i64, Expand);
- setOperationAction(ISD::MULHS, EVT::i64, Expand);
+ setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
+ setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
+ setOperationAction(ISD::MULHU, MVT::i8, Expand);
+ setOperationAction(ISD::MULHS, MVT::i8, Expand);
+ setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
+ setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
+ setOperationAction(ISD::MULHU, MVT::i16, Expand);
+ setOperationAction(ISD::MULHS, MVT::i16, Expand);
+ setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
+ setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
+ setOperationAction(ISD::MULHU, MVT::i32, Expand);
+ setOperationAction(ISD::MULHS, MVT::i32, Expand);
+ setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
+ setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
+ setOperationAction(ISD::MULHU, MVT::i64, Expand);
+ setOperationAction(ISD::MULHS, MVT::i64, Expand);
// Need to custom handle (some) common i8, i64 math ops
- setOperationAction(ISD::ADD, EVT::i8, Custom);
- setOperationAction(ISD::ADD, EVT::i64, Legal);
- setOperationAction(ISD::SUB, EVT::i8, Custom);
- setOperationAction(ISD::SUB, EVT::i64, Legal);
+ setOperationAction(ISD::ADD, MVT::i8, Custom);
+ setOperationAction(ISD::ADD, MVT::i64, Legal);
+ setOperationAction(ISD::SUB, MVT::i8, Custom);
+ setOperationAction(ISD::SUB, MVT::i64, Legal);
// SPU does not have BSWAP. It does have i32 support CTLZ.
// CTPOP has to be custom lowered.
- setOperationAction(ISD::BSWAP, EVT::i32, Expand);
- setOperationAction(ISD::BSWAP, EVT::i64, Expand);
+ setOperationAction(ISD::BSWAP, MVT::i32, Expand);
+ setOperationAction(ISD::BSWAP, MVT::i64, Expand);
- setOperationAction(ISD::CTPOP, EVT::i8, Custom);
- setOperationAction(ISD::CTPOP, EVT::i16, Custom);
- setOperationAction(ISD::CTPOP, EVT::i32, Custom);
- setOperationAction(ISD::CTPOP, EVT::i64, Custom);
- setOperationAction(ISD::CTPOP, EVT::i128, Expand);
-
- setOperationAction(ISD::CTTZ , EVT::i8, Expand);
- setOperationAction(ISD::CTTZ , EVT::i16, Expand);
- setOperationAction(ISD::CTTZ , EVT::i32, Expand);
- setOperationAction(ISD::CTTZ , EVT::i64, Expand);
- setOperationAction(ISD::CTTZ , EVT::i128, Expand);
-
- setOperationAction(ISD::CTLZ , EVT::i8, Promote);
- setOperationAction(ISD::CTLZ , EVT::i16, Promote);
- setOperationAction(ISD::CTLZ , EVT::i32, Legal);
- setOperationAction(ISD::CTLZ , EVT::i64, Expand);
- setOperationAction(ISD::CTLZ , EVT::i128, Expand);
+ setOperationAction(ISD::CTPOP, MVT::i8, Custom);
+ setOperationAction(ISD::CTPOP, MVT::i16, Custom);
+ setOperationAction(ISD::CTPOP, MVT::i32, Custom);
+ setOperationAction(ISD::CTPOP, MVT::i64, Custom);
+ setOperationAction(ISD::CTPOP, MVT::i128, Expand);
+
+ setOperationAction(ISD::CTTZ , MVT::i8, Expand);
+ setOperationAction(ISD::CTTZ , MVT::i16, Expand);
+ setOperationAction(ISD::CTTZ , MVT::i32, Expand);
+ setOperationAction(ISD::CTTZ , MVT::i64, Expand);
+ setOperationAction(ISD::CTTZ , MVT::i128, Expand);
+
+ setOperationAction(ISD::CTLZ , MVT::i8, Promote);
+ setOperationAction(ISD::CTLZ , MVT::i16, Promote);
+ setOperationAction(ISD::CTLZ , MVT::i32, Legal);
+ setOperationAction(ISD::CTLZ , MVT::i64, Expand);
+ setOperationAction(ISD::CTLZ , MVT::i128, Expand);
// SPU has a version of select that implements (a&~c)|(b&c), just like
// select ought to work:
- setOperationAction(ISD::SELECT, EVT::i8, Legal);
- setOperationAction(ISD::SELECT, EVT::i16, Legal);
- setOperationAction(ISD::SELECT, EVT::i32, Legal);
- setOperationAction(ISD::SELECT, EVT::i64, Legal);
-
- setOperationAction(ISD::SETCC, EVT::i8, Legal);
- setOperationAction(ISD::SETCC, EVT::i16, Legal);
- setOperationAction(ISD::SETCC, EVT::i32, Legal);
- setOperationAction(ISD::SETCC, EVT::i64, Legal);
- setOperationAction(ISD::SETCC, EVT::f64, Custom);
+ setOperationAction(ISD::SELECT, MVT::i8, Legal);
+ setOperationAction(ISD::SELECT, MVT::i16, Legal);
+ setOperationAction(ISD::SELECT, MVT::i32, Legal);
+ setOperationAction(ISD::SELECT, MVT::i64, Legal);
+
+ setOperationAction(ISD::SETCC, MVT::i8, Legal);
+ setOperationAction(ISD::SETCC, MVT::i16, Legal);
+ setOperationAction(ISD::SETCC, MVT::i32, Legal);
+ setOperationAction(ISD::SETCC, MVT::i64, Legal);
+ setOperationAction(ISD::SETCC, MVT::f64, Custom);
// Custom lower i128 -> i64 truncates
- setOperationAction(ISD::TRUNCATE, EVT::i64, Custom);
+ setOperationAction(ISD::TRUNCATE, MVT::i64, Custom);
- setOperationAction(ISD::FP_TO_SINT, EVT::i8, Promote);
- setOperationAction(ISD::FP_TO_UINT, EVT::i8, Promote);
- setOperationAction(ISD::FP_TO_SINT, EVT::i16, Promote);
- setOperationAction(ISD::FP_TO_UINT, EVT::i16, Promote);
+ setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
+ setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
// SPU has a legal FP -> signed INT instruction for f32, but for f64, need
// to expand to a libcall, hence the custom lowering:
- setOperationAction(ISD::FP_TO_SINT, EVT::i32, Custom);
- setOperationAction(ISD::FP_TO_UINT, EVT::i32, Custom);
- setOperationAction(ISD::FP_TO_SINT, EVT::i64, Expand);
- setOperationAction(ISD::FP_TO_UINT, EVT::i64, Expand);
- setOperationAction(ISD::FP_TO_SINT, EVT::i128, Expand);
- setOperationAction(ISD::FP_TO_UINT, EVT::i128, Expand);
+ setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
+ setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
+ setOperationAction(ISD::FP_TO_SINT, MVT::i128, Expand);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i128, Expand);
// FDIV on SPU requires custom lowering
- setOperationAction(ISD::FDIV, EVT::f64, Expand); // to libcall
+ setOperationAction(ISD::FDIV, MVT::f64, Expand); // to libcall
// SPU has [U|S]INT_TO_FP for f32->i32, but not for f64->i32, f64->i64:
- setOperationAction(ISD::SINT_TO_FP, EVT::i32, Custom);
- setOperationAction(ISD::SINT_TO_FP, EVT::i16, Promote);
- setOperationAction(ISD::SINT_TO_FP, EVT::i8, Promote);
- setOperationAction(ISD::UINT_TO_FP, EVT::i32, Custom);
- setOperationAction(ISD::UINT_TO_FP, EVT::i16, Promote);
- setOperationAction(ISD::UINT_TO_FP, EVT::i8, Promote);
- setOperationAction(ISD::SINT_TO_FP, EVT::i64, Custom);
- setOperationAction(ISD::UINT_TO_FP, EVT::i64, Custom);
-
- setOperationAction(ISD::BIT_CONVERT, EVT::i32, Legal);
- setOperationAction(ISD::BIT_CONVERT, EVT::f32, Legal);
- setOperationAction(ISD::BIT_CONVERT, EVT::i64, Legal);
- setOperationAction(ISD::BIT_CONVERT, EVT::f64, Legal);
+ setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
+ setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
+ setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
+ setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
+ setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
+ setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
+ setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
+ setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
+
+ setOperationAction(ISD::BIT_CONVERT, MVT::i32, Legal);
+ setOperationAction(ISD::BIT_CONVERT, MVT::f32, Legal);
+ setOperationAction(ISD::BIT_CONVERT, MVT::i64, Legal);
+ setOperationAction(ISD::BIT_CONVERT, MVT::f64, Legal);
// We cannot sextinreg(i1). Expand to shifts.
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
// Support label based line numbers.
- setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand);
+ setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
// We want to legalize GlobalAddress and ConstantPool nodes into the
// appropriate instructions to materialize the address.
- for (unsigned sctype = (unsigned) EVT::i8; sctype < (unsigned) EVT::f128;
+ for (unsigned sctype = (unsigned) MVT::i8; sctype < (unsigned) MVT::f128;
++sctype) {
- EVT::SimpleValueType VT = (EVT::SimpleValueType)sctype;
+ MVT::SimpleValueType VT = (MVT::SimpleValueType)sctype;
setOperationAction(ISD::GlobalAddress, VT, Custom);
setOperationAction(ISD::ConstantPool, VT, Custom);
@@ -399,42 +399,42 @@
}
// VASTART needs to be custom lowered to use the VarArgsFrameIndex
- setOperationAction(ISD::VASTART , EVT::Other, Custom);
+ setOperationAction(ISD::VASTART , MVT::Other, Custom);
// Use the default implementation.
- setOperationAction(ISD::VAARG , EVT::Other, Expand);
- setOperationAction(ISD::VACOPY , EVT::Other, Expand);
- setOperationAction(ISD::VAEND , EVT::Other, Expand);
- setOperationAction(ISD::STACKSAVE , EVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE , EVT::Other, Expand);
- setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32 , Expand);
- setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i64 , Expand);
+ setOperationAction(ISD::VAARG , MVT::Other, Expand);
+ setOperationAction(ISD::VACOPY , MVT::Other, Expand);
+ setOperationAction(ISD::VAEND , MVT::Other, Expand);
+ setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Expand);
// Cell SPU has instructions for converting between i64 and fp.
- setOperationAction(ISD::FP_TO_SINT, EVT::i64, Custom);
- setOperationAction(ISD::SINT_TO_FP, EVT::i64, Custom);
+ setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
+ setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
// To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
- setOperationAction(ISD::FP_TO_UINT, EVT::i32, Promote);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
// BUILD_PAIR can't be handled natively, and should be expanded to shl/or
- setOperationAction(ISD::BUILD_PAIR, EVT::i64, Expand);
+ setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
// First set operation action for all vector types to expand. Then we
// will selectively turn on ones that can be effectively codegen'd.
- addRegisterClass(EVT::v16i8, SPU::VECREGRegisterClass);
- addRegisterClass(EVT::v8i16, SPU::VECREGRegisterClass);
- addRegisterClass(EVT::v4i32, SPU::VECREGRegisterClass);
- addRegisterClass(EVT::v2i64, SPU::VECREGRegisterClass);
- addRegisterClass(EVT::v4f32, SPU::VECREGRegisterClass);
- addRegisterClass(EVT::v2f64, SPU::VECREGRegisterClass);
+ addRegisterClass(MVT::v16i8, SPU::VECREGRegisterClass);
+ addRegisterClass(MVT::v8i16, SPU::VECREGRegisterClass);
+ addRegisterClass(MVT::v4i32, SPU::VECREGRegisterClass);
+ addRegisterClass(MVT::v2i64, SPU::VECREGRegisterClass);
+ addRegisterClass(MVT::v4f32, SPU::VECREGRegisterClass);
+ addRegisterClass(MVT::v2f64, SPU::VECREGRegisterClass);
// "Odd size" vector classes that we're willing to support:
- addRegisterClass(EVT::v2i32, SPU::VECREGRegisterClass);
+ addRegisterClass(MVT::v2i32, SPU::VECREGRegisterClass);
- for (unsigned i = (unsigned)EVT::FIRST_VECTOR_VALUETYPE;
- i <= (unsigned)EVT::LAST_VECTOR_VALUETYPE; ++i) {
- EVT::SimpleValueType VT = (EVT::SimpleValueType)i;
+ for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
+ i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
+ MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
// add/sub are legal for all supported vector VT's.
setOperationAction(ISD::ADD, VT, Legal);
@@ -465,14 +465,14 @@
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
}
- setOperationAction(ISD::AND, EVT::v16i8, Custom);
- setOperationAction(ISD::OR, EVT::v16i8, Custom);
- setOperationAction(ISD::XOR, EVT::v16i8, Custom);
- setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v4f32, Custom);
+ setOperationAction(ISD::AND, MVT::v16i8, Custom);
+ setOperationAction(ISD::OR, MVT::v16i8, Custom);
+ setOperationAction(ISD::XOR, MVT::v16i8, Custom);
+ setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
- setOperationAction(ISD::FDIV, EVT::v4f32, Legal);
+ setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
- setShiftAmountType(EVT::i32);
+ setShiftAmountType(MVT::i32);
setBooleanContents(ZeroOrNegativeOneBooleanContent);
setStackPointerRegisterToSaveRestore(SPU::R1);
@@ -539,11 +539,11 @@
// Return the Cell SPU's SETCC result type
//===----------------------------------------------------------------------===//
-EVT::SimpleValueType SPUTargetLowering::getSetCCResultType(EVT VT) const {
+MVT::SimpleValueType SPUTargetLowering::getSetCCResultType(EVT VT) const {
// i16 and i32 are valid SETCC result types
- return ((VT == EVT::i8 || VT == EVT::i16 || VT == EVT::i32) ?
- VT.getSimpleVT() :
- EVT::i32);
+ return ((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) ?
+ VT.getSimpleVT().SimpleTy :
+ MVT::i32);
}
//===----------------------------------------------------------------------===//
@@ -562,7 +562,7 @@
within a 16-byte block, we have to rotate to extract the requested element.
For extending loads, we also want to ensure that the following sequence is
- emitted, e.g. for EVT::f32 extending load to EVT::f64:
+ emitted, e.g. for MVT::f32 extending load to MVT::f64:
\verbatim
%1 v16i8,ch = load
@@ -604,7 +604,7 @@
if (rotamt < 0)
rotamt += 16;
- rotate = DAG.getConstant(rotamt, EVT::i16);
+ rotate = DAG.getConstant(rotamt, MVT::i16);
// Simplify the base pointer for this case:
basePtr = basePtr.getOperand(0);
@@ -622,7 +622,7 @@
int64_t rotamt = -vtm->prefslot_byte;
if (rotamt < 0)
rotamt += 16;
- rotate = DAG.getConstant(rotamt, EVT::i16);
+ rotate = DAG.getConstant(rotamt, MVT::i16);
} else {
// Offset the rotate amount by the basePtr and the preferred slot
// byte offset
@@ -670,7 +670,7 @@
}
// Re-emit as a v16i8 vector load
- result = DAG.getLoad(EVT::v16i8, dl, the_chain, basePtr,
+ result = DAG.getLoad(MVT::v16i8, dl, the_chain, basePtr,
LN->getSrcValue(), LN->getSrcValueOffset(),
LN->isVolatile(), 16);
@@ -678,7 +678,7 @@
the_chain = result.getValue(1);
// Rotate into the preferred slot:
- result = DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, EVT::v16i8,
+ result = DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, MVT::v16i8,
result.getValue(0), rotate);
// Convert the loaded v16i8 vector to the appropriate vector type
@@ -701,7 +701,7 @@
result = DAG.getNode(NewOpc, dl, OutVT, result);
}
- SDVTList retvts = DAG.getVTList(OutVT, EVT::Other);
+ SDVTList retvts = DAG.getVTList(OutVT, MVT::Other);
SDValue retops[2] = {
result,
the_chain
@@ -820,7 +820,7 @@
}
// Re-emit as a v16i8 vector load
- alignLoadVec = DAG.getLoad(EVT::v16i8, dl, the_chain, basePtr,
+ alignLoadVec = DAG.getLoad(MVT::v16i8, dl, the_chain, basePtr,
SN->getSrcValue(), SN->getSrcValueOffset(),
SN->isVolatile(), 16);
@@ -859,7 +859,7 @@
result = DAG.getNode(SPUISD::SHUFB, dl, vecVT,
vectorizeOp, alignLoadVec,
DAG.getNode(ISD::BIT_CONVERT, dl,
- EVT::v4i32, insertEltOp));
+ MVT::v4i32, insertEltOp));
result = DAG.getStore(the_chain, dl, result, basePtr,
LN->getSrcValue(), LN->getSrcValueOffset(),
@@ -993,17 +993,17 @@
// FIXME there is no actual debug info here
DebugLoc dl = Op.getDebugLoc();
- if (VT == EVT::f64) {
+ if (VT == MVT::f64) {
ConstantFPSDNode *FP = cast<ConstantFPSDNode>(Op.getNode());
assert((FP != 0) &&
"LowerConstantFP: Node is not ConstantFPSDNode");
uint64_t dbits = DoubleToBits(FP->getValueAPF().convertToDouble());
- SDValue T = DAG.getConstant(dbits, EVT::i64);
- SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v2i64, T, T);
+ SDValue T = DAG.getConstant(dbits, MVT::i64);
+ SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T);
return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT,
- DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2f64, Tvec));
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Tvec));
}
return SDValue();
@@ -1039,7 +1039,7 @@
if (ArgRegIdx < NumArgRegs) {
const TargetRegisterClass *ArgRegClass;
- switch (ObjectVT.getSimpleVT()) {
+ switch (ObjectVT.getSimpleVT().SimpleTy) {
default: {
std::string msg;
raw_string_ostream Msg(msg);
@@ -1047,33 +1047,33 @@
<< ObjectVT.getEVTString();
llvm_report_error(Msg.str());
}
- case EVT::i8:
+ case MVT::i8:
ArgRegClass = &SPU::R8CRegClass;
break;
- case EVT::i16:
+ case MVT::i16:
ArgRegClass = &SPU::R16CRegClass;
break;
- case EVT::i32:
+ case MVT::i32:
ArgRegClass = &SPU::R32CRegClass;
break;
- case EVT::i64:
+ case MVT::i64:
ArgRegClass = &SPU::R64CRegClass;
break;
- case EVT::i128:
+ case MVT::i128:
ArgRegClass = &SPU::GPRCRegClass;
break;
- case EVT::f32:
+ case MVT::f32:
ArgRegClass = &SPU::R32FPRegClass;
break;
- case EVT::f64:
+ case MVT::f64:
ArgRegClass = &SPU::R64FPRegClass;
break;
- case EVT::v2f64:
- case EVT::v4f32:
- case EVT::v2i64:
- case EVT::v4i32:
- case EVT::v8i16:
- case EVT::v16i8:
+ case MVT::v2f64:
+ case MVT::v4f32:
+ case MVT::v2i64:
+ case MVT::v4i32:
+ case MVT::v8i16:
+ case MVT::v16i8:
ArgRegClass = &SPU::VECREGRegClass;
break;
}
@@ -1108,7 +1108,7 @@
for (; ArgRegIdx != NumArgRegs; ++ArgRegIdx) {
VarArgsFrameIndex = MFI->CreateFixedObject(StackSlotSize, ArgOffset);
SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
- SDValue ArgVal = DAG.getRegister(ArgRegs[ArgRegIdx], EVT::v16i8);
+ SDValue ArgVal = DAG.getRegister(ArgRegs[ArgRegIdx], MVT::v16i8);
SDValue Store = DAG.getStore(Chain, dl, ArgVal, FIN, NULL, 0);
Chain = Store.getOperand(0);
MemOps.push_back(Store);
@@ -1117,7 +1117,7 @@
ArgOffset += StackSlotSize;
}
if (!MemOps.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOps[0], MemOps.size());
}
@@ -1135,7 +1135,7 @@
(Addr << 14 >> 14) != Addr)
return 0; // Top 14 bits have to be sext of immediate.
- return DAG.getConstant((int)C->getZExtValue() >> 2, EVT::i32).getNode();
+ return DAG.getConstant((int)C->getZExtValue() >> 2, MVT::i32).getNode();
}
SDValue
@@ -1164,7 +1164,7 @@
// Set up a copy of the stack pointer for use loading and storing any
// arguments that may not fit in the registers available for argument
// passing.
- SDValue StackPtr = DAG.getRegister(SPU::R1, EVT::i32);
+ SDValue StackPtr = DAG.getRegister(SPU::R1, MVT::i32);
// Figure out which arguments are going to go in registers, and which in
// memory.
@@ -1184,13 +1184,13 @@
SDValue PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
- switch (Arg.getValueType().getSimpleVT()) {
+ switch (Arg.getValueType().getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unexpected ValueType for argument!");
- case EVT::i8:
- case EVT::i16:
- case EVT::i32:
- case EVT::i64:
- case EVT::i128:
+ case MVT::i8:
+ case MVT::i16:
+ case MVT::i32:
+ case MVT::i64:
+ case MVT::i128:
if (ArgRegIdx != NumArgRegs) {
RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg));
} else {
@@ -1198,8 +1198,8 @@
ArgOffset += StackSlotSize;
}
break;
- case EVT::f32:
- case EVT::f64:
+ case MVT::f32:
+ case MVT::f64:
if (ArgRegIdx != NumArgRegs) {
RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg));
} else {
@@ -1207,12 +1207,12 @@
ArgOffset += StackSlotSize;
}
break;
- case EVT::v2i64:
- case EVT::v2f64:
- case EVT::v4f32:
- case EVT::v4i32:
- case EVT::v8i16:
- case EVT::v16i8:
+ case MVT::v2i64:
+ case MVT::v2f64:
+ case MVT::v4f32:
+ case MVT::v4i32:
+ case MVT::v8i16:
+ case MVT::v16i8:
if (ArgRegIdx != NumArgRegs) {
RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg));
} else {
@@ -1230,7 +1230,7 @@
if (!MemOpChains.empty()) {
// Adjust the stack pointer for the stack arguments.
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
}
@@ -1303,7 +1303,7 @@
if (InFlag.getNode())
Ops.push_back(InFlag);
// Returns a chain and a flag for retval copy to use.
- Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(EVT::Other, EVT::Flag),
+ Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
&Ops[0], Ops.size());
InFlag = Chain.getValue(1);
@@ -1317,45 +1317,45 @@
return Chain;
// If the call has results, copy the values out of the ret val registers.
- switch (Ins[0].VT.getSimpleVT()) {
+ switch (Ins[0].VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unexpected ret value!");
- case EVT::Other: break;
- case EVT::i32:
- if (Ins.size() > 1 && Ins[1].VT == EVT::i32) {
+ case MVT::Other: break;
+ case MVT::i32:
+ if (Ins.size() > 1 && Ins[1].VT == MVT::i32) {
Chain = DAG.getCopyFromReg(Chain, dl, SPU::R4,
- EVT::i32, InFlag).getValue(1);
+ MVT::i32, InFlag).getValue(1);
InVals.push_back(Chain.getValue(0));
- Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, EVT::i32,
+ Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i32,
Chain.getValue(2)).getValue(1);
InVals.push_back(Chain.getValue(0));
} else {
- Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, EVT::i32,
+ Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i32,
InFlag).getValue(1);
InVals.push_back(Chain.getValue(0));
}
break;
- case EVT::i64:
- Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, EVT::i64,
+ case MVT::i64:
+ Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i64,
InFlag).getValue(1);
InVals.push_back(Chain.getValue(0));
break;
- case EVT::i128:
- Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, EVT::i128,
+ case MVT::i128:
+ Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i128,
InFlag).getValue(1);
InVals.push_back(Chain.getValue(0));
break;
- case EVT::f32:
- case EVT::f64:
+ case MVT::f32:
+ case MVT::f64:
Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, Ins[0].VT,
InFlag).getValue(1);
InVals.push_back(Chain.getValue(0));
break;
- case EVT::v2f64:
- case EVT::v2i64:
- case EVT::v4f32:
- case EVT::v4i32:
- case EVT::v8i16:
- case EVT::v16i8:
+ case MVT::v2f64:
+ case MVT::v2i64:
+ case MVT::v4f32:
+ case MVT::v4i32:
+ case MVT::v8i16:
+ case MVT::v16i8:
Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, Ins[0].VT,
InFlag).getValue(1);
InVals.push_back(Chain.getValue(0));
@@ -1395,9 +1395,9 @@
}
if (Flag.getNode())
- return DAG.getNode(SPUISD::RET_FLAG, dl, EVT::Other, Chain, Flag);
+ return DAG.getNode(SPUISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
else
- return DAG.getNode(SPUISD::RET_FLAG, dl, EVT::Other, Chain);
+ return DAG.getNode(SPUISD::RET_FLAG, dl, MVT::Other, Chain);
}
@@ -1434,7 +1434,7 @@
EVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
uint64_t Value = CN->getZExtValue();
- if (ValueType == EVT::i64) {
+ if (ValueType == MVT::i64) {
uint64_t UValue = CN->getZExtValue();
uint32_t upper = uint32_t(UValue >> 32);
uint32_t lower = uint32_t(UValue);
@@ -1456,7 +1456,7 @@
EVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
int64_t Value = CN->getSExtValue();
- if (ValueType == EVT::i64) {
+ if (ValueType == MVT::i64) {
uint64_t UValue = CN->getZExtValue();
uint32_t upper = uint32_t(UValue >> 32);
uint32_t lower = uint32_t(UValue);
@@ -1479,7 +1479,7 @@
EVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
int64_t Value = CN->getSExtValue();
- if (ValueType == EVT::i64) {
+ if (ValueType == MVT::i64) {
uint64_t UValue = CN->getZExtValue();
uint32_t upper = uint32_t(UValue >> 32);
uint32_t lower = uint32_t(UValue);
@@ -1505,11 +1505,11 @@
EVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
int Value = (int) CN->getZExtValue();
- if (ValueType == EVT::i16
+ if (ValueType == MVT::i16
&& Value <= 0xffff /* truncated from uint64_t */
&& ((short) Value >> 8) == ((short) Value & 0xff))
return DAG.getTargetConstant(Value & 0xff, ValueType);
- else if (ValueType == EVT::i8
+ else if (ValueType == MVT::i8
&& (Value & 0xff) == Value)
return DAG.getTargetConstant(Value, ValueType);
}
@@ -1524,9 +1524,9 @@
EVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
uint64_t Value = CN->getZExtValue();
- if ((ValueType == EVT::i32
+ if ((ValueType == MVT::i32
&& ((unsigned) Value & 0xffff0000) == (unsigned) Value)
- || (ValueType == EVT::i64 && (Value & 0xffff0000) == Value))
+ || (ValueType == MVT::i64 && (Value & 0xffff0000) == Value))
return DAG.getTargetConstant(Value >> 16, ValueType);
}
@@ -1536,7 +1536,7 @@
/// get_v4i32_imm - Catch-all for general 32-bit constant vectors
SDValue SPU::get_v4i32_imm(SDNode *N, SelectionDAG &DAG) {
if (ConstantSDNode *CN = getVecImm(N)) {
- return DAG.getTargetConstant((unsigned) CN->getZExtValue(), EVT::i32);
+ return DAG.getTargetConstant((unsigned) CN->getZExtValue(), MVT::i32);
}
return SDValue();
@@ -1545,7 +1545,7 @@
/// get_v4i32_imm - Catch-all for general 64-bit constant vectors
SDValue SPU::get_v2i64_imm(SDNode *N, SelectionDAG &DAG) {
if (ConstantSDNode *CN = getVecImm(N)) {
- return DAG.getTargetConstant((unsigned) CN->getZExtValue(), EVT::i64);
+ return DAG.getTargetConstant((unsigned) CN->getZExtValue(), MVT::i64);
}
return SDValue();
@@ -1575,7 +1575,7 @@
uint64_t SplatBits = APSplatBits.getZExtValue();
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: {
std::string msg;
raw_string_ostream Msg(msg);
@@ -1584,36 +1584,36 @@
llvm_report_error(Msg.str());
/*NOTREACHED*/
}
- case EVT::v4f32: {
+ case MVT::v4f32: {
uint32_t Value32 = uint32_t(SplatBits);
assert(SplatBitSize == 32
&& "LowerBUILD_VECTOR: Unexpected floating point vector element.");
// NOTE: pretend the constant is an integer. LLVM won't load FP constants
- SDValue T = DAG.getConstant(Value32, EVT::i32);
- return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v4f32,
- DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, T,T,T,T));
+ SDValue T = DAG.getConstant(Value32, MVT::i32);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, T,T,T,T));
break;
}
- case EVT::v2f64: {
+ case MVT::v2f64: {
uint64_t f64val = uint64_t(SplatBits);
assert(SplatBitSize == 64
&& "LowerBUILD_VECTOR: 64-bit float vector size > 8 bytes.");
// NOTE: pretend the constant is an integer. LLVM won't load FP constants
- SDValue T = DAG.getConstant(f64val, EVT::i64);
- return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2f64,
- DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v2i64, T, T));
+ SDValue T = DAG.getConstant(f64val, MVT::i64);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T));
break;
}
- case EVT::v16i8: {
+ case MVT::v16i8: {
// 8-bit constants have to be expanded to 16-bits
unsigned short Value16 = SplatBits /* | (SplatBits << 8) */;
SmallVector<SDValue, 8> Ops;
- Ops.assign(8, DAG.getConstant(Value16, EVT::i16));
+ Ops.assign(8, DAG.getConstant(Value16, MVT::i16));
return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
- DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v8i16, &Ops[0], Ops.size()));
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i16, &Ops[0], Ops.size()));
}
- case EVT::v8i16: {
+ case MVT::v8i16: {
unsigned short Value16 = SplatBits;
SDValue T = DAG.getConstant(Value16, EltVT);
SmallVector<SDValue, 8> Ops;
@@ -1621,15 +1621,15 @@
Ops.assign(8, T);
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
}
- case EVT::v4i32: {
+ case MVT::v4i32: {
SDValue T = DAG.getConstant(unsigned(SplatBits), VT.getVectorElementType());
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, T, T, T, T);
}
- case EVT::v2i32: {
+ case MVT::v2i32: {
SDValue T = DAG.getConstant(unsigned(SplatBits), VT.getVectorElementType());
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, T, T);
}
- case EVT::v2i64: {
+ case MVT::v2i64: {
return SPU::LowerV2I64Splat(VT, DAG, SplatBits, dl);
}
}
@@ -1647,9 +1647,9 @@
if (upper == lower) {
// Magic constant that can be matched by IL, ILA, et. al.
- SDValue Val = DAG.getTargetConstant(upper, EVT::i32);
+ SDValue Val = DAG.getTargetConstant(upper, MVT::i32);
return DAG.getNode(ISD::BIT_CONVERT, dl, OpVT,
- DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
Val, Val, Val, Val));
} else {
bool upper_special, lower_special;
@@ -1664,8 +1664,8 @@
// Both upper and lower are special, lower to a constant pool load:
if (lower_special && upper_special) {
- SDValue SplatValCN = DAG.getConstant(SplatVal, EVT::i64);
- return DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v2i64,
+ SDValue SplatValCN = DAG.getConstant(SplatVal, MVT::i64);
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
SplatValCN, SplatValCN);
}
@@ -1676,17 +1676,17 @@
// Create lower vector if not a special pattern
if (!lower_special) {
- SDValue LO32C = DAG.getConstant(lower, EVT::i32);
+ SDValue LO32C = DAG.getConstant(lower, MVT::i32);
LO32 = DAG.getNode(ISD::BIT_CONVERT, dl, OpVT,
- DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
LO32C, LO32C, LO32C, LO32C));
}
// Create upper vector if not a special pattern
if (!upper_special) {
- SDValue HI32C = DAG.getConstant(upper, EVT::i32);
+ SDValue HI32C = DAG.getConstant(upper, MVT::i32);
HI32 = DAG.getNode(ISD::BIT_CONVERT, dl, OpVT,
- DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
HI32C, HI32C, HI32C, HI32C));
}
@@ -1720,11 +1720,11 @@
val |= i * 4 + j + ((i & 1) * 16);
}
- ShufBytes.push_back(DAG.getConstant(val, EVT::i32));
+ ShufBytes.push_back(DAG.getConstant(val, MVT::i32));
}
return DAG.getNode(SPUISD::SHUFB, dl, OpVT, HI32, LO32,
- DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
&ShufBytes[0], ShufBytes.size()));
}
}
@@ -1765,13 +1765,13 @@
bool monotonic = true;
bool rotate = true;
- if (EltVT == EVT::i8) {
+ if (EltVT == MVT::i8) {
V2EltIdx0 = 16;
- } else if (EltVT == EVT::i16) {
+ } else if (EltVT == MVT::i16) {
V2EltIdx0 = 8;
- } else if (EltVT == EVT::i32 || EltVT == EVT::f32) {
+ } else if (EltVT == MVT::i32 || EltVT == MVT::f32) {
V2EltIdx0 = 4;
- } else if (EltVT == EVT::i64 || EltVT == EVT::f64) {
+ } else if (EltVT == MVT::i64 || EltVT == MVT::f64) {
V2EltIdx0 = 2;
} else
llvm_unreachable("Unhandled vector type in LowerVECTOR_SHUFFLE");
@@ -1825,8 +1825,8 @@
DAG.getCopyToReg(DAG.getEntryNode(), dl, VReg, DAG.getConstant(0, PtrVT));
// Copy register's contents as index in SHUFFLE_MASK:
SDValue ShufMaskOp =
- DAG.getNode(SPUISD::SHUFFLE_MASK, dl, EVT::v4i32,
- DAG.getTargetConstant(V2Elt, EVT::i32),
+ DAG.getNode(SPUISD::SHUFFLE_MASK, dl, MVT::v4i32,
+ DAG.getTargetConstant(V2Elt, MVT::i32),
DAG.getCopyFromReg(InitTempReg, dl, VReg, PtrVT));
// Use shuffle mask in SHUFB synthetic instruction:
return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V2, V1,
@@ -1835,7 +1835,7 @@
int rotamt = (MaxElts - V0Elt) * EltVT.getSizeInBits()/8;
return DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, V1.getValueType(),
- V1, DAG.getConstant(rotamt, EVT::i16));
+ V1, DAG.getConstant(rotamt, MVT::i16));
} else {
// Convert the SHUFFLE_VECTOR mask's input element units to the
// actual bytes.
@@ -1846,10 +1846,10 @@
unsigned SrcElt = SVN->getMaskElt(i) < 0 ? 0 : SVN->getMaskElt(i);
for (unsigned j = 0; j < BytesPerElement; ++j)
- ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,EVT::i8));
+ ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,MVT::i8));
}
- SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v16i8,
+ SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
&ResultMask[0], ResultMask.size());
return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V1, V2, VPermMask);
}
@@ -1869,15 +1869,15 @@
size_t n_copies;
// Create a constant vector:
- switch (Op.getValueType().getSimpleVT()) {
+ switch (Op.getValueType().getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unexpected constant value type in "
"LowerSCALAR_TO_VECTOR");
- case EVT::v16i8: n_copies = 16; VT = EVT::i8; break;
- case EVT::v8i16: n_copies = 8; VT = EVT::i16; break;
- case EVT::v4i32: n_copies = 4; VT = EVT::i32; break;
- case EVT::v4f32: n_copies = 4; VT = EVT::f32; break;
- case EVT::v2i64: n_copies = 2; VT = EVT::i64; break;
- case EVT::v2f64: n_copies = 2; VT = EVT::f64; break;
+ case MVT::v16i8: n_copies = 16; VT = MVT::i8; break;
+ case MVT::v8i16: n_copies = 8; VT = MVT::i16; break;
+ case MVT::v4i32: n_copies = 4; VT = MVT::i32; break;
+ case MVT::v4f32: n_copies = 4; VT = MVT::f32; break;
+ case MVT::v2i64: n_copies = 2; VT = MVT::i64; break;
+ case MVT::v2f64: n_copies = 2; VT = MVT::f64; break;
}
SDValue CValue = DAG.getConstant(CN->getZExtValue(), VT);
@@ -1888,14 +1888,14 @@
&ConstVecValues[0], ConstVecValues.size());
} else {
// Otherwise, copy the value from one register to another:
- switch (Op0.getValueType().getSimpleVT()) {
+ switch (Op0.getValueType().getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unexpected value type in LowerSCALAR_TO_VECTOR");
- case EVT::i8:
- case EVT::i16:
- case EVT::i32:
- case EVT::i64:
- case EVT::f32:
- case EVT::f64:
+ case MVT::i8:
+ case MVT::i16:
+ case MVT::i32:
+ case MVT::i64:
+ case MVT::f32:
+ case MVT::f64:
return DAG.getNode(SPUISD::PREFSLOT2VEC, dl, Op.getValueType(), Op0, Op0);
}
}
@@ -1915,16 +1915,16 @@
int EltNo = (int) C->getZExtValue();
// sanity checks:
- if (VT == EVT::i8 && EltNo >= 16)
+ if (VT == MVT::i8 && EltNo >= 16)
llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i8 extraction slot > 15");
- else if (VT == EVT::i16 && EltNo >= 8)
+ else if (VT == MVT::i16 && EltNo >= 8)
llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i16 extraction slot > 7");
- else if (VT == EVT::i32 && EltNo >= 4)
+ else if (VT == MVT::i32 && EltNo >= 4)
llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i32 extraction slot > 4");
- else if (VT == EVT::i64 && EltNo >= 2)
+ else if (VT == MVT::i64 && EltNo >= 2)
llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i64 extraction slot > 2");
- if (EltNo == 0 && (VT == EVT::i32 || VT == EVT::i64)) {
+ if (EltNo == 0 && (VT == MVT::i32 || VT == MVT::i64)) {
// i32 and i64: Element 0 is the preferred slot
return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, N);
}
@@ -1933,24 +1933,24 @@
int prefslot_begin = -1, prefslot_end = -1;
int elt_byte = EltNo * VT.getSizeInBits() / 8;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default:
assert(false && "Invalid value type!");
- case EVT::i8: {
+ case MVT::i8: {
prefslot_begin = prefslot_end = 3;
break;
}
- case EVT::i16: {
+ case MVT::i16: {
prefslot_begin = 2; prefslot_end = 3;
break;
}
- case EVT::i32:
- case EVT::f32: {
+ case MVT::i32:
+ case MVT::f32: {
prefslot_begin = 0; prefslot_end = 3;
break;
}
- case EVT::i64:
- case EVT::f64: {
+ case MVT::i64:
+ case MVT::f64: {
prefslot_begin = 0; prefslot_end = 7;
break;
}
@@ -1982,11 +1982,11 @@
(ShufBytes[bidx+1] << 16) |
(ShufBytes[bidx+2] << 8) |
ShufBytes[bidx+3]);
- ShufMask[i] = DAG.getConstant(bits, EVT::i32);
+ ShufMask[i] = DAG.getConstant(bits, MVT::i32);
}
SDValue ShufMaskVec =
- DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
&ShufMask[0], sizeof(ShufMask)/sizeof(ShufMask[0]));
retval = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT,
@@ -2002,8 +2002,8 @@
}
// Make life easier by making sure the index is zero-extended to i32
- if (Elt.getValueType() != EVT::i32)
- Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, EVT::i32, Elt);
+ if (Elt.getValueType() != MVT::i32)
+ Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Elt);
// Scale the index to a bit/byte shift quantity
APInt scaleFactor =
@@ -2013,8 +2013,8 @@
if (scaleShift > 0) {
// Scale the shift factor:
- Elt = DAG.getNode(ISD::SHL, dl, EVT::i32, Elt,
- DAG.getConstant(scaleShift, EVT::i32));
+ Elt = DAG.getNode(ISD::SHL, dl, MVT::i32, Elt,
+ DAG.getConstant(scaleShift, MVT::i32));
}
vecShift = DAG.getNode(SPUISD::SHLQUAD_L_BYTES, dl, VecVT, N, Elt);
@@ -2023,35 +2023,35 @@
// consistency with the notion of a unified register set)
SDValue replicate;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default:
llvm_report_error("LowerEXTRACT_VECTOR_ELT(varable): Unhandled vector"
"type");
/*NOTREACHED*/
- case EVT::i8: {
- SDValue factor = DAG.getConstant(0x00000000, EVT::i32);
- replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ case MVT::i8: {
+ SDValue factor = DAG.getConstant(0x00000000, MVT::i32);
+ replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
factor, factor, factor, factor);
break;
}
- case EVT::i16: {
- SDValue factor = DAG.getConstant(0x00010001, EVT::i32);
- replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ case MVT::i16: {
+ SDValue factor = DAG.getConstant(0x00010001, MVT::i32);
+ replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
factor, factor, factor, factor);
break;
}
- case EVT::i32:
- case EVT::f32: {
- SDValue factor = DAG.getConstant(0x00010203, EVT::i32);
- replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ case MVT::i32:
+ case MVT::f32: {
+ SDValue factor = DAG.getConstant(0x00010203, MVT::i32);
+ replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
factor, factor, factor, factor);
break;
}
- case EVT::i64:
- case EVT::f64: {
- SDValue loFactor = DAG.getConstant(0x00010203, EVT::i32);
- SDValue hiFactor = DAG.getConstant(0x04050607, EVT::i32);
- replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ case MVT::i64:
+ case MVT::f64: {
+ SDValue loFactor = DAG.getConstant(0x00010203, MVT::i32);
+ SDValue hiFactor = DAG.getConstant(0x04050607, MVT::i32);
+ replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
loFactor, hiFactor, loFactor, hiFactor);
break;
}
@@ -2086,7 +2086,7 @@
DAG.getNode(SPUISD::SHUFB, dl, VT,
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, ValOp),
VecOp,
- DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v4i32, ShufMask));
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, ShufMask));
return result;
}
@@ -2098,7 +2098,7 @@
DebugLoc dl = Op.getDebugLoc();
EVT ShiftVT = TLI.getShiftAmountTy();
- assert(Op.getValueType() == EVT::i8);
+ assert(Op.getValueType() == MVT::i8);
switch (Opc) {
default:
llvm_unreachable("Unhandled i8 math operator");
@@ -2108,10 +2108,10 @@
// 8-bit addition: Promote the arguments up to 16-bits and truncate
// the result:
SDValue N1 = Op.getOperand(1);
- N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N0);
- N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N1);
- return DAG.getNode(ISD::TRUNCATE, dl, EVT::i8,
- DAG.getNode(Opc, dl, EVT::i16, N0, N1));
+ N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
+ N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1);
+ return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
+ DAG.getNode(Opc, dl, MVT::i16, N0, N1));
}
@@ -2119,17 +2119,17 @@
// 8-bit subtraction: Promote the arguments up to 16-bits and truncate
// the result:
SDValue N1 = Op.getOperand(1);
- N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N0);
- N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N1);
- return DAG.getNode(ISD::TRUNCATE, dl, EVT::i8,
- DAG.getNode(Opc, dl, EVT::i16, N0, N1));
+ N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
+ N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1);
+ return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
+ DAG.getNode(Opc, dl, MVT::i16, N0, N1));
}
case ISD::ROTR:
case ISD::ROTL: {
SDValue N1 = Op.getOperand(1);
EVT N1VT = N1.getValueType();
- N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, EVT::i16, N0);
+ N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, N0);
if (!N1VT.bitsEq(ShiftVT)) {
unsigned N1Opc = N1.getValueType().bitsLT(ShiftVT)
? ISD::ZERO_EXTEND
@@ -2139,20 +2139,20 @@
// Replicate lower 8-bits into upper 8:
SDValue ExpandArg =
- DAG.getNode(ISD::OR, dl, EVT::i16, N0,
- DAG.getNode(ISD::SHL, dl, EVT::i16,
- N0, DAG.getConstant(8, EVT::i32)));
+ DAG.getNode(ISD::OR, dl, MVT::i16, N0,
+ DAG.getNode(ISD::SHL, dl, MVT::i16,
+ N0, DAG.getConstant(8, MVT::i32)));
// Truncate back down to i8
- return DAG.getNode(ISD::TRUNCATE, dl, EVT::i8,
- DAG.getNode(Opc, dl, EVT::i16, ExpandArg, N1));
+ return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
+ DAG.getNode(Opc, dl, MVT::i16, ExpandArg, N1));
}
case ISD::SRL:
case ISD::SHL: {
SDValue N1 = Op.getOperand(1);
EVT N1VT = N1.getValueType();
- N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, EVT::i16, N0);
+ N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, N0);
if (!N1VT.bitsEq(ShiftVT)) {
unsigned N1Opc = ISD::ZERO_EXTEND;
@@ -2162,14 +2162,14 @@
N1 = DAG.getNode(N1Opc, dl, ShiftVT, N1);
}
- return DAG.getNode(ISD::TRUNCATE, dl, EVT::i8,
- DAG.getNode(Opc, dl, EVT::i16, N0, N1));
+ return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
+ DAG.getNode(Opc, dl, MVT::i16, N0, N1));
}
case ISD::SRA: {
SDValue N1 = Op.getOperand(1);
EVT N1VT = N1.getValueType();
- N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N0);
+ N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
if (!N1VT.bitsEq(ShiftVT)) {
unsigned N1Opc = ISD::SIGN_EXTEND;
@@ -2178,16 +2178,16 @@
N1 = DAG.getNode(N1Opc, dl, ShiftVT, N1);
}
- return DAG.getNode(ISD::TRUNCATE, dl, EVT::i8,
- DAG.getNode(Opc, dl, EVT::i16, N0, N1));
+ return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
+ DAG.getNode(Opc, dl, MVT::i16, N0, N1));
}
case ISD::MUL: {
SDValue N1 = Op.getOperand(1);
- N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N0);
- N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N1);
- return DAG.getNode(ISD::TRUNCATE, dl, EVT::i8,
- DAG.getNode(Opc, dl, EVT::i16, N0, N1));
+ N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
+ N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1);
+ return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
+ DAG.getNode(Opc, dl, MVT::i16, N0, N1));
break;
}
}
@@ -2230,7 +2230,7 @@
HasAnyUndefs, minSplatBits)
&& minSplatBits <= SplatBitSize) {
uint64_t SplatBits = APSplatBits.getZExtValue();
- SDValue tc = DAG.getTargetConstant(SplatBits & 0xff, EVT::i8);
+ SDValue tc = DAG.getTargetConstant(SplatBits & 0xff, MVT::i8);
SmallVector<SDValue, 16> tcVec;
tcVec.assign(16, tc);
@@ -2255,29 +2255,29 @@
EVT vecVT = EVT::getVectorVT(VT, (128 / VT.getSizeInBits()));
DebugLoc dl = Op.getDebugLoc();
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default:
assert(false && "Invalid value type!");
- case EVT::i8: {
+ case MVT::i8: {
SDValue N = Op.getOperand(0);
- SDValue Elt0 = DAG.getConstant(0, EVT::i32);
+ SDValue Elt0 = DAG.getConstant(0, MVT::i32);
SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N);
SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote);
- return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i8, CNTB, Elt0);
+ return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i8, CNTB, Elt0);
}
- case EVT::i16: {
+ case MVT::i16: {
MachineFunction &MF = DAG.getMachineFunction();
MachineRegisterInfo &RegInfo = MF.getRegInfo();
unsigned CNTB_reg = RegInfo.createVirtualRegister(&SPU::R16CRegClass);
SDValue N = Op.getOperand(0);
- SDValue Elt0 = DAG.getConstant(0, EVT::i16);
- SDValue Mask0 = DAG.getConstant(0x0f, EVT::i16);
- SDValue Shift1 = DAG.getConstant(8, EVT::i32);
+ SDValue Elt0 = DAG.getConstant(0, MVT::i16);
+ SDValue Mask0 = DAG.getConstant(0x0f, MVT::i16);
+ SDValue Shift1 = DAG.getConstant(8, MVT::i32);
SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N);
SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote);
@@ -2285,22 +2285,22 @@
// CNTB_result becomes the chain to which all of the virtual registers
// CNTB_reg, SUM1_reg become associated:
SDValue CNTB_result =
- DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i16, CNTB, Elt0);
+ DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, CNTB, Elt0);
SDValue CNTB_rescopy =
DAG.getCopyToReg(CNTB_result, dl, CNTB_reg, CNTB_result);
- SDValue Tmp1 = DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, EVT::i16);
+ SDValue Tmp1 = DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i16);
- return DAG.getNode(ISD::AND, dl, EVT::i16,
- DAG.getNode(ISD::ADD, dl, EVT::i16,
- DAG.getNode(ISD::SRL, dl, EVT::i16,
+ return DAG.getNode(ISD::AND, dl, MVT::i16,
+ DAG.getNode(ISD::ADD, dl, MVT::i16,
+ DAG.getNode(ISD::SRL, dl, MVT::i16,
Tmp1, Shift1),
Tmp1),
Mask0);
}
- case EVT::i32: {
+ case MVT::i32: {
MachineFunction &MF = DAG.getMachineFunction();
MachineRegisterInfo &RegInfo = MF.getRegInfo();
@@ -2308,10 +2308,10 @@
unsigned SUM1_reg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
SDValue N = Op.getOperand(0);
- SDValue Elt0 = DAG.getConstant(0, EVT::i32);
- SDValue Mask0 = DAG.getConstant(0xff, EVT::i32);
- SDValue Shift1 = DAG.getConstant(16, EVT::i32);
- SDValue Shift2 = DAG.getConstant(8, EVT::i32);
+ SDValue Elt0 = DAG.getConstant(0, MVT::i32);
+ SDValue Mask0 = DAG.getConstant(0xff, MVT::i32);
+ SDValue Shift1 = DAG.getConstant(16, MVT::i32);
+ SDValue Shift2 = DAG.getConstant(8, MVT::i32);
SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N);
SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote);
@@ -2319,35 +2319,35 @@
// CNTB_result becomes the chain to which all of the virtual registers
// CNTB_reg, SUM1_reg become associated:
SDValue CNTB_result =
- DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i32, CNTB, Elt0);
+ DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, CNTB, Elt0);
SDValue CNTB_rescopy =
DAG.getCopyToReg(CNTB_result, dl, CNTB_reg, CNTB_result);
SDValue Comp1 =
- DAG.getNode(ISD::SRL, dl, EVT::i32,
- DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, EVT::i32),
+ DAG.getNode(ISD::SRL, dl, MVT::i32,
+ DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i32),
Shift1);
SDValue Sum1 =
- DAG.getNode(ISD::ADD, dl, EVT::i32, Comp1,
- DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, EVT::i32));
+ DAG.getNode(ISD::ADD, dl, MVT::i32, Comp1,
+ DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i32));
SDValue Sum1_rescopy =
DAG.getCopyToReg(CNTB_result, dl, SUM1_reg, Sum1);
SDValue Comp2 =
- DAG.getNode(ISD::SRL, dl, EVT::i32,
- DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, EVT::i32),
+ DAG.getNode(ISD::SRL, dl, MVT::i32,
+ DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, MVT::i32),
Shift2);
SDValue Sum2 =
- DAG.getNode(ISD::ADD, dl, EVT::i32, Comp2,
- DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, EVT::i32));
+ DAG.getNode(ISD::ADD, dl, MVT::i32, Comp2,
+ DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, MVT::i32));
- return DAG.getNode(ISD::AND, dl, EVT::i32, Sum2, Mask0);
+ return DAG.getNode(ISD::AND, dl, MVT::i32, Sum2, Mask0);
}
- case EVT::i64:
+ case MVT::i64:
break;
}
@@ -2365,8 +2365,8 @@
SDValue Op0 = Op.getOperand(0);
EVT Op0VT = Op0.getValueType();
- if ((OpVT == EVT::i32 && Op0VT == EVT::f64)
- || OpVT == EVT::i64) {
+ if ((OpVT == MVT::i32 && Op0VT == MVT::f64)
+ || OpVT == MVT::i64) {
// Convert f32 / f64 to i32 / i64 via libcall.
RTLIB::Libcall LC =
(Op.getOpcode() == ISD::FP_TO_SINT)
@@ -2391,8 +2391,8 @@
SDValue Op0 = Op.getOperand(0);
EVT Op0VT = Op0.getValueType();
- if ((OpVT == EVT::f64 && Op0VT == EVT::i32)
- || Op0VT == EVT::i64) {
+ if ((OpVT == MVT::f64 && Op0VT == MVT::i32)
+ || Op0VT == MVT::i64) {
// Convert i32, i64 to f64 via libcall:
RTLIB::Libcall LC =
(Op.getOpcode() == ISD::SINT_TO_FP)
@@ -2408,7 +2408,7 @@
//! Lower ISD::SETCC
/*!
- This handles EVT::f64 (double floating point) condition lowering
+ This handles MVT::f64 (double floating point) condition lowering
*/
static SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG,
const TargetLowering &TLI) {
@@ -2419,24 +2419,24 @@
SDValue lhs = Op.getOperand(0);
SDValue rhs = Op.getOperand(1);
EVT lhsVT = lhs.getValueType();
- assert(lhsVT == EVT::f64 && "LowerSETCC: type other than EVT::64\n");
+ assert(lhsVT == MVT::f64 && "LowerSETCC: type other than MVT::64\n");
EVT ccResultVT = TLI.getSetCCResultType(lhs.getValueType());
APInt ccResultOnes = APInt::getAllOnesValue(ccResultVT.getSizeInBits());
- EVT IntVT(EVT::i64);
+ EVT IntVT(MVT::i64);
// Take advantage of the fact that (truncate (sra arg, 32)) is efficiently
// selected to a NOP:
SDValue i64lhs = DAG.getNode(ISD::BIT_CONVERT, dl, IntVT, lhs);
SDValue lhsHi32 =
- DAG.getNode(ISD::TRUNCATE, dl, EVT::i32,
+ DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
DAG.getNode(ISD::SRL, dl, IntVT,
- i64lhs, DAG.getConstant(32, EVT::i32)));
+ i64lhs, DAG.getConstant(32, MVT::i32)));
SDValue lhsHi32abs =
- DAG.getNode(ISD::AND, dl, EVT::i32,
- lhsHi32, DAG.getConstant(0x7fffffff, EVT::i32));
+ DAG.getNode(ISD::AND, dl, MVT::i32,
+ lhsHi32, DAG.getConstant(0x7fffffff, MVT::i32));
SDValue lhsLo32 =
- DAG.getNode(ISD::TRUNCATE, dl, EVT::i32, i64lhs);
+ DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, i64lhs);
// SETO and SETUO only use the lhs operand:
if (CC->get() == ISD::SETO) {
@@ -2453,33 +2453,33 @@
return DAG.getNode(ISD::AND, dl, ccResultVT,
DAG.getSetCC(dl, ccResultVT,
lhsHi32abs,
- DAG.getConstant(0x7ff00000, EVT::i32),
+ DAG.getConstant(0x7ff00000, MVT::i32),
ISD::SETGE),
DAG.getSetCC(dl, ccResultVT,
lhsLo32,
- DAG.getConstant(0, EVT::i32),
+ DAG.getConstant(0, MVT::i32),
ISD::SETGT));
}
SDValue i64rhs = DAG.getNode(ISD::BIT_CONVERT, dl, IntVT, rhs);
SDValue rhsHi32 =
- DAG.getNode(ISD::TRUNCATE, dl, EVT::i32,
+ DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
DAG.getNode(ISD::SRL, dl, IntVT,
- i64rhs, DAG.getConstant(32, EVT::i32)));
+ i64rhs, DAG.getConstant(32, MVT::i32)));
// If a value is negative, subtract from the sign magnitude constant:
SDValue signMag2TC = DAG.getConstant(0x8000000000000000ULL, IntVT);
// Convert the sign-magnitude representation into 2's complement:
SDValue lhsSelectMask = DAG.getNode(ISD::SRA, dl, ccResultVT,
- lhsHi32, DAG.getConstant(31, EVT::i32));
+ lhsHi32, DAG.getConstant(31, MVT::i32));
SDValue lhsSignMag2TC = DAG.getNode(ISD::SUB, dl, IntVT, signMag2TC, i64lhs);
SDValue lhsSelect =
DAG.getNode(ISD::SELECT, dl, IntVT,
lhsSelectMask, lhsSignMag2TC, i64lhs);
SDValue rhsSelectMask = DAG.getNode(ISD::SRA, dl, ccResultVT,
- rhsHi32, DAG.getConstant(31, EVT::i32));
+ rhsHi32, DAG.getConstant(31, MVT::i32));
SDValue rhsSignMag2TC = DAG.getNode(ISD::SUB, dl, IntVT, signMag2TC, i64rhs);
SDValue rhsSelect =
DAG.getNode(ISD::SELECT, dl, IntVT,
@@ -2517,10 +2517,10 @@
if ((CC->get() & 0x8) == 0) {
// Ordered comparison:
SDValue lhsNaN = DAG.getSetCC(dl, ccResultVT,
- lhs, DAG.getConstantFP(0.0, EVT::f64),
+ lhs, DAG.getConstantFP(0.0, MVT::f64),
ISD::SETO);
SDValue rhsNaN = DAG.getSetCC(dl, ccResultVT,
- rhs, DAG.getConstantFP(0.0, EVT::f64),
+ rhs, DAG.getConstantFP(0.0, MVT::f64),
ISD::SETO);
SDValue ordered = DAG.getNode(ISD::AND, dl, ccResultVT, lhsNaN, rhsNaN);
@@ -2574,7 +2574,7 @@
{
// Type to truncate to
EVT VT = Op.getValueType();
- EVT::SimpleValueType simpleVT = VT.getSimpleVT();
+ MVT simpleVT = VT.getSimpleVT();
EVT VecVT = EVT::getVectorVT(VT, (128 / VT.getSizeInBits()));
DebugLoc dl = Op.getDebugLoc();
@@ -2582,16 +2582,16 @@
SDValue Op0 = Op.getOperand(0);
EVT Op0VT = Op0.getValueType();
- if (Op0VT.getSimpleVT() == EVT::i128 && simpleVT == EVT::i64) {
+ if (Op0VT.getSimpleVT() == MVT::i128 && simpleVT == MVT::i64) {
// Create shuffle mask, least significant doubleword of quadword
unsigned maskHigh = 0x08090a0b;
unsigned maskLow = 0x0c0d0e0f;
// Use a shuffle to perform the truncation
- SDValue shufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
- DAG.getConstant(maskHigh, EVT::i32),
- DAG.getConstant(maskLow, EVT::i32),
- DAG.getConstant(maskHigh, EVT::i32),
- DAG.getConstant(maskLow, EVT::i32));
+ SDValue shufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ DAG.getConstant(maskHigh, MVT::i32),
+ DAG.getConstant(maskLow, MVT::i32),
+ DAG.getConstant(maskHigh, MVT::i32),
+ DAG.getConstant(maskLow, MVT::i32));
SDValue truncShuffle = DAG.getNode(SPUISD::SHUFB, dl, VecVT,
Op0, Op0, shufMask);
@@ -2647,7 +2647,7 @@
case ISD::SRL:
case ISD::SHL:
case ISD::SRA: {
- if (VT == EVT::i8)
+ if (VT == MVT::i8)
return LowerI8Math(Op, DAG, Opc, *this);
break;
}
@@ -2680,7 +2680,7 @@
// Vector and i8 multiply:
case ISD::MUL:
- if (VT == EVT::i8)
+ if (VT == MVT::i8)
return LowerI8Math(Op, DAG, Opc, *this);
case ISD::CTPOP:
@@ -2945,13 +2945,13 @@
switch (Constraint[0]) {
case 'b': // R1-R31
case 'r': // R0-R31
- if (VT == EVT::i64)
+ if (VT == MVT::i64)
return std::make_pair(0U, SPU::R64CRegisterClass);
return std::make_pair(0U, SPU::R32CRegisterClass);
case 'f':
- if (VT == EVT::f32)
+ if (VT == MVT::f32)
return std::make_pair(0U, SPU::R32FPRegisterClass);
- else if (VT == EVT::f64)
+ else if (VT == MVT::f64)
return std::make_pair(0U, SPU::R64FPRegisterClass);
break;
case 'v':
@@ -3008,8 +3008,8 @@
case ISD::SETCC: {
EVT VT = Op.getValueType();
- if (VT != EVT::i8 && VT != EVT::i16 && VT != EVT::i32) {
- VT = EVT::i32;
+ if (VT != MVT::i8 && VT != MVT::i16 && VT != MVT::i32) {
+ VT = MVT::i32;
}
return VT.getSizeInBits();
}
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h Tue Aug 11 15:47:22 2009
@@ -109,7 +109,7 @@
virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - Return the ValueType for ISD::SETCC
- virtual EVT::SimpleValueType getSetCCResultType(EVT VT) const;
+ virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
//! Custom lowering hooks
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
Modified: llvm/trunk/lib/Target/CellSPU/SPUOperands.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUOperands.td?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUOperands.td (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUOperands.td Tue Aug 11 15:47:22 2009
@@ -144,7 +144,7 @@
def lo16 : PatLeaf<(imm), [{
// lo16 predicate - returns true if the immediate has all zeros in the
// low order bits and is a 32-bit constant:
- if (N->getValueType(0) == EVT::i32) {
+ if (N->getValueType(0) == MVT::i32) {
uint32_t val = N->getZExtValue();
return ((val & 0x0000ffff) == val);
}
@@ -155,10 +155,10 @@
def hi16 : PatLeaf<(imm), [{
// hi16 predicate - returns true if the immediate has all zeros in the
// low order bits and is a 32-bit constant:
- if (N->getValueType(0) == EVT::i32) {
+ if (N->getValueType(0) == MVT::i32) {
uint32_t val = uint32_t(N->getZExtValue());
return ((val & 0xffff0000) == val);
- } else if (N->getValueType(0) == EVT::i64) {
+ } else if (N->getValueType(0) == MVT::i64) {
uint64_t val = N->getZExtValue();
return ((val & 0xffff0000ULL) == val);
}
@@ -208,7 +208,7 @@
// Does the SFP constant only have upp 16 bits set?
def hi16_f32 : PatLeaf<(fpimm), [{
- if (N->getValueType(0) == EVT::f32) {
+ if (N->getValueType(0) == MVT::f32) {
uint32_t val = FloatToBits(N->getValueAPF().convertToFloat());
return ((val & 0xffff0000) == val);
}
@@ -218,7 +218,7 @@
// Does the SFP constant fit into 18 bits?
def fpimm18 : PatLeaf<(fpimm), [{
- if (N->getValueType(0) == EVT::f32) {
+ if (N->getValueType(0) == MVT::f32) {
uint32_t Value = FloatToBits(N->getValueAPF().convertToFloat());
return ((Value & ((1 << 19) - 1)) == Value);
}
@@ -238,7 +238,7 @@
// immediate constant load for v16i8 vectors. N.B.: The incoming constant has
// to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a).
def v16i8SExt8Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i8imm(N, *CurDAG, EVT::i8);
+ return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8);
}]>;
// v16i8SExt8Imm: Predicate test for 8-bit sign extended immediate constant
@@ -246,14 +246,14 @@
// incoming constant being a 16-bit quantity, where the upper and lower bytes
// are EXACTLY the same (e.g., 0x2a2a)
def v16i8SExt8Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i8imm(N, *CurDAG, EVT::i8).getNode() != 0;
+ return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).getNode() != 0;
}], v16i8SExt8Imm_xform>;
// v16i8U8Imm_xform function: convert build_vector to unsigned 8-bit
// immediate constant load for v16i8 vectors. N.B.: The incoming constant has
// to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a).
def v16i8U8Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i8imm(N, *CurDAG, EVT::i8);
+ return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8);
}]>;
// v16i8U8Imm: Predicate test for unsigned 8-bit immediate constant
@@ -261,114 +261,114 @@
// incoming constant being a 16-bit quantity, where the upper and lower bytes
// are EXACTLY the same (e.g., 0x2a2a)
def v16i8U8Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i8imm(N, *CurDAG, EVT::i8).getNode() != 0;
+ return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).getNode() != 0;
}], v16i8U8Imm_xform>;
// v8i16SExt8Imm_xform function: convert build_vector to 8-bit sign extended
// immediate constant load for v8i16 vectors.
def v8i16SExt8Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i8imm(N, *CurDAG, EVT::i16);
+ return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16);
}]>;
// v8i16SExt8Imm: Predicate test for 8-bit sign extended immediate constant
// load, works in conjunction with its transform function.
def v8i16SExt8Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i8imm(N, *CurDAG, EVT::i16).getNode() != 0;
+ return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16).getNode() != 0;
}], v8i16SExt8Imm_xform>;
// v8i16SExt10Imm_xform function: convert build_vector to 16-bit sign extended
// immediate constant load for v8i16 vectors.
def v8i16SExt10Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i10imm(N, *CurDAG, EVT::i16);
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16);
}]>;
// v8i16SExt10Imm: Predicate test for 16-bit sign extended immediate constant
// load, works in conjunction with its transform function.
def v8i16SExt10Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i10imm(N, *CurDAG, EVT::i16).getNode() != 0;
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).getNode() != 0;
}], v8i16SExt10Imm_xform>;
// v8i16Uns10Imm_xform function: convert build_vector to 16-bit unsigned
// immediate constant load for v8i16 vectors.
def v8i16Uns10Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i10imm(N, *CurDAG, EVT::i16);
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16);
}]>;
// v8i16Uns10Imm: Predicate test for 16-bit unsigned immediate constant
// load, works in conjunction with its transform function.
def v8i16Uns10Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i10imm(N, *CurDAG, EVT::i16).getNode() != 0;
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).getNode() != 0;
}], v8i16Uns10Imm_xform>;
// v8i16SExt16Imm_xform function: convert build_vector to 16-bit sign extended
// immediate constant load for v8i16 vectors.
def v8i16Uns16Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i16imm(N, *CurDAG, EVT::i16);
+ return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16);
}]>;
// v8i16SExt16Imm: Predicate test for 16-bit sign extended immediate constant
// load, works in conjunction with its transform function.
def v8i16SExt16Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i16imm(N, *CurDAG, EVT::i16).getNode() != 0;
+ return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16).getNode() != 0;
}], v8i16Uns16Imm_xform>;
// v4i32SExt10Imm_xform function: convert build_vector to 10-bit sign extended
// immediate constant load for v4i32 vectors.
def v4i32SExt10Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i10imm(N, *CurDAG, EVT::i32);
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32);
}]>;
// v4i32SExt10Imm: Predicate test for 10-bit sign extended immediate constant
// load, works in conjunction with its transform function.
def v4i32SExt10Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i10imm(N, *CurDAG, EVT::i32).getNode() != 0;
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).getNode() != 0;
}], v4i32SExt10Imm_xform>;
// v4i32Uns10Imm_xform function: convert build_vector to 10-bit unsigned
// immediate constant load for v4i32 vectors.
def v4i32Uns10Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i10imm(N, *CurDAG, EVT::i32);
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32);
}]>;
// v4i32Uns10Imm: Predicate test for 10-bit unsigned immediate constant
// load, works in conjunction with its transform function.
def v4i32Uns10Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i10imm(N, *CurDAG, EVT::i32).getNode() != 0;
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).getNode() != 0;
}], v4i32Uns10Imm_xform>;
// v4i32SExt16Imm_xform function: convert build_vector to 16-bit sign extended
// immediate constant load for v4i32 vectors.
def v4i32SExt16Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i16imm(N, *CurDAG, EVT::i32);
+ return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32);
}]>;
// v4i32SExt16Imm: Predicate test for 16-bit sign extended immediate constant
// load, works in conjunction with its transform function.
def v4i32SExt16Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i16imm(N, *CurDAG, EVT::i32).getNode() != 0;
+ return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32).getNode() != 0;
}], v4i32SExt16Imm_xform>;
// v4i32Uns18Imm_xform function: convert build_vector to 18-bit unsigned
// immediate constant load for v4i32 vectors.
def v4i32Uns18Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_u18imm(N, *CurDAG, EVT::i32);
+ return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32);
}]>;
// v4i32Uns18Imm: Predicate test for 18-bit unsigned immediate constant load,
// works in conjunction with its transform function.
def v4i32Uns18Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_u18imm(N, *CurDAG, EVT::i32).getNode() != 0;
+ return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32).getNode() != 0;
}], v4i32Uns18Imm_xform>;
// ILHUvec_get_imm xform function: convert build_vector to ILHUvec imm constant
// load.
def ILHUvec_get_imm: SDNodeXForm<build_vector, [{
- return SPU::get_ILHUvec_imm(N, *CurDAG, EVT::i32);
+ return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32);
}]>;
/// immILHUvec: Predicate test for a ILHU constant vector.
def immILHUvec: PatLeaf<(build_vector), [{
- return SPU::get_ILHUvec_imm(N, *CurDAG, EVT::i32).getNode() != 0;
+ return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32).getNode() != 0;
}], ILHUvec_get_imm>;
// Catch-all for any other i32 vector constants
@@ -383,42 +383,42 @@
// v2i64SExt10Imm_xform function: convert build_vector to 10-bit sign extended
// immediate constant load for v2i64 vectors.
def v2i64SExt10Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i10imm(N, *CurDAG, EVT::i64);
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64);
}]>;
// v2i64SExt10Imm: Predicate test for 10-bit sign extended immediate constant
// load, works in conjunction with its transform function.
def v2i64SExt10Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i10imm(N, *CurDAG, EVT::i64).getNode() != 0;
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64).getNode() != 0;
}], v2i64SExt10Imm_xform>;
// v2i64SExt16Imm_xform function: convert build_vector to 16-bit sign extended
// immediate constant load for v2i64 vectors.
def v2i64SExt16Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i16imm(N, *CurDAG, EVT::i64);
+ return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64);
}]>;
// v2i64SExt16Imm: Predicate test for 16-bit sign extended immediate constant
// load, works in conjunction with its transform function.
def v2i64SExt16Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i16imm(N, *CurDAG, EVT::i64).getNode() != 0;
+ return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64).getNode() != 0;
}], v2i64SExt16Imm_xform>;
// v2i64Uns18Imm_xform function: convert build_vector to 18-bit unsigned
// immediate constant load for v2i64 vectors.
def v2i64Uns18Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_u18imm(N, *CurDAG, EVT::i64);
+ return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64);
}]>;
// v2i64Uns18Imm: Predicate test for 18-bit unsigned immediate constant load,
// works in conjunction with its transform function.
def v2i64Uns18Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_u18imm(N, *CurDAG, EVT::i64).getNode() != 0;
+ return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64).getNode() != 0;
}], v2i64Uns18Imm_xform>;
/// immILHUvec: Predicate test for a ILHU constant vector.
def immILHUvec_i64: PatLeaf<(build_vector), [{
- return SPU::get_ILHUvec_imm(N, *CurDAG, EVT::i64).getNode() != 0;
+ return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i64).getNode() != 0;
}], ILHUvec_get_imm>;
// Catch-all for any other i32 vector constants
Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp Tue Aug 11 15:47:22 2009
@@ -78,8 +78,8 @@
SDValue &Base, SDValue &Disp) {
// Try to match frame address first.
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i16);
- Disp = CurDAG->getTargetConstant(0, EVT::i16);
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i16);
+ Disp = CurDAG->getTargetConstant(0, MVT::i16);
return true;
}
@@ -92,11 +92,11 @@
if (((CVal << 48) >> 48) == CVal) {
SDValue N0 = Addr.getOperand(0);
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N0))
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i16);
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i16);
else
Base = N0;
- Disp = CurDAG->getTargetConstant(CVal, EVT::i16);
+ Disp = CurDAG->getTargetConstant(CVal, MVT::i16);
return true;
}
}
@@ -105,18 +105,18 @@
SDValue N0 = Addr.getOperand(0);
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
Base = CurDAG->getTargetGlobalAddress(G->getGlobal(),
- EVT::i16, G->getOffset());
- Disp = CurDAG->getTargetConstant(0, EVT::i16);
+ MVT::i16, G->getOffset());
+ Disp = CurDAG->getTargetConstant(0, MVT::i16);
return true;
} else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(N0)) {
- Base = CurDAG->getTargetExternalSymbol(E->getSymbol(), EVT::i16);
- Disp = CurDAG->getTargetConstant(0, EVT::i16);
+ Base = CurDAG->getTargetExternalSymbol(E->getSymbol(), MVT::i16);
+ Disp = CurDAG->getTargetConstant(0, MVT::i16);
}
break;
};
Base = Addr;
- Disp = CurDAG->getTargetConstant(0, EVT::i16);
+ Disp = CurDAG->getTargetConstant(0, MVT::i16);
return true;
}
@@ -168,14 +168,14 @@
switch (Node->getOpcode()) {
default: break;
case ISD::FrameIndex: {
- assert(Op.getValueType() == EVT::i16);
+ assert(Op.getValueType() == MVT::i16);
int FI = cast<FrameIndexSDNode>(Node)->getIndex();
- SDValue TFI = CurDAG->getTargetFrameIndex(FI, EVT::i16);
+ SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i16);
if (Node->hasOneUse())
- return CurDAG->SelectNodeTo(Node, MSP430::ADD16ri, EVT::i16,
- TFI, CurDAG->getTargetConstant(0, EVT::i16));
- return CurDAG->getTargetNode(MSP430::ADD16ri, dl, EVT::i16,
- TFI, CurDAG->getTargetConstant(0, EVT::i16));
+ return CurDAG->SelectNodeTo(Node, MSP430::ADD16ri, MVT::i16,
+ TFI, CurDAG->getTargetConstant(0, MVT::i16));
+ return CurDAG->getTargetNode(MSP430::ADD16ri, dl, MVT::i16,
+ TFI, CurDAG->getTargetConstant(0, MVT::i16));
}
}
Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp Tue Aug 11 15:47:22 2009
@@ -42,8 +42,8 @@
Subtarget(*tm.getSubtargetImpl()), TM(tm) {
// Set up the register classes.
- addRegisterClass(EVT::i8, MSP430::GR8RegisterClass);
- addRegisterClass(EVT::i16, MSP430::GR16RegisterClass);
+ addRegisterClass(MVT::i8, MSP430::GR8RegisterClass);
+ addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
// Compute derived properties from the register classes
computeRegisterProperties();
@@ -55,75 +55,75 @@
// Even if we have only 1 bit shift here, we can perform
// shifts of the whole bitwidth 1 bit per step.
- setShiftAmountType(EVT::i8);
+ setShiftAmountType(MVT::i8);
setStackPointerRegisterToSaveRestore(MSP430::SPW);
setBooleanContents(ZeroOrOneBooleanContent);
setSchedulingPreference(SchedulingForLatency);
- setLoadExtAction(ISD::EXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::SEXTLOAD, EVT::i8, Expand);
- setLoadExtAction(ISD::SEXTLOAD, EVT::i16, Expand);
+ setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
// We don't have any truncstores
- setTruncStoreAction(EVT::i16, EVT::i8, Expand);
+ setTruncStoreAction(MVT::i16, MVT::i8, Expand);
- setOperationAction(ISD::SRA, EVT::i8, Custom);
- setOperationAction(ISD::SHL, EVT::i8, Custom);
- setOperationAction(ISD::SRL, EVT::i8, Custom);
- setOperationAction(ISD::SRA, EVT::i16, Custom);
- setOperationAction(ISD::SHL, EVT::i16, Custom);
- setOperationAction(ISD::SRL, EVT::i16, Custom);
- setOperationAction(ISD::ROTL, EVT::i8, Expand);
- setOperationAction(ISD::ROTR, EVT::i8, Expand);
- setOperationAction(ISD::ROTL, EVT::i16, Expand);
- setOperationAction(ISD::ROTR, EVT::i16, Expand);
- setOperationAction(ISD::GlobalAddress, EVT::i16, Custom);
- setOperationAction(ISD::ExternalSymbol, EVT::i16, Custom);
- setOperationAction(ISD::BR_JT, EVT::Other, Expand);
- setOperationAction(ISD::BRIND, EVT::Other, Expand);
- setOperationAction(ISD::BR_CC, EVT::i8, Custom);
- setOperationAction(ISD::BR_CC, EVT::i16, Custom);
- setOperationAction(ISD::BRCOND, EVT::Other, Expand);
- setOperationAction(ISD::SETCC, EVT::i8, Expand);
- setOperationAction(ISD::SETCC, EVT::i16, Expand);
- setOperationAction(ISD::SELECT, EVT::i8, Expand);
- setOperationAction(ISD::SELECT, EVT::i16, Expand);
- setOperationAction(ISD::SELECT_CC, EVT::i8, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::i16, Custom);
- setOperationAction(ISD::SIGN_EXTEND, EVT::i16, Custom);
-
- setOperationAction(ISD::CTTZ, EVT::i8, Expand);
- setOperationAction(ISD::CTTZ, EVT::i16, Expand);
- setOperationAction(ISD::CTLZ, EVT::i8, Expand);
- setOperationAction(ISD::CTLZ, EVT::i16, Expand);
- setOperationAction(ISD::CTPOP, EVT::i8, Expand);
- setOperationAction(ISD::CTPOP, EVT::i16, Expand);
-
- setOperationAction(ISD::SHL_PARTS, EVT::i8, Expand);
- setOperationAction(ISD::SHL_PARTS, EVT::i16, Expand);
- setOperationAction(ISD::SRL_PARTS, EVT::i8, Expand);
- setOperationAction(ISD::SRL_PARTS, EVT::i16, Expand);
- setOperationAction(ISD::SRA_PARTS, EVT::i8, Expand);
- setOperationAction(ISD::SRA_PARTS, EVT::i16, Expand);
+ setOperationAction(ISD::SRA, MVT::i8, Custom);
+ setOperationAction(ISD::SHL, MVT::i8, Custom);
+ setOperationAction(ISD::SRL, MVT::i8, Custom);
+ setOperationAction(ISD::SRA, MVT::i16, Custom);
+ setOperationAction(ISD::SHL, MVT::i16, Custom);
+ setOperationAction(ISD::SRL, MVT::i16, Custom);
+ setOperationAction(ISD::ROTL, MVT::i8, Expand);
+ setOperationAction(ISD::ROTR, MVT::i8, Expand);
+ setOperationAction(ISD::ROTL, MVT::i16, Expand);
+ setOperationAction(ISD::ROTR, MVT::i16, Expand);
+ setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
+ setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
+ setOperationAction(ISD::BR_JT, MVT::Other, Expand);
+ setOperationAction(ISD::BRIND, MVT::Other, Expand);
+ setOperationAction(ISD::BR_CC, MVT::i8, Custom);
+ setOperationAction(ISD::BR_CC, MVT::i16, Custom);
+ setOperationAction(ISD::BRCOND, MVT::Other, Expand);
+ setOperationAction(ISD::SETCC, MVT::i8, Expand);
+ setOperationAction(ISD::SETCC, MVT::i16, Expand);
+ setOperationAction(ISD::SELECT, MVT::i8, Expand);
+ setOperationAction(ISD::SELECT, MVT::i16, Expand);
+ setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
+ setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom);
+
+ setOperationAction(ISD::CTTZ, MVT::i8, Expand);
+ setOperationAction(ISD::CTTZ, MVT::i16, Expand);
+ setOperationAction(ISD::CTLZ, MVT::i8, Expand);
+ setOperationAction(ISD::CTLZ, MVT::i16, Expand);
+ setOperationAction(ISD::CTPOP, MVT::i8, Expand);
+ setOperationAction(ISD::CTPOP, MVT::i16, Expand);
+
+ setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
+ setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
+ setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
+ setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
+ setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
+ setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
// FIXME: Implement efficiently multiplication by a constant
- setOperationAction(ISD::MUL, EVT::i16, Expand);
- setOperationAction(ISD::MULHS, EVT::i16, Expand);
- setOperationAction(ISD::MULHU, EVT::i16, Expand);
- setOperationAction(ISD::SMUL_LOHI, EVT::i16, Expand);
- setOperationAction(ISD::UMUL_LOHI, EVT::i16, Expand);
-
- setOperationAction(ISD::UDIV, EVT::i16, Expand);
- setOperationAction(ISD::UDIVREM, EVT::i16, Expand);
- setOperationAction(ISD::UREM, EVT::i16, Expand);
- setOperationAction(ISD::SDIV, EVT::i16, Expand);
- setOperationAction(ISD::SDIVREM, EVT::i16, Expand);
- setOperationAction(ISD::SREM, EVT::i16, Expand);
+ setOperationAction(ISD::MUL, MVT::i16, Expand);
+ setOperationAction(ISD::MULHS, MVT::i16, Expand);
+ setOperationAction(ISD::MULHU, MVT::i16, Expand);
+ setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
+ setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
+
+ setOperationAction(ISD::UDIV, MVT::i16, Expand);
+ setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
+ setOperationAction(ISD::UREM, MVT::i16, Expand);
+ setOperationAction(ISD::SDIV, MVT::i16, Expand);
+ setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
+ setOperationAction(ISD::SREM, MVT::i16, Expand);
}
SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
@@ -221,16 +221,16 @@
if (VA.isRegLoc()) {
// Arguments passed in registers
EVT RegVT = VA.getLocVT();
- switch (RegVT.getSimpleVT()) {
+ switch (RegVT.getSimpleVT().SimpleTy) {
default:
{
#ifndef NDEBUG
cerr << "LowerFormalArguments Unhandled argument type: "
- << RegVT.getSimpleVT() << "\n";
+ << RegVT.getSimpleVT().SimpleTy << "\n";
#endif
llvm_unreachable(0);
}
- case EVT::i16:
+ case MVT::i16:
unsigned VReg =
RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg);
@@ -258,7 +258,7 @@
unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
if (ObjSize > 2) {
cerr << "LowerFormalArguments Unhandled argument type: "
- << VA.getLocVT().getSimpleVT()
+ << VA.getLocVT().getSimpleVT().SimpleTy
<< "\n";
}
// Create the frame index object for this incoming parameter...
@@ -266,7 +266,7 @@
// Create the SelectionDAG nodes corresponding to a load
//from this parameter
- SDValue FIN = DAG.getFrameIndex(FI, EVT::i16);
+ SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
PseudoSourceValue::getFixedStack(FI), 0));
}
@@ -315,10 +315,10 @@
}
if (Flag.getNode())
- return DAG.getNode(MSP430ISD::RET_FLAG, dl, EVT::Other, Chain, Flag);
+ return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
// Return Void
- return DAG.getNode(MSP430ISD::RET_FLAG, dl, EVT::Other, Chain);
+ return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain);
}
/// LowerCCCCallTo - functions arguments are copied from virtual regs to
@@ -395,7 +395,7 @@
// Transform all store nodes into one single node because all store nodes are
// independent of each other.
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token chain and
@@ -412,12 +412,12 @@
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
// Likewise ExternalSymbol -> TargetExternalSymbol.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
- Callee = DAG.getTargetGlobalAddress(G->getGlobal(), EVT::i16);
+ Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16);
else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
- Callee = DAG.getTargetExternalSymbol(E->getSymbol(), EVT::i16);
+ Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
// Returns a chain & a flag for retval copy to use.
- SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
@@ -564,7 +564,7 @@
break;
}
- return DAG.getNode(MSP430ISD::CMP, dl, EVT::Flag, LHS, RHS);
+ return DAG.getNode(MSP430ISD::CMP, dl, MVT::Flag, LHS, RHS);
}
@@ -581,7 +581,7 @@
return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
Chain,
- Dest, DAG.getConstant(TargetCC, EVT::i8),
+ Dest, DAG.getConstant(TargetCC, MVT::i8),
Flag);
}
@@ -596,11 +596,11 @@
unsigned TargetCC = MSP430::COND_INVALID;
SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
- SDVTList VTs = DAG.getVTList(Op.getValueType(), EVT::Flag);
+ SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
SmallVector<SDValue, 4> Ops;
Ops.push_back(TrueV);
Ops.push_back(FalseV);
- Ops.push_back(DAG.getConstant(TargetCC, EVT::i8));
+ Ops.push_back(DAG.getConstant(TargetCC, MVT::i8));
Ops.push_back(Flag);
return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
@@ -612,7 +612,7 @@
EVT VT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
- assert(VT == EVT::i16 && "Only support i16 for now!");
+ assert(VT == MVT::i16 && "Only support i16 for now!");
return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Tue Aug 11 15:47:22 2009
@@ -95,7 +95,7 @@
// getI32Imm - Return a target constant with the specified
// value, of type i32.
inline SDValue getI32Imm(unsigned Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i32);
+ return CurDAG->getTargetConstant(Imm, MVT::i32);
}
@@ -142,8 +142,8 @@
{
// if Address is FI, get the TargetFrameIndex.
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i32);
- Offset = CurDAG->getTargetConstant(0, EVT::i32);
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
+ Offset = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
@@ -151,7 +151,7 @@
if (TM.getRelocationModel() == Reloc::PIC_) {
if ((Addr.getOpcode() == ISD::TargetGlobalAddress) ||
(Addr.getOpcode() == ISD::TargetJumpTable)){
- Base = CurDAG->getRegister(Mips::GP, EVT::i32);
+ Base = CurDAG->getRegister(Mips::GP, MVT::i32);
Offset = Addr;
return true;
}
@@ -169,19 +169,19 @@
// If the first operand is a FI, get the TargetFI Node
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
(Addr.getOperand(0))) {
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i32);
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
} else {
Base = Addr.getOperand(0);
}
- Offset = CurDAG->getTargetConstant(CN->getZExtValue(), EVT::i32);
+ Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
return true;
}
}
}
Base = Addr;
- Offset = CurDAG->getTargetConstant(0, EVT::i32);
+ Offset = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
@@ -248,7 +248,7 @@
SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, dl, VT,
SDValue(Carry,0), RHS);
- return CurDAG->SelectNodeTo(N.getNode(), MOp, VT, EVT::Flag,
+ return CurDAG->SelectNodeTo(N.getNode(), MOp, VT, MVT::Flag,
LHS, SDValue(AddCarry,0));
}
@@ -266,13 +266,13 @@
else
Op = (Opcode == ISD::UDIVREM ? Mips::DIVu : Mips::DIV);
- SDNode *Node = CurDAG->getTargetNode(Op, dl, EVT::Flag, Op1, Op2);
+ SDNode *Node = CurDAG->getTargetNode(Op, dl, MVT::Flag, Op1, Op2);
SDValue InFlag = SDValue(Node, 0);
- SDNode *Lo = CurDAG->getTargetNode(Mips::MFLO, dl, EVT::i32,
- EVT::Flag, InFlag);
+ SDNode *Lo = CurDAG->getTargetNode(Mips::MFLO, dl, MVT::i32,
+ MVT::Flag, InFlag);
InFlag = SDValue(Lo,1);
- SDNode *Hi = CurDAG->getTargetNode(Mips::MFHI, dl, EVT::i32, InFlag);
+ SDNode *Hi = CurDAG->getTargetNode(Mips::MFHI, dl, MVT::i32, InFlag);
if (!N.getValue(0).use_empty())
ReplaceUses(N.getValue(0), SDValue(Lo,0));
@@ -292,14 +292,14 @@
unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
SDNode *MulNode = CurDAG->getTargetNode(MulOp, dl,
- EVT::Flag, MulOp1, MulOp2);
+ MVT::Flag, MulOp1, MulOp2);
SDValue InFlag = SDValue(MulNode, 0);
if (MulOp == ISD::MUL)
- return CurDAG->getTargetNode(Mips::MFLO, dl, EVT::i32, InFlag);
+ return CurDAG->getTargetNode(Mips::MFLO, dl, MVT::i32, InFlag);
else
- return CurDAG->getTargetNode(Mips::MFHI, dl, EVT::i32, InFlag);
+ return CurDAG->getTargetNode(Mips::MFHI, dl, MVT::i32, InFlag);
}
/// Div/Rem operations
@@ -318,10 +318,10 @@
Op = (Opcode == ISD::SREM ? Mips::DIV : Mips::DIVu);
MOp = Mips::MFHI;
}
- SDNode *Node = CurDAG->getTargetNode(Op, dl, EVT::Flag, Op1, Op2);
+ SDNode *Node = CurDAG->getTargetNode(Op, dl, MVT::Flag, Op1, Op2);
SDValue InFlag = SDValue(Node, 0);
- return CurDAG->getTargetNode(MOp, dl, EVT::i32, InFlag);
+ return CurDAG->getTargetNode(MOp, dl, MVT::i32, InFlag);
}
// Get target GOT address.
@@ -337,19 +337,19 @@
//bool isCodeLarge = (TM.getCodeModel() == CodeModel::Large);
SDValue Chain = Node->getOperand(0);
SDValue Callee = Node->getOperand(1);
- SDValue T9Reg = CurDAG->getRegister(Mips::T9, EVT::i32);
+ SDValue T9Reg = CurDAG->getRegister(Mips::T9, MVT::i32);
SDValue InFlag(0, 0);
if ( (isa<GlobalAddressSDNode>(Callee)) ||
(isa<ExternalSymbolSDNode>(Callee)) )
{
/// Direct call for global addresses and external symbols
- SDValue GPReg = CurDAG->getRegister(Mips::GP, EVT::i32);
+ SDValue GPReg = CurDAG->getRegister(Mips::GP, MVT::i32);
// Use load to get GOT target
SDValue Ops[] = { Callee, GPReg, Chain };
- SDValue Load = SDValue(CurDAG->getTargetNode(Mips::LW, dl, EVT::i32,
- EVT::Other, Ops, 3), 0);
+ SDValue Load = SDValue(CurDAG->getTargetNode(Mips::LW, dl, MVT::i32,
+ MVT::Other, Ops, 3), 0);
Chain = Load.getValue(1);
// Call target must be on T9
@@ -359,8 +359,8 @@
Chain = CurDAG->getCopyToReg(Chain, dl, T9Reg, Callee, InFlag);
// Emit Jump and Link Register
- SDNode *ResNode = CurDAG->getTargetNode(Mips::JALR, dl, EVT::Other,
- EVT::Flag, T9Reg, Chain);
+ SDNode *ResNode = CurDAG->getTargetNode(Mips::JALR, dl, MVT::Other,
+ MVT::Flag, T9Reg, Chain);
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
ReplaceUses(SDValue(Node, 0), Chain);
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Aug 11 15:47:22 2009
@@ -65,108 +65,108 @@
setUsesGlobalOffsetTable(true);
// Set up the register classes
- addRegisterClass(EVT::i32, Mips::CPURegsRegisterClass);
- addRegisterClass(EVT::f32, Mips::FGR32RegisterClass);
+ addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
+ addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
// When dealing with single precision only, use libcalls
if (!Subtarget->isSingleFloat())
if (!Subtarget->isFP64bit())
- addRegisterClass(EVT::f64, Mips::AFGR64RegisterClass);
+ addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
// Legal fp constants
addLegalFPImmediate(APFloat(+0.0f));
// Load extented operations for i1 types must be promoted
- setLoadExtAction(ISD::EXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
+ setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
// MIPS doesn't have extending float->double load/store
- setLoadExtAction(ISD::EXTLOAD, EVT::f32, Expand);
- setTruncStoreAction(EVT::f64, EVT::f32, Expand);
+ setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
+ setTruncStoreAction(MVT::f64, MVT::f32, Expand);
// Used by legalize types to correctly generate the setcc result.
// Without this, every float setcc comes with a AND/OR with the result,
// we don't want this, since the fpcmp result goes to a flag register,
// which is used implicitly by brcond and select operations.
- AddPromotedToType(ISD::SETCC, EVT::i1, EVT::i32);
+ AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
// Mips Custom Operations
- setOperationAction(ISD::GlobalAddress, EVT::i32, Custom);
- setOperationAction(ISD::GlobalTLSAddress, EVT::i32, Custom);
- setOperationAction(ISD::JumpTable, EVT::i32, Custom);
- setOperationAction(ISD::ConstantPool, EVT::i32, Custom);
- setOperationAction(ISD::SELECT, EVT::f32, Custom);
- setOperationAction(ISD::SELECT, EVT::f64, Custom);
- setOperationAction(ISD::SELECT, EVT::i32, Custom);
- setOperationAction(ISD::SETCC, EVT::f32, Custom);
- setOperationAction(ISD::SETCC, EVT::f64, Custom);
- setOperationAction(ISD::BRCOND, EVT::Other, Custom);
- setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32, Custom);
- setOperationAction(ISD::FP_TO_SINT, EVT::i32, Custom);
+ setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
+ setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
+ setOperationAction(ISD::JumpTable, MVT::i32, Custom);
+ setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
+ setOperationAction(ISD::SELECT, MVT::f32, Custom);
+ setOperationAction(ISD::SELECT, MVT::f64, Custom);
+ setOperationAction(ISD::SELECT, MVT::i32, Custom);
+ setOperationAction(ISD::SETCC, MVT::f32, Custom);
+ setOperationAction(ISD::SETCC, MVT::f64, Custom);
+ setOperationAction(ISD::BRCOND, MVT::Other, Custom);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
+ setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
// We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
// with operands comming from setcc fp comparions. This is necessary since
// the result from these setcc are in a flag registers (FCR31).
- setOperationAction(ISD::AND, EVT::i32, Custom);
- setOperationAction(ISD::OR, EVT::i32, Custom);
+ setOperationAction(ISD::AND, MVT::i32, Custom);
+ setOperationAction(ISD::OR, MVT::i32, Custom);
// Operations not directly supported by Mips.
- setOperationAction(ISD::BR_JT, EVT::Other, Expand);
- setOperationAction(ISD::BR_CC, EVT::Other, Expand);
- setOperationAction(ISD::SELECT_CC, EVT::Other, Expand);
- setOperationAction(ISD::UINT_TO_FP, EVT::i32, Expand);
- setOperationAction(ISD::FP_TO_UINT, EVT::i32, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand);
- setOperationAction(ISD::CTPOP, EVT::i32, Expand);
- setOperationAction(ISD::CTTZ, EVT::i32, Expand);
- setOperationAction(ISD::ROTL, EVT::i32, Expand);
- setOperationAction(ISD::ROTR, EVT::i32, Expand);
- setOperationAction(ISD::SHL_PARTS, EVT::i32, Expand);
- setOperationAction(ISD::SRA_PARTS, EVT::i32, Expand);
- setOperationAction(ISD::SRL_PARTS, EVT::i32, Expand);
- setOperationAction(ISD::FCOPYSIGN, EVT::f32, Expand);
- setOperationAction(ISD::FCOPYSIGN, EVT::f64, Expand);
- setOperationAction(ISD::FSIN, EVT::f32, Expand);
- setOperationAction(ISD::FCOS, EVT::f32, Expand);
- setOperationAction(ISD::FPOWI, EVT::f32, Expand);
- setOperationAction(ISD::FPOW, EVT::f32, Expand);
- setOperationAction(ISD::FLOG, EVT::f32, Expand);
- setOperationAction(ISD::FLOG2, EVT::f32, Expand);
- setOperationAction(ISD::FLOG10, EVT::f32, Expand);
- setOperationAction(ISD::FEXP, EVT::f32, Expand);
+ setOperationAction(ISD::BR_JT, MVT::Other, Expand);
+ setOperationAction(ISD::BR_CC, MVT::Other, Expand);
+ setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
+ setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
+ setOperationAction(ISD::CTPOP, MVT::i32, Expand);
+ setOperationAction(ISD::CTTZ, MVT::i32, Expand);
+ setOperationAction(ISD::ROTL, MVT::i32, Expand);
+ setOperationAction(ISD::ROTR, MVT::i32, Expand);
+ setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
+ setOperationAction(ISD::FSIN, MVT::f32, Expand);
+ setOperationAction(ISD::FCOS, MVT::f32, Expand);
+ setOperationAction(ISD::FPOWI, MVT::f32, Expand);
+ setOperationAction(ISD::FPOW, MVT::f32, Expand);
+ setOperationAction(ISD::FLOG, MVT::f32, Expand);
+ setOperationAction(ISD::FLOG2, MVT::f32, Expand);
+ setOperationAction(ISD::FLOG10, MVT::f32, Expand);
+ setOperationAction(ISD::FEXP, MVT::f32, Expand);
// We don't have line number support yet.
- setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand);
- setOperationAction(ISD::DBG_LABEL, EVT::Other, Expand);
- setOperationAction(ISD::EH_LABEL, EVT::Other, Expand);
+ setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
+ setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
// Use the default for now
- setOperationAction(ISD::STACKSAVE, EVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE, EVT::Other, Expand);
- setOperationAction(ISD::MEMBARRIER, EVT::Other, Expand);
+ setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
+ setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
if (Subtarget->isSingleFloat())
- setOperationAction(ISD::SELECT_CC, EVT::f64, Expand);
+ setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
if (!Subtarget->hasSEInReg()) {
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i8, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i16, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
}
if (!Subtarget->hasBitCount())
- setOperationAction(ISD::CTLZ, EVT::i32, Expand);
+ setOperationAction(ISD::CTLZ, MVT::i32, Expand);
if (!Subtarget->hasSwap())
- setOperationAction(ISD::BSWAP, EVT::i32, Expand);
+ setOperationAction(ISD::BSWAP, MVT::i32, Expand);
setStackPointerRegisterToSaveRestore(Mips::SP);
computeRegisterProperties();
}
-EVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {
- return EVT::i32;
+MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {
+ return MVT::i32;
}
/// getFunctionAlignment - Return the Log2 alignment of this function.
@@ -358,22 +358,22 @@
SDValue Src = Op.getOperand(0);
// Set the condition register
- SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, EVT::i32);
+ SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32);
CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg);
- CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, EVT::i32);
+ CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32);
- SDValue Cst = DAG.getConstant(3, EVT::i32);
- SDValue Or = DAG.getNode(ISD::OR, dl, EVT::i32, CondReg, Cst);
- Cst = DAG.getConstant(2, EVT::i32);
- SDValue Xor = DAG.getNode(ISD::XOR, dl, EVT::i32, Or, Cst);
+ SDValue Cst = DAG.getConstant(3, MVT::i32);
+ SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst);
+ Cst = DAG.getConstant(2, MVT::i32);
+ SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst);
SDValue InFlag(0, 0);
CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag);
// Emit the round instruction and bit convert to integer
- SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, EVT::f32,
+ SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32,
Src, CondReg.getValue(1));
- SDValue BitCvt = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Trunc);
+ SDValue BitCvt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Trunc);
return BitCvt;
}
@@ -385,11 +385,11 @@
DebugLoc dl = Op.getDebugLoc();
// Get a reference from Mips stack pointer
- SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, EVT::i32);
+ SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
// Subtract the dynamic size from the actual stack size to
// obtain the new stack size.
- SDValue Sub = DAG.getNode(ISD::SUB, dl, EVT::i32, StackPointer, Size);
+ SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
// The Sub result contains the new stack start address, so it
// must be placed in the stack pointer register.
@@ -411,15 +411,15 @@
if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
return Op;
- SDValue True = DAG.getConstant(1, EVT::i32);
- SDValue False = DAG.getConstant(0, EVT::i32);
+ SDValue True = DAG.getConstant(1, MVT::i32);
+ SDValue False = DAG.getConstant(0, MVT::i32);
SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
LHS, True, False, LHS.getOperand(2));
SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
RHS, True, False, RHS.getOperand(2));
- return DAG.getNode(Op.getOpcode(), dl, EVT::i32, LSEL, RSEL);
+ return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL);
}
SDValue MipsTargetLowering::
@@ -438,7 +438,7 @@
SDValue CCNode = CondRes.getOperand(2);
Mips::CondCode CC =
(Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
- SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), EVT::i32);
+ SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
Dest, CondRes);
@@ -457,7 +457,7 @@
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS,
- DAG.getConstant(FPCondCCodeToFCC(CC), EVT::i32));
+ DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
}
SDValue MipsTargetLowering::
@@ -491,23 +491,23 @@
// FIXME there isn't actually debug info here
DebugLoc dl = Op.getDebugLoc();
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
- SDValue GA = DAG.getTargetGlobalAddress(GV, EVT::i32);
+ SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
// %hi/%lo relocation
- SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, EVT::i32, GA);
- SDValue Lo = DAG.getNode(MipsISD::Lo, dl, EVT::i32, GA);
- return DAG.getNode(ISD::ADD, dl, EVT::i32, HiPart, Lo);
+ SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, GA);
+ SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
+ return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
} else { // Abicall relocations, TODO: make this cleaner.
- SDValue ResNode = DAG.getLoad(EVT::i32, dl,
+ SDValue ResNode = DAG.getLoad(MVT::i32, dl,
DAG.getEntryNode(), GA, NULL, 0);
// On functions and global targets not internal linked only
// a load from got/GP is necessary for PIC to work.
if (!GV->hasLocalLinkage() || isa<Function>(GV))
return ResNode;
- SDValue Lo = DAG.getNode(MipsISD::Lo, dl, EVT::i32, GA);
- return DAG.getNode(ISD::ADD, dl, EVT::i32, ResNode, Lo);
+ SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
+ return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
}
llvm_unreachable("Dont know how to handle GlobalAddress");
@@ -534,14 +534,14 @@
SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
- SDVTList VTs = DAG.getVTList(EVT::i32);
+ SDVTList VTs = DAG.getVTList(MVT::i32);
SDValue Ops[] = { JTI };
HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, Ops, 1);
} else // Emit Load from Global Pointer
- HiPart = DAG.getLoad(EVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0);
+ HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0);
- SDValue Lo = DAG.getNode(MipsISD::Lo, dl, EVT::i32, JTI);
- ResNode = DAG.getNode(ISD::ADD, dl, EVT::i32, HiPart, Lo);
+ SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI);
+ ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
return ResNode;
}
@@ -552,7 +552,7 @@
SDValue ResNode;
ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
Constant *C = N->getConstVal();
- SDValue CP = DAG.getTargetConstantPool(C, EVT::i32, N->getAlignment());
+ SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
// FIXME there isn't actually debug info here
DebugLoc dl = Op.getDebugLoc();
@@ -562,13 +562,13 @@
// hacking it. This feature should come soon so we can uncomment the
// stuff below.
//if (IsInSmallSection(C->getType())) {
- // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, EVT::i32, CP);
- // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(EVT::i32);
- // ResNode = DAG.getNode(ISD::ADD, EVT::i32, GOT, GPRelNode);
+ // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
+ // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
+ // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
//} else { // %hi/%lo relocation
- SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, EVT::i32, CP);
- SDValue Lo = DAG.getNode(MipsISD::Lo, dl, EVT::i32, CP);
- ResNode = DAG.getNode(ISD::ADD, dl, EVT::i32, HiPart, Lo);
+ SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP);
+ SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
+ ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
//}
return ResNode;
@@ -614,8 +614,8 @@
bool IntRegUsed = (IntRegs[UnallocIntReg] != (unsigned (Mips::A0)));
// Promote i8 and i16
- if (LocVT == EVT::i8 || LocVT == EVT::i16) {
- LocVT = EVT::i32;
+ if (LocVT == MVT::i8 || LocVT == MVT::i16) {
+ LocVT = MVT::i32;
if (ArgFlags.isSExt())
LocInfo = CCValAssign::SExt;
else if (ArgFlags.isZExt())
@@ -624,20 +624,20 @@
LocInfo = CCValAssign::AExt;
}
- if (ValVT == EVT::i32 || (ValVT == EVT::f32 && IntRegUsed)) {
+ if (ValVT == MVT::i32 || (ValVT == MVT::f32 && IntRegUsed)) {
Reg = State.AllocateReg(IntRegs, IntRegsSize);
IntRegUsed = true;
- LocVT = EVT::i32;
+ LocVT = MVT::i32;
}
if (ValVT.isFloatingPoint() && !IntRegUsed) {
- if (ValVT == EVT::f32)
+ if (ValVT == MVT::f32)
Reg = State.AllocateReg(F32Regs, FloatRegsSize);
else
Reg = State.AllocateReg(F64Regs, FloatRegsSize);
}
- if (ValVT == EVT::f64 && IntRegUsed) {
+ if (ValVT == MVT::f64 && IntRegUsed) {
if (UnallocIntReg != IntRegsSize) {
// If we hit register A3 as the first not allocated, we must
// mark it as allocated (shadow) and use the stack instead.
@@ -646,7 +646,7 @@
for (;UnallocIntReg < IntRegsSize; ++UnallocIntReg)
State.AllocateReg(UnallocIntReg);
}
- LocVT = EVT::i32;
+ LocVT = MVT::i32;
}
if (!Reg) {
@@ -686,7 +686,7 @@
// To meet O32 ABI, Mips must always allocate 16 bytes on
// the stack (even if less than 4 are used as arguments)
if (Subtarget->isABI_O32()) {
- int VTsize = EVT(EVT::i32).getSizeInBits()/8;
+ int VTsize = EVT(MVT::i32).getSizeInBits()/8;
MFI->CreateFixedObject(VTsize, (VTsize*3));
CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
} else
@@ -715,13 +715,13 @@
default: llvm_unreachable("Unknown loc info!");
case CCValAssign::Full:
if (Subtarget->isABI_O32() && VA.isRegLoc()) {
- if (VA.getValVT() == EVT::f32 && VA.getLocVT() == EVT::i32)
- Arg = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Arg);
- if (VA.getValVT() == EVT::f64 && VA.getLocVT() == EVT::i32) {
- Arg = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i64, Arg);
- SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Arg,
+ if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
+ Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Arg);
+ if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
+ Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
+ SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
DAG.getConstant(0, getPointerTy()));
- SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Arg,
+ SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
DAG.getConstant(1, getPointerTy()));
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
@@ -768,7 +768,7 @@
// Transform all store nodes into one single node because all store
// nodes are independent of each other.
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token
@@ -794,7 +794,7 @@
// = Chain, Callee, Reg#1, Reg#2, ...
//
// Returns a chain & a flag for retval copy to use.
- SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
@@ -838,9 +838,9 @@
// Reload GP value.
FI = MipsFI->getGPFI();
SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
- SDValue GPLoad = DAG.getLoad(EVT::i32, dl, Chain, FIN, NULL, 0);
+ SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN, NULL, 0);
Chain = GPLoad.getValue(1);
- Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, EVT::i32),
+ Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32),
GPLoad, SDValue(0,0));
InFlag = Chain.getValue(1);
}
@@ -922,11 +922,11 @@
EVT RegVT = VA.getLocVT();
TargetRegisterClass *RC = 0;
- if (RegVT == EVT::i32)
+ if (RegVT == MVT::i32)
RC = Mips::CPURegsRegisterClass;
- else if (RegVT == EVT::f32)
+ else if (RegVT == MVT::f32)
RC = Mips::FGR32RegisterClass;
- else if (RegVT == EVT::f64) {
+ else if (RegVT == MVT::f64) {
if (!Subtarget->isSingleFloat())
RC = Mips::AFGR64RegisterClass;
} else
@@ -954,15 +954,15 @@
// Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
if (Subtarget->isABI_O32()) {
- if (RegVT == EVT::i32 && VA.getValVT() == EVT::f32)
- ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, ArgValue);
- if (RegVT == EVT::i32 && VA.getValVT() == EVT::f64) {
+ if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
+ ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
+ if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
VA.getLocReg()+1, RC);
SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
- SDValue Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, ArgValue);
- SDValue Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, ArgValue2);
- ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, EVT::f64, Lo, Hi);
+ SDValue Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
+ SDValue Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue2);
+ ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::f64, Lo, Hi);
}
}
@@ -1021,11 +1021,11 @@
if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
unsigned Reg = MipsFI->getSRetReturnReg();
if (!Reg) {
- Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(EVT::i32));
+ Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
MipsFI->setSRetReturnReg(Reg);
}
SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Copy, Chain);
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
}
return Chain;
@@ -1094,11 +1094,11 @@
// Return on Mips is always a "jr $ra"
if (Flag.getNode())
- return DAG.getNode(MipsISD::Ret, dl, EVT::Other,
- Chain, DAG.getRegister(Mips::RA, EVT::i32), Flag);
+ return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
+ Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
else // Return Void
- return DAG.getNode(MipsISD::Ret, dl, EVT::Other,
- Chain, DAG.getRegister(Mips::RA, EVT::i32));
+ return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
+ Chain, DAG.getRegister(Mips::RA, MVT::i32));
}
//===----------------------------------------------------------------------===//
@@ -1142,9 +1142,9 @@
case 'r':
return std::make_pair(0U, Mips::CPURegsRegisterClass);
case 'f':
- if (VT == EVT::f32)
+ if (VT == MVT::f32)
return std::make_pair(0U, Mips::FGR32RegisterClass);
- if (VT == EVT::f64)
+ if (VT == MVT::f64)
if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
return std::make_pair(0U, Mips::AFGR64RegisterClass);
}
@@ -1174,7 +1174,7 @@
Mips::T8, 0);
case 'f':
- if (VT == EVT::f32) {
+ if (VT == MVT::f32) {
if (Subtarget->isSingleFloat())
return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
@@ -1187,7 +1187,7 @@
Mips::F28, Mips::F30, 0);
}
- if (VT == EVT::f64)
+ if (VT == MVT::f64)
if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Tue Aug 11 15:47:22 2009
@@ -80,7 +80,7 @@
virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - get the ISD::SETCC result ValueType
- EVT::SimpleValueType getSetCCResultType(EVT VT) const;
+ MVT::SimpleValueType getSetCCResultType(EVT VT) const;
/// getFunctionAlignment - Return the Log2 alignment of this function.
virtual unsigned getFunctionAlignment(const Function *F) const;
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Aug 11 15:47:22 2009
@@ -96,7 +96,7 @@
// Node immediate fits as 16-bit sign extended on target immediate.
// e.g. addi, andi
def immSExt16 : PatLeaf<(imm), [{
- if (N->getValueType(0) == EVT::i32)
+ if (N->getValueType(0) == MVT::i32)
return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
else
return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
@@ -107,7 +107,7 @@
// immediate are caught.
// e.g. addiu, sltiu
def immZExt16 : PatLeaf<(imm), [{
- if (N->getValueType(0) == EVT::i32)
+ if (N->getValueType(0) == MVT::i32)
return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
else
return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Tue Aug 11 15:47:22 2009
@@ -147,9 +147,9 @@
Subtarget = &TM.getSubtarget<PIC16Subtarget>();
- addRegisterClass(EVT::i8, PIC16::GPRRegisterClass);
+ addRegisterClass(MVT::i8, PIC16::GPRRegisterClass);
- setShiftAmountType(EVT::i8);
+ setShiftAmountType(MVT::i8);
// Std lib call names
setLibcallName(RTLIB::COS_F32, getStdLibCallName(RTLIB::COS_F32));
@@ -243,65 +243,65 @@
setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
- setOperationAction(ISD::GlobalAddress, EVT::i16, Custom);
- setOperationAction(ISD::ExternalSymbol, EVT::i16, Custom);
+ setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
+ setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
- setOperationAction(ISD::LOAD, EVT::i8, Legal);
- setOperationAction(ISD::LOAD, EVT::i16, Custom);
- setOperationAction(ISD::LOAD, EVT::i32, Custom);
-
- setOperationAction(ISD::STORE, EVT::i8, Legal);
- setOperationAction(ISD::STORE, EVT::i16, Custom);
- setOperationAction(ISD::STORE, EVT::i32, Custom);
- setOperationAction(ISD::STORE, EVT::i64, Custom);
-
- setOperationAction(ISD::ADDE, EVT::i8, Custom);
- setOperationAction(ISD::ADDC, EVT::i8, Custom);
- setOperationAction(ISD::SUBE, EVT::i8, Custom);
- setOperationAction(ISD::SUBC, EVT::i8, Custom);
- setOperationAction(ISD::SUB, EVT::i8, Custom);
- setOperationAction(ISD::ADD, EVT::i8, Custom);
- setOperationAction(ISD::ADD, EVT::i16, Custom);
-
- setOperationAction(ISD::OR, EVT::i8, Custom);
- setOperationAction(ISD::AND, EVT::i8, Custom);
- setOperationAction(ISD::XOR, EVT::i8, Custom);
-
- setOperationAction(ISD::FrameIndex, EVT::i16, Custom);
-
- setOperationAction(ISD::MUL, EVT::i8, Custom);
-
- setOperationAction(ISD::SMUL_LOHI, EVT::i8, Expand);
- setOperationAction(ISD::UMUL_LOHI, EVT::i8, Expand);
- setOperationAction(ISD::MULHU, EVT::i8, Expand);
- setOperationAction(ISD::MULHS, EVT::i8, Expand);
-
- setOperationAction(ISD::SRA, EVT::i8, Custom);
- setOperationAction(ISD::SHL, EVT::i8, Custom);
- setOperationAction(ISD::SRL, EVT::i8, Custom);
+ setOperationAction(ISD::LOAD, MVT::i8, Legal);
+ setOperationAction(ISD::LOAD, MVT::i16, Custom);
+ setOperationAction(ISD::LOAD, MVT::i32, Custom);
+
+ setOperationAction(ISD::STORE, MVT::i8, Legal);
+ setOperationAction(ISD::STORE, MVT::i16, Custom);
+ setOperationAction(ISD::STORE, MVT::i32, Custom);
+ setOperationAction(ISD::STORE, MVT::i64, Custom);
+
+ setOperationAction(ISD::ADDE, MVT::i8, Custom);
+ setOperationAction(ISD::ADDC, MVT::i8, Custom);
+ setOperationAction(ISD::SUBE, MVT::i8, Custom);
+ setOperationAction(ISD::SUBC, MVT::i8, Custom);
+ setOperationAction(ISD::SUB, MVT::i8, Custom);
+ setOperationAction(ISD::ADD, MVT::i8, Custom);
+ setOperationAction(ISD::ADD, MVT::i16, Custom);
+
+ setOperationAction(ISD::OR, MVT::i8, Custom);
+ setOperationAction(ISD::AND, MVT::i8, Custom);
+ setOperationAction(ISD::XOR, MVT::i8, Custom);
+
+ setOperationAction(ISD::FrameIndex, MVT::i16, Custom);
+
+ setOperationAction(ISD::MUL, MVT::i8, Custom);
+
+ setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
+ setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
+ setOperationAction(ISD::MULHU, MVT::i8, Expand);
+ setOperationAction(ISD::MULHS, MVT::i8, Expand);
+
+ setOperationAction(ISD::SRA, MVT::i8, Custom);
+ setOperationAction(ISD::SHL, MVT::i8, Custom);
+ setOperationAction(ISD::SRL, MVT::i8, Custom);
- setOperationAction(ISD::ROTL, EVT::i8, Expand);
- setOperationAction(ISD::ROTR, EVT::i8, Expand);
+ setOperationAction(ISD::ROTL, MVT::i8, Expand);
+ setOperationAction(ISD::ROTR, MVT::i8, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
// PIC16 does not support shift parts
- setOperationAction(ISD::SRA_PARTS, EVT::i8, Expand);
- setOperationAction(ISD::SHL_PARTS, EVT::i8, Expand);
- setOperationAction(ISD::SRL_PARTS, EVT::i8, Expand);
+ setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
+ setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
+ setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
// PIC16 does not have a SETCC, expand it to SELECT_CC.
- setOperationAction(ISD::SETCC, EVT::i8, Expand);
- setOperationAction(ISD::SELECT, EVT::i8, Expand);
- setOperationAction(ISD::BRCOND, EVT::Other, Expand);
- setOperationAction(ISD::BRIND, EVT::Other, Expand);
+ setOperationAction(ISD::SETCC, MVT::i8, Expand);
+ setOperationAction(ISD::SELECT, MVT::i8, Expand);
+ setOperationAction(ISD::BRCOND, MVT::Other, Expand);
+ setOperationAction(ISD::BRIND, MVT::Other, Expand);
- setOperationAction(ISD::SELECT_CC, EVT::i8, Custom);
- setOperationAction(ISD::BR_CC, EVT::i8, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
+ setOperationAction(ISD::BR_CC, MVT::i8, Custom);
- //setOperationAction(ISD::TRUNCATE, EVT::i16, Custom);
- setTruncStoreAction(EVT::i16, EVT::i8, Custom);
+ //setOperationAction(ISD::TRUNCATE, MVT::i16, Custom);
+ setTruncStoreAction(MVT::i16, MVT::i8, Custom);
// Now deduce the information based on the above mentioned
// actions
@@ -313,7 +313,7 @@
// Flag is the last value of the node.
SDValue Flag = Op.getValue(Op.getNode()->getNumValues() - 1);
- assert (Flag.getValueType() == EVT::Flag
+ assert (Flag.getValueType() == MVT::Flag
&& "Node does not have an out Flag");
return Flag;
@@ -340,12 +340,12 @@
// If the last value returned in Flag then the chain is
// second last value returned.
- if (Chain.getValueType() == EVT::Flag)
+ if (Chain.getValueType() == MVT::Flag)
Chain = Op.getValue(Op.getNode()->getNumValues() - 2);
// All nodes may not produce a chain. Therefore following assert
// verifies that the node is returning a chain only.
- assert (Chain.getValueType() == EVT::Other
+ assert (Chain.getValueType() == MVT::Other
&& "Node does not have a chain");
return Chain;
@@ -365,9 +365,9 @@
Results.push_back(N);
}
-EVT::SimpleValueType
+MVT::SimpleValueType
PIC16TargetLowering::getSetCCResultType(EVT ValType) const {
- return EVT::i8;
+ return MVT::i8;
}
/// The type legalizer framework of generating legalizer can generate libcalls
@@ -405,7 +405,7 @@
Args.push_back(Entry);
}
- SDValue Callee = DAG.getExternalSymbol(getPIC16LibcallName(Call), EVT::i16);
+ SDValue Callee = DAG.getExternalSymbol(getPIC16LibcallName(Call), MVT::i16);
const Type *RetTy = RetVT.getTypeForEVT();
std::pair<SDValue,SDValue> CallInfo =
@@ -478,11 +478,11 @@
SDValue PIC16TargetLowering::ExpandFrameIndex(SDNode *N, SelectionDAG &DAG) {
- // Currently handling FrameIndex of size EVT::i16 only
+ // Currently handling FrameIndex of size MVT::i16 only
// One example of this scenario is when return value is written on
// FrameIndex#0
- if (N->getValueType(0) != EVT::i16)
+ if (N->getValueType(0) != MVT::i16)
return SDValue();
// Expand the FrameIndex into ExternalSymbol and a Constant node
@@ -504,9 +504,9 @@
int FrameOffset;
SDValue FI = SDValue(N,0);
LegalizeFrameIndex(FI, DAG, ES, FrameOffset);
- SDValue Offset = DAG.getConstant(FrameOffset, EVT::i8);
- SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, EVT::i8, ES, Offset);
- SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, EVT::i8, ES, Offset);
+ SDValue Offset = DAG.getConstant(FrameOffset, MVT::i8);
+ SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, ES, Offset);
+ SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, ES, Offset);
return DAG.getNode(ISD::BUILD_PAIR, dl, N->getValueType(0), Lo, Hi);
}
@@ -523,12 +523,12 @@
SDValue PtrLo, PtrHi;
LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, StoreOffset, dl);
- if (ValueType == EVT::i8) {
- return DAG.getNode (PIC16ISD::PIC16Store, dl, EVT::Other, Chain, Src,
+ if (ValueType == MVT::i8) {
+ return DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, Src,
PtrLo, PtrHi,
- DAG.getConstant (0 + StoreOffset, EVT::i8));
+ DAG.getConstant (0 + StoreOffset, MVT::i8));
}
- else if (ValueType == EVT::i16) {
+ else if (ValueType == MVT::i16) {
// Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR.
SDValue SrcLo, SrcHi;
GetExpandedParts(Src, DAG, SrcLo, SrcHi);
@@ -537,19 +537,19 @@
ChainLo = Chain.getOperand(0);
ChainHi = Chain.getOperand(1);
}
- SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, EVT::Other,
+ SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other,
ChainLo,
SrcLo, PtrLo, PtrHi,
- DAG.getConstant (0 + StoreOffset, EVT::i8));
+ DAG.getConstant (0 + StoreOffset, MVT::i8));
- SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, EVT::Other, ChainHi,
+ SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi,
SrcHi, PtrLo, PtrHi,
- DAG.getConstant (1 + StoreOffset, EVT::i8));
+ DAG.getConstant (1 + StoreOffset, MVT::i8));
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, getChain(Store1),
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, getChain(Store1),
getChain(Store2));
}
- else if (ValueType == EVT::i32) {
+ else if (ValueType == MVT::i32) {
// Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR.
SDValue SrcLo, SrcHi;
GetExpandedParts(Src, DAG, SrcLo, SrcHi);
@@ -574,30 +574,30 @@
ChainHi1 = ChainHi.getOperand(0);
ChainHi2 = ChainHi.getOperand(1);
}
- SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, EVT::Other,
+ SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other,
ChainLo1,
SrcLo1, PtrLo, PtrHi,
- DAG.getConstant (0 + StoreOffset, EVT::i8));
+ DAG.getConstant (0 + StoreOffset, MVT::i8));
- SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, EVT::Other, ChainLo2,
+ SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainLo2,
SrcLo2, PtrLo, PtrHi,
- DAG.getConstant (1 + StoreOffset, EVT::i8));
+ DAG.getConstant (1 + StoreOffset, MVT::i8));
- SDValue Store3 = DAG.getNode(PIC16ISD::PIC16Store, dl, EVT::Other, ChainHi1,
+ SDValue Store3 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi1,
SrcHi1, PtrLo, PtrHi,
- DAG.getConstant (2 + StoreOffset, EVT::i8));
+ DAG.getConstant (2 + StoreOffset, MVT::i8));
- SDValue Store4 = DAG.getNode(PIC16ISD::PIC16Store, dl, EVT::Other, ChainHi2,
+ SDValue Store4 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi2,
SrcHi2, PtrLo, PtrHi,
- DAG.getConstant (3 + StoreOffset, EVT::i8));
+ DAG.getConstant (3 + StoreOffset, MVT::i8));
- SDValue RetLo = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ SDValue RetLo = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
getChain(Store1), getChain(Store2));
- SDValue RetHi = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ SDValue RetHi = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
getChain(Store3), getChain(Store4));
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, RetLo, RetHi);
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, RetLo, RetHi);
- } else if (ValueType == EVT::i64) {
+ } else if (ValueType == MVT::i64) {
SDValue SrcLo, SrcHi;
GetExpandedParts(Src, DAG, SrcLo, SrcHi);
SDValue ChainLo = Chain, ChainHi = Chain;
@@ -613,7 +613,7 @@
SDValue Store2 = DAG.getStore(ChainHi, dl, SrcHi, Ptr, NULL,
1 + StoreOffset);
- return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Store1,
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1,
Store2);
} else {
assert (0 && "value type not supported");
@@ -627,12 +627,12 @@
// FIXME there isn't really debug info here
DebugLoc dl = ES->getDebugLoc();
- SDValue TES = DAG.getTargetExternalSymbol(ES->getSymbol(), EVT::i8);
- SDValue Offset = DAG.getConstant(0, EVT::i8);
- SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, EVT::i8, TES, Offset);
- SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, EVT::i8, TES, Offset);
+ SDValue TES = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8);
+ SDValue Offset = DAG.getConstant(0, MVT::i8);
+ SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TES, Offset);
+ SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TES, Offset);
- return DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i16, Lo, Hi);
+ return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
}
// ExpandGlobalAddress -
@@ -641,14 +641,14 @@
// FIXME there isn't really debug info here
DebugLoc dl = G->getDebugLoc();
- SDValue TGA = DAG.getTargetGlobalAddress(G->getGlobal(), EVT::i8,
+ SDValue TGA = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i8,
G->getOffset());
- SDValue Offset = DAG.getConstant(0, EVT::i8);
- SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, EVT::i8, TGA, Offset);
- SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, EVT::i8, TGA, Offset);
+ SDValue Offset = DAG.getConstant(0, MVT::i8);
+ SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TGA, Offset);
+ SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TGA, Offset);
- return DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i16, Lo, Hi);
+ return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
}
bool PIC16TargetLowering::isDirectAddress(const SDValue &Op) {
@@ -695,11 +695,11 @@
// Extract the lo component.
Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op,
- DAG.getConstant(0, EVT::i8));
+ DAG.getConstant(0, MVT::i8));
// extract the hi component
Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op,
- DAG.getConstant(1, EVT::i8));
+ DAG.getConstant(1, MVT::i8));
}
// Legalize FrameIndex into ExternalSymbol and offset.
@@ -723,7 +723,7 @@
const char *tmpName;
if (FIndex < ReservedFrameCount) {
tmpName = createESName(PAN::getFrameLabel(Name));
- ES = DAG.getTargetExternalSymbol(tmpName, EVT::i8);
+ ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
Offset = 0;
for (unsigned i=0; i<FIndex ; ++i) {
Offset += MFI->getObjectSize(i);
@@ -731,7 +731,7 @@
} else {
// FrameIndex has been made for some temporary storage
tmpName = createESName(PAN::getTempdataLabel(Name));
- ES = DAG.getTargetExternalSymbol(tmpName, EVT::i8);
+ ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
Offset = GetTmpOffsetForFI(FIndex, MFI->getObjectSize(FIndex));
}
@@ -777,11 +777,11 @@
// then treat it as direct address.
// One example for such case is storing and loading
// from function frame during a call
- if (Ptr.getValueType() == EVT::i8) {
+ if (Ptr.getValueType() == MVT::i8) {
switch (Ptr.getOpcode()) {
case ISD::TargetExternalSymbol:
Lo = Ptr;
- Hi = DAG.getConstant(1, EVT::i8);
+ Hi = DAG.getConstant(1, MVT::i8);
return;
}
}
@@ -792,14 +792,14 @@
int FrameOffset;
if (TFI.getOpcode() == ISD::TargetFrameIndex) {
LegalizeFrameIndex(TFI, DAG, Lo, FrameOffset);
- Hi = DAG.getConstant(1, EVT::i8);
+ Hi = DAG.getConstant(1, MVT::i8);
Offset += FrameOffset;
return;
} else if (TFI.getOpcode() == ISD::TargetExternalSymbol) {
// FrameIndex has already been expanded.
// Now just make use of its expansion
Lo = TFI;
- Hi = DAG.getConstant(1, EVT::i8);
+ Hi = DAG.getConstant(1, MVT::i8);
SDValue FOffset = Ptr.getOperand(0).getOperand(1);
assert (FOffset.getOpcode() == ISD::Constant &&
"Invalid operand of PIC16ISD::Lo");
@@ -817,7 +817,7 @@
// signifies that banksel needs to generated for it. Value 0 for
// the constant signifies that banksel does not need to be generated
// for it. Mark it as 1 now and optimize later.
- Hi = DAG.getConstant(1, EVT::i8);
+ Hi = DAG.getConstant(1, MVT::i8);
return;
}
@@ -825,8 +825,8 @@
GetExpandedParts(Ptr, DAG, Lo, Hi);
// Put the hi and lo parts into FSR.
- Lo = DAG.getNode(PIC16ISD::MTLO, dl, EVT::i8, Lo);
- Hi = DAG.getNode(PIC16ISD::MTHI, dl, EVT::i8, Hi);
+ Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Lo);
+ Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Hi);
return;
}
@@ -856,8 +856,8 @@
if(ISD::isNON_EXTLoad(N)) {
for (iter=0; iter<NumLoads ; ++iter) {
// Add the pointer offset if any
- Offset = DAG.getConstant(iter + LoadOffset, EVT::i8);
- Tys = DAG.getVTList(EVT::i8, EVT::Other);
+ Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
+ Tys = DAG.getVTList(MVT::i8, MVT::Other);
Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi,
Offset);
PICLoads.push_back(Load);
@@ -872,18 +872,18 @@
// i.e. without any extension
EVT MemVT = LD->getMemoryVT();
unsigned MemBytes = MemVT.getSizeInBits() / 8;
- // if EVT::i1 is extended to EVT::i8 then MemBytes will be zero
+ // if MVT::i1 is extended to MVT::i8 then MemBytes will be zero
// So set it to one
if (MemBytes == 0) MemBytes = 1;
unsigned ExtdBytes = VT.getSizeInBits() / 8;
- Offset = DAG.getConstant(LoadOffset, EVT::i8);
+ Offset = DAG.getConstant(LoadOffset, MVT::i8);
- Tys = DAG.getVTList(EVT::i8, EVT::Other);
+ Tys = DAG.getVTList(MVT::i8, MVT::Other);
// For MemBytes generate PIC16Load with proper offset
for (iter=0; iter < MemBytes; ++iter) {
// Add the pointer offset if any
- Offset = DAG.getConstant(iter + LoadOffset, EVT::i8);
+ Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi,
Offset);
PICLoads.push_back(Load);
@@ -893,15 +893,15 @@
if (ISD::isSEXTLoad(N)) {
// For all ExtdBytes use the Right Shifted(Arithmetic) Value of the
// highest MemByte
- SDValue SRA = DAG.getNode(ISD::SRA, dl, EVT::i8, Load,
- DAG.getConstant(7, EVT::i8));
+ SDValue SRA = DAG.getNode(ISD::SRA, dl, MVT::i8, Load,
+ DAG.getConstant(7, MVT::i8));
for (iter=MemBytes; iter<ExtdBytes; ++iter) {
PICLoads.push_back(SRA);
}
} else if (ISD::isZEXTLoad(N) || ISD::isEXTLoad(N)) {
//} else if (ISD::isZEXTLoad(N)) {
// ZeroExtendedLoad -- For all ExtdBytes use constant 0
- SDValue ConstZero = DAG.getConstant(0, EVT::i8);
+ SDValue ConstZero = DAG.getConstant(0, MVT::i8);
for (iter=MemBytes; iter<ExtdBytes; ++iter) {
PICLoads.push_back(ConstZero);
}
@@ -909,46 +909,46 @@
}
SDValue BP;
- if (VT == EVT::i8) {
+ if (VT == MVT::i8) {
// Operand of Load is illegal -- Load itself is legal
return PICLoads[0];
}
- else if (VT == EVT::i16) {
+ else if (VT == MVT::i16) {
BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, PICLoads[0], PICLoads[1]);
- if (MemVT == EVT::i8)
+ if (MemVT == MVT::i8)
Chain = getChain(PICLoads[0]);
else
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
getChain(PICLoads[0]), getChain(PICLoads[1]));
- } else if (VT == EVT::i32) {
+ } else if (VT == MVT::i32) {
SDValue BPs[2];
- BPs[0] = DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i16,
+ BPs[0] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16,
PICLoads[0], PICLoads[1]);
- BPs[1] = DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i16,
+ BPs[1] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16,
PICLoads[2], PICLoads[3]);
BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, BPs[0], BPs[1]);
- if (MemVT == EVT::i8)
+ if (MemVT == MVT::i8)
Chain = getChain(PICLoads[0]);
- else if (MemVT == EVT::i16)
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ else if (MemVT == MVT::i16)
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
getChain(PICLoads[0]), getChain(PICLoads[1]));
else {
SDValue Chains[2];
- Chains[0] = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chains[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
getChain(PICLoads[0]), getChain(PICLoads[1]));
- Chains[1] = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chains[1] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
getChain(PICLoads[2]), getChain(PICLoads[3]));
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
Chains[0], Chains[1]);
}
}
- Tys = DAG.getVTList(VT, EVT::Other);
+ Tys = DAG.getVTList(VT, MVT::Other);
return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, BP, Chain);
}
SDValue PIC16TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
// We should have handled larger operands in type legalizer itself.
- assert (Op.getValueType() == EVT::i8 && "illegal shift to lower");
+ assert (Op.getValueType() == MVT::i8 && "illegal shift to lower");
SDNode *N = Op.getNode();
SDValue Value = N->getOperand(0);
@@ -978,7 +978,7 @@
SDValue PIC16TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) {
// We should have handled larger operands in type legalizer itself.
- assert (Op.getValueType() == EVT::i8 && "illegal multiply to lower");
+ assert (Op.getValueType() == MVT::i8 && "illegal multiply to lower");
SDNode *N = Op.getNode();
SmallVector<SDValue, 2> Ops(2);
@@ -1051,7 +1051,7 @@
SDValue PIC16TargetLowering::ConvertToMemOperand(SDValue Op,
SelectionDAG &DAG,
DebugLoc dl) {
- assert (Op.getValueType() == EVT::i8
+ assert (Op.getValueType() == MVT::i8
&& "illegal value type to store on stack.");
MachineFunction &MF = DAG.getMachineFunction();
@@ -1063,22 +1063,22 @@
// Get a stack slot index and convert to es.
int FI = MF.getFrameInfo()->CreateStackObject(1, 1);
const char *tmpName = createESName(PAN::getTempdataLabel(FuncName));
- SDValue ES = DAG.getTargetExternalSymbol(tmpName, EVT::i8);
+ SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
// Store the value to ES.
- SDValue Store = DAG.getNode (PIC16ISD::PIC16Store, dl, EVT::Other,
+ SDValue Store = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other,
DAG.getEntryNode(),
Op, ES,
- DAG.getConstant (1, EVT::i8), // Banksel.
+ DAG.getConstant (1, MVT::i8), // Banksel.
DAG.getConstant (GetTmpOffsetForFI(FI, 1),
- EVT::i8));
+ MVT::i8));
// Load the value from ES.
- SDVTList Tys = DAG.getVTList(EVT::i8, EVT::Other);
+ SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other);
SDValue Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Store,
- ES, DAG.getConstant (1, EVT::i8),
+ ES, DAG.getConstant (1, MVT::i8),
DAG.getConstant (GetTmpOffsetForFI(FI, 1),
- EVT::i8));
+ MVT::i8));
return Load.getValue(0);
}
@@ -1096,7 +1096,7 @@
return Chain;
std::vector<SDValue> Ops;
- SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
SDValue Arg, StoreRet;
// For PIC16 ABI the arguments come after the return value.
@@ -1110,7 +1110,7 @@
Ops.push_back(Arg);
Ops.push_back(DataAddr_Lo);
Ops.push_back(DataAddr_Hi);
- Ops.push_back(DAG.getConstant(ArgOffset, EVT::i8));
+ Ops.push_back(DAG.getConstant(ArgOffset, MVT::i8));
Ops.push_back(InFlag);
StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
@@ -1147,7 +1147,7 @@
SDValue StoreRet;
std::vector<SDValue> Ops;
- SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
for (unsigned i=0, Offset = 0; i<NumOps; i++) {
// Get the argument
Arg = Outs[i].Val;
@@ -1160,7 +1160,7 @@
Ops.push_back(Arg);
Ops.push_back(PtrLo);
Ops.push_back(PtrHi);
- Ops.push_back(DAG.getConstant(StoreOffset, EVT::i8));
+ Ops.push_back(DAG.getConstant(StoreOffset, MVT::i8));
Ops.push_back(InFlag);
StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
@@ -1193,10 +1193,10 @@
// Call has something to return
SDValue LoadRet;
- SDVTList Tys = DAG.getVTList(EVT::i8, EVT::Other, EVT::Flag);
+ SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
for(unsigned i=0;i<RetVals;i++) {
LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, DataAddr_Lo,
- DataAddr_Hi, DAG.getConstant(i, EVT::i8),
+ DataAddr_Hi, DAG.getConstant(i, MVT::i8),
InFlag);
InFlag = getOutFlag(LoadRet);
Chain = getChain(LoadRet);
@@ -1226,13 +1226,13 @@
unsigned LdOffset;
LegalizeAddress(RetLabel, DAG, LdLo, LdHi, LdOffset, dl);
- SDVTList Tys = DAG.getVTList(EVT::i8, EVT::Other, EVT::Flag);
+ SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
SDValue LoadRet;
for(unsigned i=0, Offset=0;i<RetVals;i++) {
LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, LdLo, LdHi,
- DAG.getConstant(LdOffset + Offset, EVT::i8),
+ DAG.getConstant(LdOffset + Offset, MVT::i8),
InFlag);
InFlag = getOutFlag(LoadRet);
@@ -1261,18 +1261,18 @@
std::string FuncName = F->getName();
const char *tmpName = createESName(PAN::getFrameLabel(FuncName));
- SDVTList VTs = DAG.getVTList (EVT::i8, EVT::Other);
- SDValue ES = DAG.getTargetExternalSymbol(tmpName, EVT::i8);
- SDValue BS = DAG.getConstant(1, EVT::i8);
+ SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Other);
+ SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
+ SDValue BS = DAG.getConstant(1, MVT::i8);
SDValue RetVal;
for(unsigned i=0;i<NumRet; ++i) {
RetVal = Outs[i].Val;
- Chain = DAG.getNode (PIC16ISD::PIC16Store, dl, EVT::Other, Chain, RetVal,
+ Chain = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, RetVal,
ES, BS,
- DAG.getConstant (i, EVT::i8));
+ DAG.getConstant (i, MVT::i8));
}
- return DAG.getNode(PIC16ISD::RET, dl, EVT::Other, Chain);
+ return DAG.getNode(PIC16ISD::RET, dl, MVT::Other, Chain);
}
void PIC16TargetLowering::
@@ -1281,7 +1281,7 @@
SelectionDAG &DAG) {
assert (Callee.getOpcode() == PIC16ISD::PIC16Connect
&& "Don't know what to do of such callee!!");
- SDValue ZeroOperand = DAG.getConstant(0, EVT::i8);
+ SDValue ZeroOperand = DAG.getConstant(0, MVT::i8);
SDValue SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
Chain = getChain(SeqStart);
SDValue OperFlag = getOutFlag(SeqStart); // To manage the data dependency
@@ -1291,15 +1291,15 @@
SDValue Hi = Callee.getOperand(1);
SDValue Data_Lo, Data_Hi;
- SDVTList Tys = DAG.getVTList(EVT::i8, EVT::Other, EVT::Flag);
+ SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
// Subtract 2 from Address to get the Lower part of DataAddress.
- SDVTList VTList = DAG.getVTList(EVT::i8, EVT::Flag);
+ SDVTList VTList = DAG.getVTList(MVT::i8, MVT::Flag);
Data_Lo = DAG.getNode(ISD::SUBC, dl, VTList, Lo,
- DAG.getConstant(2, EVT::i8));
- SDValue Ops[3] = { Hi, DAG.getConstant(0, EVT::i8), Data_Lo.getValue(1)};
+ DAG.getConstant(2, MVT::i8));
+ SDValue Ops[3] = { Hi, DAG.getConstant(0, MVT::i8), Data_Lo.getValue(1)};
Data_Hi = DAG.getNode(ISD::SUBE, dl, VTList, Ops, 3);
- SDValue PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, EVT::i8, Data_Hi);
- Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, EVT::i8, Data_Lo, PCLATH);
+ SDValue PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, Data_Hi);
+ Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Data_Lo, PCLATH);
SDValue Call = DAG.getNode(PIC16ISD::CALLW, dl, Tys, Chain, Callee,
OperFlag);
Chain = getChain(Call);
@@ -1310,7 +1310,7 @@
OperFlag = getOutFlag(SeqEnd);
// Low part of Data Address
- DataAddr_Lo = DAG.getNode(PIC16ISD::MTLO, dl, EVT::i8, Call, OperFlag);
+ DataAddr_Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Call, OperFlag);
// Make the second call.
SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
@@ -1319,13 +1319,13 @@
// Subtract 1 from Address to get high part of data address.
Data_Lo = DAG.getNode(ISD::SUBC, dl, VTList, Lo,
- DAG.getConstant(1, EVT::i8));
- SDValue HiOps[3] = { Hi, DAG.getConstant(0, EVT::i8), Data_Lo.getValue(1)};
+ DAG.getConstant(1, MVT::i8));
+ SDValue HiOps[3] = { Hi, DAG.getConstant(0, MVT::i8), Data_Lo.getValue(1)};
Data_Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
- PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, EVT::i8, Data_Hi);
+ PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, Data_Hi);
// Use new Lo to make another CALLW
- Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, EVT::i8, Data_Lo, PCLATH);
+ Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Data_Lo, PCLATH);
Call = DAG.getNode(PIC16ISD::CALLW, dl, Tys, Chain, Callee, OperFlag);
Chain = getChain(Call);
OperFlag = getOutFlag(Call);
@@ -1334,7 +1334,7 @@
Chain = getChain(SeqEnd);
OperFlag = getOutFlag(SeqEnd);
// Hi part of Data Address
- DataAddr_Hi = DAG.getNode(PIC16ISD::MTHI, dl, EVT::i8, Call, OperFlag);
+ DataAddr_Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Call, OperFlag);
}
SDValue
@@ -1346,7 +1346,7 @@
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) {
- assert(Callee.getValueType() == EVT::i16 &&
+ assert(Callee.getValueType() == MVT::i16 &&
"Don't know how to legalize this call node!!!");
// The flag to track if this is a direct or indirect call.
@@ -1369,7 +1369,7 @@
// Indirect addresses. Get the hi and lo parts of ptr.
GetExpandedParts(Callee, DAG, Lo, Hi);
// Connect Lo and Hi parts of the callee with the PIC16Connect
- Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, EVT::i8, Lo, Hi);
+ Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Lo, Hi);
// Read DataAddress only if we have to pass arguments or
// read return value.
@@ -1377,7 +1377,7 @@
GetDataAddress(dl, Callee, Chain, DataAddr_Lo, DataAddr_Hi, DAG);
}
- SDValue ZeroOperand = DAG.getConstant(0, EVT::i8);
+ SDValue ZeroOperand = DAG.getConstant(0, MVT::i8);
// Start the call sequence.
// Carring the Constant 0 along the CALLSEQSTART
@@ -1394,32 +1394,32 @@
// Considering the GlobalAddressNode case here.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
GlobalValue *GV = G->getGlobal();
- Callee = DAG.getTargetGlobalAddress(GV, EVT::i8);
+ Callee = DAG.getTargetGlobalAddress(GV, MVT::i8);
Name = G->getGlobal()->getName();
} else {// Considering the ExternalSymbol case here
ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Callee);
- Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), EVT::i8);
+ Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8);
Name = ES->getSymbol();
}
// Label for argument passing
const char *argFrame = createESName(PAN::getArgsLabel(Name));
- ArgLabel = DAG.getTargetExternalSymbol(argFrame, EVT::i8);
+ ArgLabel = DAG.getTargetExternalSymbol(argFrame, MVT::i8);
// Label for reading return value
const char *retName = createESName(PAN::getRetvalLabel(Name));
- RetLabel = DAG.getTargetExternalSymbol(retName, EVT::i8);
+ RetLabel = DAG.getTargetExternalSymbol(retName, MVT::i8);
} else {
// if indirect call
SDValue CodeAddr_Lo = Callee.getOperand(0);
SDValue CodeAddr_Hi = Callee.getOperand(1);
- /*CodeAddr_Lo = DAG.getNode(ISD::ADD, dl, EVT::i8, CodeAddr_Lo,
- DAG.getConstant(2, EVT::i8));*/
+ /*CodeAddr_Lo = DAG.getNode(ISD::ADD, dl, MVT::i8, CodeAddr_Lo,
+ DAG.getConstant(2, MVT::i8));*/
// move Hi part in PCLATH
- CodeAddr_Hi = DAG.getNode(PIC16ISD::MTPCLATH, dl, EVT::i8, CodeAddr_Hi);
- Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, EVT::i8, CodeAddr_Lo,
+ CodeAddr_Hi = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, CodeAddr_Hi);
+ Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, CodeAddr_Lo,
CodeAddr_Hi);
}
@@ -1437,7 +1437,7 @@
OperFlag = getOutFlag(CallArgs);
}
- SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
SDValue PICCall = DAG.getNode(PIC16ISD::CALL, dl, Tys, Chain, Callee,
OperFlag);
Chain = getChain(PICCall);
@@ -1502,14 +1502,14 @@
DebugLoc dl = Op.getDebugLoc();
// We should have handled larger operands in type legalizer itself.
- assert (Op.getValueType() == EVT::i8 && "illegal Op to lower");
+ assert (Op.getValueType() == MVT::i8 && "illegal Op to lower");
unsigned MemOp = 1;
if (NeedToConvertToMemOp(Op, MemOp)) {
// Put one value on stack.
SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
- return DAG.getNode(Op.getOpcode(), dl, EVT::i8, Op.getOperand(MemOp ^ 1),
+ return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
NewVal);
}
else {
@@ -1521,7 +1521,7 @@
// that affects carry.
SDValue PIC16TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) {
// We should have handled larger operands in type legalizer itself.
- assert (Op.getValueType() == EVT::i8 && "illegal add to lower");
+ assert (Op.getValueType() == MVT::i8 && "illegal add to lower");
DebugLoc dl = Op.getDebugLoc();
unsigned MemOp = 1;
if (NeedToConvertToMemOp(Op, MemOp)) {
@@ -1529,7 +1529,7 @@
SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
// ADDC and ADDE produce two results.
- SDVTList Tys = DAG.getVTList(EVT::i8, EVT::Flag);
+ SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
// ADDE has three operands, the last one is the carry bit.
if (Op.getOpcode() == ISD::ADDE)
@@ -1541,7 +1541,7 @@
NewVal);
// ADD it is. It produces only one result.
else
- return DAG.getNode(Op.getOpcode(), dl, EVT::i8, Op.getOperand(MemOp ^ 1),
+ return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
NewVal);
}
else
@@ -1551,7 +1551,7 @@
SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
// We should have handled larger operands in type legalizer itself.
- assert (Op.getValueType() == EVT::i8 && "illegal sub to lower");
+ assert (Op.getValueType() == MVT::i8 && "illegal sub to lower");
// Nothing to do if the first operand is already a direct load and it has
// only one use.
@@ -1561,7 +1561,7 @@
// Put first operand on stack.
SDValue NewVal = ConvertToMemOperand (Op.getOperand(0), DAG, dl);
- SDVTList Tys = DAG.getVTList(EVT::i8, EVT::Flag);
+ SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
switch (Op.getOpcode()) {
default:
assert (0 && "Opcode unknown.");
@@ -1573,7 +1573,7 @@
return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1));
break;
case ISD::SUB:
- return DAG.getNode(Op.getOpcode(), dl, EVT::i8, NewVal, Op.getOperand(1));
+ return DAG.getNode(Op.getOpcode(), dl, MVT::i8, NewVal, Op.getOperand(1));
break;
}
}
@@ -1615,13 +1615,13 @@
// Create the <fname>.args external symbol.
const char *tmpName = createESName(PAN::getArgsLabel(FuncName));
- SDValue ES = DAG.getTargetExternalSymbol(tmpName, EVT::i8);
+ SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
// Load arg values from the label + offset.
- SDVTList VTs = DAG.getVTList (EVT::i8, EVT::Other);
- SDValue BS = DAG.getConstant(1, EVT::i8);
+ SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Other);
+ SDValue BS = DAG.getConstant(1, MVT::i8);
for (unsigned i = 0; i < NumArgVals ; ++i) {
- SDValue Offset = DAG.getConstant(i, EVT::i8);
+ SDValue Offset = DAG.getConstant(i, MVT::i8);
SDValue PICLoad = DAG.getNode(PIC16ISD::PIC16LdArg, dl, VTs, Chain, ES, BS,
Offset);
Chain = getChain(PICLoad);
@@ -1753,16 +1753,16 @@
}
}
- PIC16CC = DAG.getConstant(CondCode, EVT::i8);
+ PIC16CC = DAG.getConstant(CondCode, MVT::i8);
// These are signed comparisons.
- SDValue Mask = DAG.getConstant(128, EVT::i8);
+ SDValue Mask = DAG.getConstant(128, MVT::i8);
if (isSignedComparison(CondCode)) {
- LHS = DAG.getNode (ISD::XOR, dl, EVT::i8, LHS, Mask);
- RHS = DAG.getNode (ISD::XOR, dl, EVT::i8, RHS, Mask);
+ LHS = DAG.getNode (ISD::XOR, dl, MVT::i8, LHS, Mask);
+ RHS = DAG.getNode (ISD::XOR, dl, MVT::i8, RHS, Mask);
}
- SDVTList VTs = DAG.getVTList (EVT::i8, EVT::Flag);
+ SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Flag);
// We can use a subtract operation to set the condition codes. But
// we need to put one operand in memory if required.
// Nothing to do if the first operand is already a valid type (direct load
@@ -1877,7 +1877,7 @@
SDValue PIC16CC;
SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl);
- return DAG.getNode(PIC16ISD::BRCOND, dl, EVT::Other, Chain, Dest, PIC16CC,
+ return DAG.getNode(PIC16ISD::BRCOND, dl, MVT::Other, Chain, Dest, PIC16CC,
Cmp.getValue(1));
}
Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h Tue Aug 11 15:47:22 2009
@@ -82,7 +82,7 @@
/// DAG node.
virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - Return the ISD::SETCC ValueType
- virtual EVT::SimpleValueType getSetCCResultType(EVT ValType) const;
+ virtual MVT::SimpleValueType getSetCCResultType(EVT ValType) const;
SDValue LowerShift(SDValue Op, SelectionDAG &DAG);
SDValue LowerMUL(SDValue Op, SelectionDAG &DAG);
SDValue LowerADD(SDValue Op, SelectionDAG &DAG);
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Tue Aug 11 15:47:22 2009
@@ -64,13 +64,13 @@
/// getI32Imm - Return a target constant with the specified value, of type
/// i32.
inline SDValue getI32Imm(unsigned Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i32);
+ return CurDAG->getTargetConstant(Imm, MVT::i32);
}
/// getI64Imm - Return a target constant with the specified value, of type
/// i64.
inline SDValue getI64Imm(uint64_t Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i64);
+ return CurDAG->getTargetConstant(Imm, MVT::i64);
}
/// getSmallIPtrImm - Return a target constant of pointer type.
@@ -286,7 +286,7 @@
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
DebugLoc dl = DebugLoc::getUnknownLoc();
- if (PPCLowering.getPointerTy() == EVT::i32) {
+ if (PPCLowering.getPointerTy() == MVT::i32) {
GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass);
BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR), PPC::LR);
BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
@@ -309,7 +309,7 @@
return false;
Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
- if (N->getValueType(0) == EVT::i32)
+ if (N->getValueType(0) == MVT::i32)
return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
else
return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
@@ -323,7 +323,7 @@
/// isInt32Immediate - This method tests to see if the node is a 32-bit constant
/// operand. If so Imm will receive the 32-bit value.
static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
- if (N->getOpcode() == ISD::Constant && N->getValueType(0) == EVT::i32) {
+ if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
Imm = cast<ConstantSDNode>(N)->getZExtValue();
return true;
}
@@ -333,7 +333,7 @@
/// isInt64Immediate - This method tests to see if the node is a 64-bit constant
/// operand. If so Imm will receive the 64-bit value.
static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
- if (N->getOpcode() == ISD::Constant && N->getValueType(0) == EVT::i64) {
+ if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
Imm = cast<ConstantSDNode>(N)->getZExtValue();
return true;
}
@@ -381,7 +381,7 @@
unsigned &MB, unsigned &ME) {
// Don't even go down this path for i64, since different logic will be
// necessary for rldicl/rldicr/rldimi.
- if (N->getValueType(0) != EVT::i32)
+ if (N->getValueType(0) != MVT::i32)
return false;
unsigned Shift = 32;
@@ -485,7 +485,7 @@
SH &= 31;
SDValue Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB),
getI32Imm(ME) };
- return CurDAG->getTargetNode(PPC::RLWIMI, dl, EVT::i32, Ops, 5);
+ return CurDAG->getTargetNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
}
}
return 0;
@@ -498,17 +498,17 @@
// Always select the LHS.
unsigned Opc;
- if (LHS.getValueType() == EVT::i32) {
+ if (LHS.getValueType() == MVT::i32) {
unsigned Imm;
if (CC == ISD::SETEQ || CC == ISD::SETNE) {
if (isInt32Immediate(RHS, Imm)) {
// SETEQ/SETNE comparison with 16-bit immediate, fold it.
if (isUInt16(Imm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, EVT::i32, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
// If this is a 16-bit signed immediate, fold it.
if (isInt16((int)Imm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, EVT::i32, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, MVT::i32, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
// For non-equality comparisons, the default code would materialize the
@@ -520,36 +520,36 @@
// xoris r0,r3,0x1234
// cmplwi cr0,r0,0x5678
// beq cr0,L6
- SDValue Xor(CurDAG->getTargetNode(PPC::XORIS, dl, EVT::i32, LHS,
+ SDValue Xor(CurDAG->getTargetNode(PPC::XORIS, dl, MVT::i32, LHS,
getI32Imm(Imm >> 16)), 0);
- return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, EVT::i32, Xor,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, Xor,
getI32Imm(Imm & 0xFFFF)), 0);
}
Opc = PPC::CMPLW;
} else if (ISD::isUnsignedIntSetCC(CC)) {
if (isInt32Immediate(RHS, Imm) && isUInt16(Imm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, EVT::i32, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
Opc = PPC::CMPLW;
} else {
short SImm;
if (isIntS16Immediate(RHS, SImm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, EVT::i32, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, MVT::i32, LHS,
getI32Imm((int)SImm & 0xFFFF)),
0);
Opc = PPC::CMPW;
}
- } else if (LHS.getValueType() == EVT::i64) {
+ } else if (LHS.getValueType() == MVT::i64) {
uint64_t Imm;
if (CC == ISD::SETEQ || CC == ISD::SETNE) {
if (isInt64Immediate(RHS.getNode(), Imm)) {
// SETEQ/SETNE comparison with 16-bit immediate, fold it.
if (isUInt16(Imm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, EVT::i64, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
// If this is a 16-bit signed immediate, fold it.
if (isInt16(Imm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, EVT::i64, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, MVT::i64, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
// For non-equality comparisons, the default code would materialize the
@@ -562,33 +562,33 @@
// cmpldi cr0,r0,0x5678
// beq cr0,L6
if (isUInt32(Imm)) {
- SDValue Xor(CurDAG->getTargetNode(PPC::XORIS8, dl, EVT::i64, LHS,
+ SDValue Xor(CurDAG->getTargetNode(PPC::XORIS8, dl, MVT::i64, LHS,
getI64Imm(Imm >> 16)), 0);
- return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, EVT::i64, Xor,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, Xor,
getI64Imm(Imm & 0xFFFF)), 0);
}
}
Opc = PPC::CMPLD;
} else if (ISD::isUnsignedIntSetCC(CC)) {
if (isInt64Immediate(RHS.getNode(), Imm) && isUInt16(Imm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, EVT::i64, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, LHS,
getI64Imm(Imm & 0xFFFF)), 0);
Opc = PPC::CMPLD;
} else {
short SImm;
if (isIntS16Immediate(RHS, SImm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, EVT::i64, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, MVT::i64, LHS,
getI64Imm(SImm & 0xFFFF)),
0);
Opc = PPC::CMPD;
}
- } else if (LHS.getValueType() == EVT::f32) {
+ } else if (LHS.getValueType() == MVT::f32) {
Opc = PPC::FCMPUS;
} else {
- assert(LHS.getValueType() == EVT::f64 && "Unknown vt!");
+ assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
Opc = PPC::FCMPUD;
}
- return SDValue(CurDAG->getTargetNode(Opc, dl, EVT::i32, LHS, RHS), 0);
+ return SDValue(CurDAG->getTargetNode(Opc, dl, MVT::i32, LHS, RHS), 0);
}
static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
@@ -670,27 +670,27 @@
switch (CC) {
default: break;
case ISD::SETEQ: {
- Op = SDValue(CurDAG->getTargetNode(PPC::CNTLZW, dl, EVT::i32, Op), 0);
+ Op = SDValue(CurDAG->getTargetNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4);
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
case ISD::SETNE: {
SDValue AD =
- SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, EVT::i32, EVT::Flag,
+ SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
Op, getI32Imm(~0U)), 0);
- return CurDAG->SelectNodeTo(N, PPC::SUBFE, EVT::i32, AD, Op,
+ return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
AD.getValue(1));
}
case ISD::SETLT: {
SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4);
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
case ISD::SETGT: {
SDValue T =
- SDValue(CurDAG->getTargetNode(PPC::NEG, dl, EVT::i32, Op), 0);
- T = SDValue(CurDAG->getTargetNode(PPC::ANDC, dl, EVT::i32, T, Op), 0);
+ SDValue(CurDAG->getTargetNode(PPC::NEG, dl, MVT::i32, Op), 0);
+ T = SDValue(CurDAG->getTargetNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4);
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
}
} else if (Imm == ~0U) { // setcc op, -1
@@ -698,33 +698,33 @@
switch (CC) {
default: break;
case ISD::SETEQ:
- Op = SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, EVT::i32, EVT::Flag,
+ Op = SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
Op, getI32Imm(1)), 0);
- return CurDAG->SelectNodeTo(N, PPC::ADDZE, EVT::i32,
+ return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
SDValue(CurDAG->getTargetNode(PPC::LI, dl,
- EVT::i32,
+ MVT::i32,
getI32Imm(0)), 0),
Op.getValue(1));
case ISD::SETNE: {
- Op = SDValue(CurDAG->getTargetNode(PPC::NOR, dl, EVT::i32, Op, Op), 0);
- SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, dl, EVT::i32, EVT::Flag,
+ Op = SDValue(CurDAG->getTargetNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
+ SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
Op, getI32Imm(~0U));
- return CurDAG->SelectNodeTo(N, PPC::SUBFE, EVT::i32, SDValue(AD, 0),
+ return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
Op, SDValue(AD, 1));
}
case ISD::SETLT: {
- SDValue AD = SDValue(CurDAG->getTargetNode(PPC::ADDI, dl, EVT::i32, Op,
+ SDValue AD = SDValue(CurDAG->getTargetNode(PPC::ADDI, dl, MVT::i32, Op,
getI32Imm(1)), 0);
- SDValue AN = SDValue(CurDAG->getTargetNode(PPC::AND, dl, EVT::i32, AD,
+ SDValue AN = SDValue(CurDAG->getTargetNode(PPC::AND, dl, MVT::i32, AD,
Op), 0);
SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4);
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
case ISD::SETGT: {
SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
- Op = SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, EVT::i32, Ops, 4),
+ Op = SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4),
0);
- return CurDAG->SelectNodeTo(N, PPC::XORI, EVT::i32, Op,
+ return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
getI32Imm(1));
}
}
@@ -738,29 +738,29 @@
SDValue IntCR;
// Force the ccreg into CR7.
- SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, EVT::i32);
+ SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
SDValue InFlag(0, 0); // Null incoming flag value.
CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
InFlag).getValue(1);
if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1)
- IntCR = SDValue(CurDAG->getTargetNode(PPC::MFOCRF, dl, EVT::i32, CR7Reg,
+ IntCR = SDValue(CurDAG->getTargetNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
CCReg), 0);
else
- IntCR = SDValue(CurDAG->getTargetNode(PPC::MFCR, dl, EVT::i32, CCReg), 0);
+ IntCR = SDValue(CurDAG->getTargetNode(PPC::MFCR, dl, MVT::i32, CCReg), 0);
SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
getI32Imm(31), getI32Imm(31) };
if (OtherCondIdx == -1 && !Inv)
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4);
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
// Get the specified bit.
SDValue Tmp =
- SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, EVT::i32, Ops, 4), 0);
+ SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
if (Inv) {
assert(OtherCondIdx == -1 && "Can't have split plus negation");
- return CurDAG->SelectNodeTo(N, PPC::XORI, EVT::i32, Tmp, getI32Imm(1));
+ return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
}
// Otherwise, we have to turn an operation like SETONE -> SETOLT | SETOGT.
@@ -769,9 +769,9 @@
// Get the other bit of the comparison.
Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31);
SDValue OtherCond =
- SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, EVT::i32, Ops, 4), 0);
+ SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
- return CurDAG->SelectNodeTo(N, PPC::OR, EVT::i32, Tmp, OtherCond);
+ return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond);
}
@@ -787,7 +787,7 @@
default: break;
case ISD::Constant: {
- if (N->getValueType(0) == EVT::i64) {
+ if (N->getValueType(0) == MVT::i64) {
// Get 64 bit value.
int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
// Assume no remaining bits.
@@ -822,17 +822,17 @@
// Simple value.
if (isInt16(Imm)) {
// Just the Lo bits.
- Result = CurDAG->getTargetNode(PPC::LI8, dl, EVT::i64, getI32Imm(Lo));
+ Result = CurDAG->getTargetNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
} else if (Lo) {
// Handle the Hi bits.
unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
- Result = CurDAG->getTargetNode(OpC, dl, EVT::i64, getI32Imm(Hi));
+ Result = CurDAG->getTargetNode(OpC, dl, MVT::i64, getI32Imm(Hi));
// And Lo bits.
- Result = CurDAG->getTargetNode(PPC::ORI8, dl, EVT::i64,
+ Result = CurDAG->getTargetNode(PPC::ORI8, dl, MVT::i64,
SDValue(Result, 0), getI32Imm(Lo));
} else {
// Just the Hi bits.
- Result = CurDAG->getTargetNode(PPC::LIS8, dl, EVT::i64, getI32Imm(Hi));
+ Result = CurDAG->getTargetNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
}
// If no shift, we're done.
@@ -840,18 +840,18 @@
// Shift for next step if the upper 32-bits were not zero.
if (Imm) {
- Result = CurDAG->getTargetNode(PPC::RLDICR, dl, EVT::i64,
+ Result = CurDAG->getTargetNode(PPC::RLDICR, dl, MVT::i64,
SDValue(Result, 0),
getI32Imm(Shift), getI32Imm(63 - Shift));
}
// Add in the last bits as required.
if ((Hi = (Remainder >> 16) & 0xFFFF)) {
- Result = CurDAG->getTargetNode(PPC::ORIS8, dl, EVT::i64,
+ Result = CurDAG->getTargetNode(PPC::ORIS8, dl, MVT::i64,
SDValue(Result, 0), getI32Imm(Hi));
}
if ((Lo = Remainder & 0xFFFF)) {
- Result = CurDAG->getTargetNode(PPC::ORI8, dl, EVT::i64,
+ Result = CurDAG->getTargetNode(PPC::ORI8, dl, MVT::i64,
SDValue(Result, 0), getI32Imm(Lo));
}
@@ -868,7 +868,7 @@
case ISD::FrameIndex: {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
SDValue TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
- unsigned Opc = Op.getValueType() == EVT::i32 ? PPC::ADDI : PPC::ADDI8;
+ unsigned Opc = Op.getValueType() == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
if (N->hasOneUse())
return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI,
getSmallIPtrImm(0));
@@ -880,10 +880,10 @@
SDValue InFlag = N->getOperand(1);
// Use MFOCRF if supported.
if (PPCSubTarget.isGigaProcessor())
- return CurDAG->getTargetNode(PPC::MFOCRF, dl, EVT::i32,
+ return CurDAG->getTargetNode(PPC::MFOCRF, dl, MVT::i32,
N->getOperand(0), InFlag);
else
- return CurDAG->getTargetNode(PPC::MFCR, dl, EVT::i32, InFlag);
+ return CurDAG->getTargetNode(PPC::MFCR, dl, MVT::i32, InFlag);
}
case ISD::SDIV: {
@@ -897,19 +897,19 @@
SDValue N0 = N->getOperand(0);
if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
SDNode *Op =
- CurDAG->getTargetNode(PPC::SRAWI, dl, EVT::i32, EVT::Flag,
+ CurDAG->getTargetNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag,
N0, getI32Imm(Log2_32(Imm)));
- return CurDAG->SelectNodeTo(N, PPC::ADDZE, EVT::i32,
+ return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
SDValue(Op, 0), SDValue(Op, 1));
} else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
SDNode *Op =
- CurDAG->getTargetNode(PPC::SRAWI, dl, EVT::i32, EVT::Flag,
+ CurDAG->getTargetNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag,
N0, getI32Imm(Log2_32(-Imm)));
SDValue PT =
- SDValue(CurDAG->getTargetNode(PPC::ADDZE, dl, EVT::i32,
+ SDValue(CurDAG->getTargetNode(PPC::ADDZE, dl, MVT::i32,
SDValue(Op, 0), SDValue(Op, 1)),
0);
- return CurDAG->SelectNodeTo(N, PPC::NEG, EVT::i32, PT);
+ return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
}
}
@@ -932,28 +932,28 @@
unsigned Opcode;
bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
- if (LD->getValueType(0) != EVT::i64) {
+ if (LD->getValueType(0) != MVT::i64) {
// Handle PPC32 integer and normal FP loads.
- assert((!isSExt || LoadedVT == EVT::i16) && "Invalid sext update load");
- switch (LoadedVT.getSimpleVT()) {
+ assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
+ switch (LoadedVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Invalid PPC load type!");
- case EVT::f64: Opcode = PPC::LFDU; break;
- case EVT::f32: Opcode = PPC::LFSU; break;
- case EVT::i32: Opcode = PPC::LWZU; break;
- case EVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
- case EVT::i1:
- case EVT::i8: Opcode = PPC::LBZU; break;
+ case MVT::f64: Opcode = PPC::LFDU; break;
+ case MVT::f32: Opcode = PPC::LFSU; break;
+ case MVT::i32: Opcode = PPC::LWZU; break;
+ case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
+ case MVT::i1:
+ case MVT::i8: Opcode = PPC::LBZU; break;
}
} else {
- assert(LD->getValueType(0) == EVT::i64 && "Unknown load result type!");
- assert((!isSExt || LoadedVT == EVT::i16) && "Invalid sext update load");
- switch (LoadedVT.getSimpleVT()) {
+ assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
+ assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
+ switch (LoadedVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Invalid PPC load type!");
- case EVT::i64: Opcode = PPC::LDU; break;
- case EVT::i32: Opcode = PPC::LWZU8; break;
- case EVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
- case EVT::i1:
- case EVT::i8: Opcode = PPC::LBZU8; break;
+ case MVT::i64: Opcode = PPC::LDU; break;
+ case MVT::i32: Opcode = PPC::LWZU8; break;
+ case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
+ case MVT::i1:
+ case MVT::i8: Opcode = PPC::LBZU8; break;
}
}
@@ -963,7 +963,7 @@
// FIXME: PPC64
return CurDAG->getTargetNode(Opcode, dl, LD->getValueType(0),
PPCLowering.getPointerTy(),
- EVT::Other, Ops, 3);
+ MVT::Other, Ops, 3);
} else {
llvm_unreachable("R+R preindex loads not supported yet!");
}
@@ -978,7 +978,7 @@
isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
SDValue Val = N->getOperand(0).getOperand(0);
SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4);
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
// If this is just a masked value where the input is not handled above, and
// is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
@@ -987,7 +987,7 @@
N->getOperand(0).getOpcode() != ISD::ROTL) {
SDValue Val = N->getOperand(0);
SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4);
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
// AND X, 0 -> 0, not "rlwinm 32".
if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
@@ -1005,7 +1005,7 @@
SDValue Ops[] = { N->getOperand(0).getOperand(0),
N->getOperand(0).getOperand(1),
getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
- return CurDAG->getTargetNode(PPC::RLWIMI, dl, EVT::i32, Ops, 5);
+ return CurDAG->getTargetNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
}
}
@@ -1013,7 +1013,7 @@
break;
}
case ISD::OR:
- if (N->getValueType(0) == EVT::i32)
+ if (N->getValueType(0) == MVT::i32)
if (SDNode *I = SelectBitfieldInsert(N))
return I;
@@ -1025,7 +1025,7 @@
isRotateAndMask(N, Imm, true, SH, MB, ME)) {
SDValue Ops[] = { N->getOperand(0).getOperand(0),
getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4);
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
// Other cases are autogenerated.
@@ -1037,7 +1037,7 @@
isRotateAndMask(N, Imm, true, SH, MB, ME)) {
SDValue Ops[] = { N->getOperand(0).getOperand(0),
getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4);
+ return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
// Other cases are autogenerated.
@@ -1053,11 +1053,11 @@
if (N1C->isNullValue() && N3C->isNullValue() &&
N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
// FIXME: Implement this optzn for PPC64.
- N->getValueType(0) == EVT::i32) {
+ N->getValueType(0) == MVT::i32) {
SDNode *Tmp =
- CurDAG->getTargetNode(PPC::ADDIC, dl, EVT::i32, EVT::Flag,
+ CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
N->getOperand(0), getI32Imm(~0U));
- return CurDAG->SelectNodeTo(N, PPC::SUBFE, EVT::i32,
+ return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
SDValue(Tmp, 0), N->getOperand(0),
SDValue(Tmp, 1));
}
@@ -1066,13 +1066,13 @@
unsigned BROpc = getPredicateForSetCC(CC);
unsigned SelectCCOp;
- if (N->getValueType(0) == EVT::i32)
+ if (N->getValueType(0) == MVT::i32)
SelectCCOp = PPC::SELECT_CC_I4;
- else if (N->getValueType(0) == EVT::i64)
+ else if (N->getValueType(0) == MVT::i64)
SelectCCOp = PPC::SELECT_CC_I8;
- else if (N->getValueType(0) == EVT::f32)
+ else if (N->getValueType(0) == MVT::f32)
SelectCCOp = PPC::SELECT_CC_F4;
- else if (N->getValueType(0) == EVT::f64)
+ else if (N->getValueType(0) == MVT::f64)
SelectCCOp = PPC::SELECT_CC_F8;
else
SelectCCOp = PPC::SELECT_CC_VRRC;
@@ -1092,23 +1092,23 @@
getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
N->getOperand(0), N->getOperand(4) };
- return CurDAG->SelectNodeTo(N, PPC::BCC, EVT::Other, Ops, 5);
+ return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5);
}
case ISD::BR_CC: {
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
N->getOperand(4), N->getOperand(0) };
- return CurDAG->SelectNodeTo(N, PPC::BCC, EVT::Other, Ops, 4);
+ return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
}
case ISD::BRIND: {
// FIXME: Should custom lower this.
SDValue Chain = N->getOperand(0);
SDValue Target = N->getOperand(1);
- unsigned Opc = Target.getValueType() == EVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
- Chain = SDValue(CurDAG->getTargetNode(Opc, dl, EVT::Other, Target,
+ unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
+ Chain = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Target,
Chain), 0);
- return CurDAG->SelectNodeTo(N, PPC::BCTR, EVT::Other, Chain);
+ return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain);
}
case ISD::DECLARE: {
SDValue Chain = N->getOperand(0);
@@ -1149,7 +1149,7 @@
SDValue Tmp1 = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());
return CurDAG->SelectNodeTo(N, TargetInstrInfo::DECLARE,
- EVT::Other, Tmp1, Tmp2, Chain);
+ MVT::Other, Tmp1, Tmp2, Chain);
}
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Tue Aug 11 15:47:22 2009
@@ -74,216 +74,216 @@
setUseUnderscoreLongJmp(true);
// Set up the register classes.
- addRegisterClass(EVT::i32, PPC::GPRCRegisterClass);
- addRegisterClass(EVT::f32, PPC::F4RCRegisterClass);
- addRegisterClass(EVT::f64, PPC::F8RCRegisterClass);
+ addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
+ addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
+ addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
// PowerPC has an i16 but no i8 (or i1) SEXTLOAD
- setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::SEXTLOAD, EVT::i8, Expand);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
- setTruncStoreAction(EVT::f64, EVT::f32, Expand);
+ setTruncStoreAction(MVT::f64, MVT::f32, Expand);
// PowerPC has pre-inc load and store's.
- setIndexedLoadAction(ISD::PRE_INC, EVT::i1, Legal);
- setIndexedLoadAction(ISD::PRE_INC, EVT::i8, Legal);
- setIndexedLoadAction(ISD::PRE_INC, EVT::i16, Legal);
- setIndexedLoadAction(ISD::PRE_INC, EVT::i32, Legal);
- setIndexedLoadAction(ISD::PRE_INC, EVT::i64, Legal);
- setIndexedStoreAction(ISD::PRE_INC, EVT::i1, Legal);
- setIndexedStoreAction(ISD::PRE_INC, EVT::i8, Legal);
- setIndexedStoreAction(ISD::PRE_INC, EVT::i16, Legal);
- setIndexedStoreAction(ISD::PRE_INC, EVT::i32, Legal);
- setIndexedStoreAction(ISD::PRE_INC, EVT::i64, Legal);
+ setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
+ setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
+ setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
+ setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
+ setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
+ setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
+ setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
+ setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
+ setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
+ setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
// This is used in the ppcf128->int sequence. Note it has different semantics
// from FP_ROUND: that rounds to nearest, this rounds to zero.
- setOperationAction(ISD::FP_ROUND_INREG, EVT::ppcf128, Custom);
+ setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
// PowerPC has no SREM/UREM instructions
- setOperationAction(ISD::SREM, EVT::i32, Expand);
- setOperationAction(ISD::UREM, EVT::i32, Expand);
- setOperationAction(ISD::SREM, EVT::i64, Expand);
- setOperationAction(ISD::UREM, EVT::i64, Expand);
+ setOperationAction(ISD::SREM, MVT::i32, Expand);
+ setOperationAction(ISD::UREM, MVT::i32, Expand);
+ setOperationAction(ISD::SREM, MVT::i64, Expand);
+ setOperationAction(ISD::UREM, MVT::i64, Expand);
// Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
- setOperationAction(ISD::UMUL_LOHI, EVT::i32, Expand);
- setOperationAction(ISD::SMUL_LOHI, EVT::i32, Expand);
- setOperationAction(ISD::UMUL_LOHI, EVT::i64, Expand);
- setOperationAction(ISD::SMUL_LOHI, EVT::i64, Expand);
- setOperationAction(ISD::UDIVREM, EVT::i32, Expand);
- setOperationAction(ISD::SDIVREM, EVT::i32, Expand);
- setOperationAction(ISD::UDIVREM, EVT::i64, Expand);
- setOperationAction(ISD::SDIVREM, EVT::i64, Expand);
+ setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
+ setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
+ setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
+ setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
+ setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
+ setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
+ setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
+ setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
// We don't support sin/cos/sqrt/fmod/pow
- setOperationAction(ISD::FSIN , EVT::f64, Expand);
- setOperationAction(ISD::FCOS , EVT::f64, Expand);
- setOperationAction(ISD::FREM , EVT::f64, Expand);
- setOperationAction(ISD::FPOW , EVT::f64, Expand);
- setOperationAction(ISD::FSIN , EVT::f32, Expand);
- setOperationAction(ISD::FCOS , EVT::f32, Expand);
- setOperationAction(ISD::FREM , EVT::f32, Expand);
- setOperationAction(ISD::FPOW , EVT::f32, Expand);
+ setOperationAction(ISD::FSIN , MVT::f64, Expand);
+ setOperationAction(ISD::FCOS , MVT::f64, Expand);
+ setOperationAction(ISD::FREM , MVT::f64, Expand);
+ setOperationAction(ISD::FPOW , MVT::f64, Expand);
+ setOperationAction(ISD::FSIN , MVT::f32, Expand);
+ setOperationAction(ISD::FCOS , MVT::f32, Expand);
+ setOperationAction(ISD::FREM , MVT::f32, Expand);
+ setOperationAction(ISD::FPOW , MVT::f32, Expand);
- setOperationAction(ISD::FLT_ROUNDS_, EVT::i32, Custom);
+ setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
// If we're enabling GP optimizations, use hardware square root
if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
- setOperationAction(ISD::FSQRT, EVT::f64, Expand);
- setOperationAction(ISD::FSQRT, EVT::f32, Expand);
+ setOperationAction(ISD::FSQRT, MVT::f64, Expand);
+ setOperationAction(ISD::FSQRT, MVT::f32, Expand);
}
- setOperationAction(ISD::FCOPYSIGN, EVT::f64, Expand);
- setOperationAction(ISD::FCOPYSIGN, EVT::f32, Expand);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
// PowerPC does not have BSWAP, CTPOP or CTTZ
- setOperationAction(ISD::BSWAP, EVT::i32 , Expand);
- setOperationAction(ISD::CTPOP, EVT::i32 , Expand);
- setOperationAction(ISD::CTTZ , EVT::i32 , Expand);
- setOperationAction(ISD::BSWAP, EVT::i64 , Expand);
- setOperationAction(ISD::CTPOP, EVT::i64 , Expand);
- setOperationAction(ISD::CTTZ , EVT::i64 , Expand);
+ setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
+ setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
+ setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
+ setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
+ setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
+ setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
// PowerPC does not have ROTR
- setOperationAction(ISD::ROTR, EVT::i32 , Expand);
- setOperationAction(ISD::ROTR, EVT::i64 , Expand);
+ setOperationAction(ISD::ROTR, MVT::i32 , Expand);
+ setOperationAction(ISD::ROTR, MVT::i64 , Expand);
// PowerPC does not have Select
- setOperationAction(ISD::SELECT, EVT::i32, Expand);
- setOperationAction(ISD::SELECT, EVT::i64, Expand);
- setOperationAction(ISD::SELECT, EVT::f32, Expand);
- setOperationAction(ISD::SELECT, EVT::f64, Expand);
+ setOperationAction(ISD::SELECT, MVT::i32, Expand);
+ setOperationAction(ISD::SELECT, MVT::i64, Expand);
+ setOperationAction(ISD::SELECT, MVT::f32, Expand);
+ setOperationAction(ISD::SELECT, MVT::f64, Expand);
// PowerPC wants to turn select_cc of FP into fsel when possible.
- setOperationAction(ISD::SELECT_CC, EVT::f32, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::f64, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
// PowerPC wants to optimize integer setcc a bit
- setOperationAction(ISD::SETCC, EVT::i32, Custom);
+ setOperationAction(ISD::SETCC, MVT::i32, Custom);
// PowerPC does not have BRCOND which requires SetCC
- setOperationAction(ISD::BRCOND, EVT::Other, Expand);
+ setOperationAction(ISD::BRCOND, MVT::Other, Expand);
- setOperationAction(ISD::BR_JT, EVT::Other, Expand);
+ setOperationAction(ISD::BR_JT, MVT::Other, Expand);
// PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
- setOperationAction(ISD::FP_TO_SINT, EVT::i32, Custom);
+ setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
// PowerPC does not have [U|S]INT_TO_FP
- setOperationAction(ISD::SINT_TO_FP, EVT::i32, Expand);
- setOperationAction(ISD::UINT_TO_FP, EVT::i32, Expand);
+ setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
+ setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
- setOperationAction(ISD::BIT_CONVERT, EVT::f32, Expand);
- setOperationAction(ISD::BIT_CONVERT, EVT::i32, Expand);
- setOperationAction(ISD::BIT_CONVERT, EVT::i64, Expand);
- setOperationAction(ISD::BIT_CONVERT, EVT::f64, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
// We cannot sextinreg(i1). Expand to shifts.
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
// Support label based line numbers.
- setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand);
+ setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
- setOperationAction(ISD::EXCEPTIONADDR, EVT::i64, Expand);
- setOperationAction(ISD::EHSELECTION, EVT::i64, Expand);
- setOperationAction(ISD::EXCEPTIONADDR, EVT::i32, Expand);
- setOperationAction(ISD::EHSELECTION, EVT::i32, Expand);
+ setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
+ setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
+ setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
+ setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
// We want to legalize GlobalAddress and ConstantPool nodes into the
// appropriate instructions to materialize the address.
- setOperationAction(ISD::GlobalAddress, EVT::i32, Custom);
- setOperationAction(ISD::GlobalTLSAddress, EVT::i32, Custom);
- setOperationAction(ISD::ConstantPool, EVT::i32, Custom);
- setOperationAction(ISD::JumpTable, EVT::i32, Custom);
- setOperationAction(ISD::GlobalAddress, EVT::i64, Custom);
- setOperationAction(ISD::GlobalTLSAddress, EVT::i64, Custom);
- setOperationAction(ISD::ConstantPool, EVT::i64, Custom);
- setOperationAction(ISD::JumpTable, EVT::i64, Custom);
+ setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
+ setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
+ setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
+ setOperationAction(ISD::JumpTable, MVT::i32, Custom);
+ setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
+ setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
+ setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
+ setOperationAction(ISD::JumpTable, MVT::i64, Custom);
// TRAP is legal.
- setOperationAction(ISD::TRAP, EVT::Other, Legal);
+ setOperationAction(ISD::TRAP, MVT::Other, Legal);
// TRAMPOLINE is custom lowered.
- setOperationAction(ISD::TRAMPOLINE, EVT::Other, Custom);
+ setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
// VASTART needs to be custom lowered to use the VarArgsFrameIndex
- setOperationAction(ISD::VASTART , EVT::Other, Custom);
+ setOperationAction(ISD::VASTART , MVT::Other, Custom);
// VAARG is custom lowered with the SVR4 ABI
if (TM.getSubtarget<PPCSubtarget>().isSVR4ABI())
- setOperationAction(ISD::VAARG, EVT::Other, Custom);
+ setOperationAction(ISD::VAARG, MVT::Other, Custom);
else
- setOperationAction(ISD::VAARG, EVT::Other, Expand);
+ setOperationAction(ISD::VAARG, MVT::Other, Expand);
// Use the default implementation.
- setOperationAction(ISD::VACOPY , EVT::Other, Expand);
- setOperationAction(ISD::VAEND , EVT::Other, Expand);
- setOperationAction(ISD::STACKSAVE , EVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE , EVT::Other, Custom);
- setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32 , Custom);
- setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i64 , Custom);
+ setOperationAction(ISD::VACOPY , MVT::Other, Expand);
+ setOperationAction(ISD::VAEND , MVT::Other, Expand);
+ setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
// We want to custom lower some of our intrinsics.
- setOperationAction(ISD::INTRINSIC_WO_CHAIN, EVT::Other, Custom);
+ setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
// Comparisons that require checking two conditions.
- setCondCodeAction(ISD::SETULT, EVT::f32, Expand);
- setCondCodeAction(ISD::SETULT, EVT::f64, Expand);
- setCondCodeAction(ISD::SETUGT, EVT::f32, Expand);
- setCondCodeAction(ISD::SETUGT, EVT::f64, Expand);
- setCondCodeAction(ISD::SETUEQ, EVT::f32, Expand);
- setCondCodeAction(ISD::SETUEQ, EVT::f64, Expand);
- setCondCodeAction(ISD::SETOGE, EVT::f32, Expand);
- setCondCodeAction(ISD::SETOGE, EVT::f64, Expand);
- setCondCodeAction(ISD::SETOLE, EVT::f32, Expand);
- setCondCodeAction(ISD::SETOLE, EVT::f64, Expand);
- setCondCodeAction(ISD::SETONE, EVT::f32, Expand);
- setCondCodeAction(ISD::SETONE, EVT::f64, Expand);
+ setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
+ setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
+ setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
+ setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
+ setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
+ setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
+ setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
+ setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
+ setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
+ setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
+ setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
+ setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
// They also have instructions for converting between i64 and fp.
- setOperationAction(ISD::FP_TO_SINT, EVT::i64, Custom);
- setOperationAction(ISD::FP_TO_UINT, EVT::i64, Expand);
- setOperationAction(ISD::SINT_TO_FP, EVT::i64, Custom);
- setOperationAction(ISD::UINT_TO_FP, EVT::i64, Expand);
+ setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
+ setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
+ setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
// This is just the low 32 bits of a (signed) fp->i64 conversion.
// We cannot do this with Promote because i64 is not a legal type.
- setOperationAction(ISD::FP_TO_UINT, EVT::i32, Custom);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
// FIXME: disable this lowered code. This generates 64-bit register values,
// and we don't model the fact that the top part is clobbered by calls. We
// need to flag these together so that the value isn't live across a call.
- //setOperationAction(ISD::SINT_TO_FP, EVT::i32, Custom);
+ //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
} else {
// PowerPC does not have FP_TO_UINT on 32-bit implementations.
- setOperationAction(ISD::FP_TO_UINT, EVT::i32, Expand);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
}
if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
// 64-bit PowerPC implementations can support i64 types directly
- addRegisterClass(EVT::i64, PPC::G8RCRegisterClass);
+ addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
// BUILD_PAIR can't be handled natively, and should be expanded to shl/or
- setOperationAction(ISD::BUILD_PAIR, EVT::i64, Expand);
+ setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
// 64-bit PowerPC wants to expand i128 shifts itself.
- setOperationAction(ISD::SHL_PARTS, EVT::i64, Custom);
- setOperationAction(ISD::SRA_PARTS, EVT::i64, Custom);
- setOperationAction(ISD::SRL_PARTS, EVT::i64, Custom);
+ setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
+ setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
+ setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
} else {
// 32-bit PowerPC wants to expand i64 shifts itself.
- setOperationAction(ISD::SHL_PARTS, EVT::i32, Custom);
- setOperationAction(ISD::SRA_PARTS, EVT::i32, Custom);
- setOperationAction(ISD::SRL_PARTS, EVT::i32, Custom);
+ setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
+ setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
+ setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
}
if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
// First set operation action for all vector types to expand. Then we
// will selectively turn on ones that can be effectively codegen'd.
- for (unsigned i = (unsigned)EVT::FIRST_VECTOR_VALUETYPE;
- i <= (unsigned)EVT::LAST_VECTOR_VALUETYPE; ++i) {
- EVT::SimpleValueType VT = (EVT::SimpleValueType)i;
+ for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
+ i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
+ MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
// add/sub are legal for all supported vector VT's.
setOperationAction(ISD::ADD , VT, Legal);
@@ -291,21 +291,21 @@
// We promote all shuffles to v16i8.
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
- AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, EVT::v16i8);
+ AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
// We promote all non-typed operations to v4i32.
setOperationAction(ISD::AND , VT, Promote);
- AddPromotedToType (ISD::AND , VT, EVT::v4i32);
+ AddPromotedToType (ISD::AND , VT, MVT::v4i32);
setOperationAction(ISD::OR , VT, Promote);
- AddPromotedToType (ISD::OR , VT, EVT::v4i32);
+ AddPromotedToType (ISD::OR , VT, MVT::v4i32);
setOperationAction(ISD::XOR , VT, Promote);
- AddPromotedToType (ISD::XOR , VT, EVT::v4i32);
+ AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
setOperationAction(ISD::LOAD , VT, Promote);
- AddPromotedToType (ISD::LOAD , VT, EVT::v4i32);
+ AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
setOperationAction(ISD::SELECT, VT, Promote);
- AddPromotedToType (ISD::SELECT, VT, EVT::v4i32);
+ AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
setOperationAction(ISD::STORE, VT, Promote);
- AddPromotedToType (ISD::STORE, VT, EVT::v4i32);
+ AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
// No other operations are legal.
setOperationAction(ISD::MUL , VT, Expand);
@@ -331,35 +331,35 @@
// We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
// with merges, splats, etc.
- setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v16i8, Custom);
+ setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
- setOperationAction(ISD::AND , EVT::v4i32, Legal);
- setOperationAction(ISD::OR , EVT::v4i32, Legal);
- setOperationAction(ISD::XOR , EVT::v4i32, Legal);
- setOperationAction(ISD::LOAD , EVT::v4i32, Legal);
- setOperationAction(ISD::SELECT, EVT::v4i32, Expand);
- setOperationAction(ISD::STORE , EVT::v4i32, Legal);
-
- addRegisterClass(EVT::v4f32, PPC::VRRCRegisterClass);
- addRegisterClass(EVT::v4i32, PPC::VRRCRegisterClass);
- addRegisterClass(EVT::v8i16, PPC::VRRCRegisterClass);
- addRegisterClass(EVT::v16i8, PPC::VRRCRegisterClass);
-
- setOperationAction(ISD::MUL, EVT::v4f32, Legal);
- setOperationAction(ISD::MUL, EVT::v4i32, Custom);
- setOperationAction(ISD::MUL, EVT::v8i16, Custom);
- setOperationAction(ISD::MUL, EVT::v16i8, Custom);
-
- setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v4f32, Custom);
- setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v4i32, Custom);
-
- setOperationAction(ISD::BUILD_VECTOR, EVT::v16i8, Custom);
- setOperationAction(ISD::BUILD_VECTOR, EVT::v8i16, Custom);
- setOperationAction(ISD::BUILD_VECTOR, EVT::v4i32, Custom);
- setOperationAction(ISD::BUILD_VECTOR, EVT::v4f32, Custom);
+ setOperationAction(ISD::AND , MVT::v4i32, Legal);
+ setOperationAction(ISD::OR , MVT::v4i32, Legal);
+ setOperationAction(ISD::XOR , MVT::v4i32, Legal);
+ setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
+ setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
+ setOperationAction(ISD::STORE , MVT::v4i32, Legal);
+
+ addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
+ addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
+ addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
+ addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
+
+ setOperationAction(ISD::MUL, MVT::v4f32, Legal);
+ setOperationAction(ISD::MUL, MVT::v4i32, Custom);
+ setOperationAction(ISD::MUL, MVT::v8i16, Custom);
+ setOperationAction(ISD::MUL, MVT::v16i8, Custom);
+
+ setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
+ setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
+
+ setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
+ setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
+ setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
+ setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
}
- setShiftAmountType(EVT::i32);
+ setShiftAmountType(MVT::i32);
setBooleanContents(ZeroOrOneBooleanContent);
if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
@@ -449,8 +449,8 @@
}
}
-EVT::SimpleValueType PPCTargetLowering::getSetCCResultType(EVT VT) const {
- return EVT::i32;
+MVT::SimpleValueType PPCTargetLowering::getSetCCResultType(EVT VT) const {
+ return MVT::i32;
}
/// getFunctionAlignment - Return the Log2 alignment of this function.
@@ -523,7 +523,7 @@
///
static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
unsigned LHSStart, unsigned RHSStart) {
- assert(N->getValueType(0) == EVT::v16i8 &&
+ assert(N->getValueType(0) == MVT::v16i8 &&
"PPC only supports shuffles by bytes!");
assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
"Unsupported merge size!");
@@ -561,7 +561,7 @@
/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
/// amount, otherwise return -1.
int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
- assert(N->getValueType(0) == EVT::v16i8 &&
+ assert(N->getValueType(0) == MVT::v16i8 &&
"PPC only supports shuffles by bytes!");
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
@@ -597,7 +597,7 @@
/// specifies a splat of a single element that is suitable for input to
/// VSPLTB/VSPLTH/VSPLTW.
bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
- assert(N->getValueType(0) == EVT::v16i8 &&
+ assert(N->getValueType(0) == MVT::v16i8 &&
(EltSize == 1 || EltSize == 2 || EltSize == 4));
// This is a splat operation if each element of the permute is the same, and
@@ -694,17 +694,17 @@
// Finally, check the least significant entry.
if (LeadingZero) {
if (UniquedVals[Multiple-1].getNode() == 0)
- return DAG.getTargetConstant(0, EVT::i32); // 0,0,0,undef
+ return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
if (Val < 16)
- return DAG.getTargetConstant(Val, EVT::i32); // 0,0,0,4 -> vspltisw(4)
+ return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
}
if (LeadingOnes) {
if (UniquedVals[Multiple-1].getNode() == 0)
- return DAG.getTargetConstant(~0U, EVT::i32); // -1,-1,-1,undef
+ return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
- return DAG.getTargetConstant(Val, EVT::i32);
+ return DAG.getTargetConstant(Val, MVT::i32);
}
return SDValue();
@@ -726,7 +726,7 @@
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
Value = CN->getZExtValue();
} else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
- assert(CN->getValueType(0) == EVT::f32 && "Only one legal FP vector type!");
+ assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
Value = FloatToBits(CN->getValueAPF().convertToFloat());
}
@@ -756,7 +756,7 @@
// Finally, if this value fits in a 5 bit sext field, return it
if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
- return DAG.getTargetConstant(MaskVal, EVT::i32);
+ return DAG.getTargetConstant(MaskVal, MVT::i32);
return SDValue();
}
@@ -773,7 +773,7 @@
return false;
Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
- if (N->getValueType(0) == EVT::i32)
+ if (N->getValueType(0) == MVT::i32)
return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
else
return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
@@ -846,7 +846,7 @@
if (N.getOpcode() == ISD::ADD) {
short imm = 0;
if (isIntS16Immediate(N.getOperand(1), imm)) {
- Disp = DAG.getTargetConstant((int)imm & 0xFFFF, EVT::i32);
+ Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
} else {
@@ -880,7 +880,7 @@
// If all of the bits are known zero on the LHS or RHS, the add won't
// carry.
Base = N.getOperand(0);
- Disp = DAG.getTargetConstant((int)imm & 0xFFFF, EVT::i32);
+ Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
return true;
}
}
@@ -897,15 +897,15 @@
}
// Handle 32-bit sext immediates with LIS + addr mode.
- if (CN->getValueType(0) == EVT::i32 ||
+ if (CN->getValueType(0) == MVT::i32 ||
(int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
int Addr = (int)CN->getZExtValue();
// Otherwise, break this down into an LIS + disp.
- Disp = DAG.getTargetConstant((short)Addr, EVT::i32);
+ Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
- Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, EVT::i32);
- unsigned Opc = CN->getValueType(0) == EVT::i32 ? PPC::LIS : PPC::LIS8;
+ Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
+ unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base), 0);
return true;
}
@@ -960,7 +960,7 @@
if (N.getOpcode() == ISD::ADD) {
short imm = 0;
if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
- Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, EVT::i32);
+ Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
} else {
@@ -993,7 +993,7 @@
// If all of the bits are known zero on the LHS or RHS, the add won't
// carry.
Base = N.getOperand(0);
- Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, EVT::i32);
+ Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
return true;
}
}
@@ -1010,14 +1010,14 @@
}
// Fold the low-part of 32-bit absolute addresses into addr mode.
- if (CN->getValueType(0) == EVT::i32 ||
+ if (CN->getValueType(0) == MVT::i32 ||
(int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
int Addr = (int)CN->getZExtValue();
// Otherwise, break this down into an LIS + disp.
- Disp = DAG.getTargetConstant((short)Addr >> 2, EVT::i32);
- Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, EVT::i32);
- unsigned Opc = CN->getValueType(0) == EVT::i32 ? PPC::LIS : PPC::LIS8;
+ Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
+ Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
+ unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base),0);
return true;
}
@@ -1063,7 +1063,7 @@
// TODO: Check reg+reg first.
// LDU/STU use reg+imm*4, others use reg+imm.
- if (VT != EVT::i64) {
+ if (VT != MVT::i64) {
// reg + imm
if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
return false;
@@ -1076,7 +1076,7 @@
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
// PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
// sext i32 to i64 when addr mode is r+i.
- if (LD->getValueType(0) == EVT::i64 && LD->getMemoryVT() == EVT::i32 &&
+ if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
LD->getExtensionType() == ISD::SEXTLOAD &&
isa<ConstantSDNode>(Offset))
return false;
@@ -1216,15 +1216,15 @@
if (C->isNullValue() && CC == ISD::SETEQ) {
EVT VT = Op.getOperand(0).getValueType();
SDValue Zext = Op.getOperand(0);
- if (VT.bitsLT(EVT::i32)) {
- VT = EVT::i32;
+ if (VT.bitsLT(MVT::i32)) {
+ VT = MVT::i32;
Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
}
unsigned Log2b = Log2_32(VT.getSizeInBits());
SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
- DAG.getConstant(Log2b, EVT::i32));
- return DAG.getNode(ISD::TRUNCATE, dl, EVT::i32, Scc);
+ DAG.getConstant(Log2b, MVT::i32));
+ return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
}
// Leave comparisons against 0 and -1 alone for now, since they're usually
// optimized. FIXME: revisit this when we can custom lower all setcc
@@ -1267,7 +1267,7 @@
DebugLoc dl = Op.getDebugLoc();
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
- bool isPPC64 = (PtrVT == EVT::i64);
+ bool isPPC64 = (PtrVT == MVT::i64);
const Type *IntPtrTy =
DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType();
@@ -1279,7 +1279,7 @@
// TrampSize == (isPPC64 ? 48 : 40);
Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
- isPPC64 ? EVT::i64 : EVT::i32);
+ isPPC64 ? MVT::i64 : MVT::i32);
Args.push_back(Entry);
Entry.Node = FPtr; Args.push_back(Entry);
@@ -1341,8 +1341,8 @@
// } va_list[1];
- SDValue ArgGPR = DAG.getConstant(VarArgsNumGPR, EVT::i32);
- SDValue ArgFPR = DAG.getConstant(VarArgsNumFPR, EVT::i32);
+ SDValue ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i32);
+ SDValue ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i32);
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
@@ -1363,14 +1363,14 @@
// Store first byte : number of int regs
SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
- Op.getOperand(1), SV, 0, EVT::i8);
+ Op.getOperand(1), SV, 0, MVT::i8);
uint64_t nextOffset = FPROffset;
SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
ConstFPROffset);
// Store second byte : number of float regs
SDValue secondStore =
- DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset, EVT::i8);
+ DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset, MVT::i8);
nextOffset += StackOffset;
nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
@@ -1559,22 +1559,22 @@
TargetRegisterClass *RC;
EVT ValVT = VA.getValVT();
- switch (ValVT.getSimpleVT()) {
+ switch (ValVT.getSimpleVT().SimpleTy) {
default:
llvm_unreachable("ValVT not supported by formal arguments Lowering");
- case EVT::i32:
+ case MVT::i32:
RC = PPC::GPRCRegisterClass;
break;
- case EVT::f32:
+ case MVT::f32:
RC = PPC::F4RCRegisterClass;
break;
- case EVT::f64:
+ case MVT::f64:
RC = PPC::F8RCRegisterClass;
break;
- case EVT::v16i8:
- case EVT::v8i16:
- case EVT::v4i32:
- case EVT::v4f32:
+ case MVT::v16i8:
+ case MVT::v8i16:
+ case MVT::v4i32:
+ case MVT::v4f32:
RC = PPC::VRRCRegisterClass;
break;
}
@@ -1652,7 +1652,7 @@
// Make room for NumGPArgRegs and NumFPArgRegs.
int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
- NumFPArgRegs * EVT(EVT::f64).getSizeInBits()/8;
+ NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
VarArgsStackOffset = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
CCInfo.getNextStackOffset());
@@ -1693,11 +1693,11 @@
// on the stack.
unsigned FPRIndex = 0;
for (FPRIndex = 0; FPRIndex != VarArgsNumFPR; ++FPRIndex) {
- SDValue Val = DAG.getRegister(FPArgRegs[FPRIndex], EVT::f64);
+ SDValue Val = DAG.getRegister(FPArgRegs[FPRIndex], MVT::f64);
SDValue Store = DAG.getStore(Chain, dl, Val, FIN, NULL, 0);
MemOps.push_back(Store);
// Increment the address by eight for the next argument to store
- SDValue PtrOff = DAG.getConstant(EVT(EVT::f64).getSizeInBits()/8,
+ SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
PtrVT);
FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
}
@@ -1705,11 +1705,11 @@
for (; FPRIndex != NumFPArgRegs; ++FPRIndex) {
unsigned VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
- SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, EVT::f64);
+ SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
MemOps.push_back(Store);
// Increment the address by eight for the next argument to store
- SDValue PtrOff = DAG.getConstant(EVT(EVT::f64).getSizeInBits()/8,
+ SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
PtrVT);
FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
}
@@ -1717,7 +1717,7 @@
if (!MemOps.empty())
Chain = DAG.getNode(ISD::TokenFactor, dl,
- EVT::Other, &MemOps[0], MemOps.size());
+ MVT::Other, &MemOps[0], MemOps.size());
return Chain;
}
@@ -1737,7 +1737,7 @@
MachineFrameInfo *MFI = MF.getFrameInfo();
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
- bool isPPC64 = PtrVT == EVT::i64;
+ bool isPPC64 = PtrVT == MVT::i64;
// Potential tail calls could cause overwriting of argument stack slots.
bool isImmutable = !(PerformTailCallOpt && (CallConv==CallingConv::Fast));
unsigned PtrByteSize = isPPC64 ? 8 : 4;
@@ -1794,20 +1794,20 @@
continue;
}
- switch(ObjectVT.getSimpleVT()) {
+ switch(ObjectVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unhandled argument type!");
- case EVT::i32:
- case EVT::f32:
+ case MVT::i32:
+ case MVT::f32:
VecArgOffset += isPPC64 ? 8 : 4;
break;
- case EVT::i64: // PPC64
- case EVT::f64:
+ case MVT::i64: // PPC64
+ case MVT::f64:
VecArgOffset += 8;
break;
- case EVT::v4f32:
- case EVT::v4i32:
- case EVT::v8i16:
- case EVT::v16i8:
+ case MVT::v4f32:
+ case MVT::v4i32:
+ case MVT::v8i16:
+ case MVT::v16i8:
// Nothing to do, we're only looking at Nonvector args here.
break;
}
@@ -1835,8 +1835,8 @@
unsigned CurArgOffset = ArgOffset;
// Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
- if (ObjectVT==EVT::v4f32 || ObjectVT==EVT::v4i32 ||
- ObjectVT==EVT::v8i16 || ObjectVT==EVT::v16i8) {
+ if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
+ ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
if (isVarArg || isPPC64) {
MinReservedArea = ((MinReservedArea+15)/16)*16;
MinReservedArea += CalculateStackSlotSize(ObjectVT,
@@ -1869,7 +1869,7 @@
unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
- NULL, 0, ObjSize==1 ? EVT::i8 : EVT::i16 );
+ NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 );
MemOps.push_back(Store);
++GPR_idx;
}
@@ -1899,13 +1899,13 @@
continue;
}
- switch (ObjectVT.getSimpleVT()) {
+ switch (ObjectVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unhandled argument type!");
- case EVT::i32:
+ case MVT::i32:
if (!isPPC64) {
if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
- ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, EVT::i32);
+ ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
++GPR_idx;
} else {
needsLoad = true;
@@ -1916,22 +1916,22 @@
break;
}
// FALLTHROUGH
- case EVT::i64: // PPC64
+ case MVT::i64: // PPC64
if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
- ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, EVT::i64);
+ ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
- if (ObjectVT == EVT::i32) {
+ if (ObjectVT == MVT::i32) {
// PPC64 passes i8, i16, and i32 values in i64 registers. Promote
- // value to EVT::i64 and then truncate to the correct register size.
+ // value to MVT::i64 and then truncate to the correct register size.
if (Flags.isSExt())
- ArgVal = DAG.getNode(ISD::AssertSext, dl, EVT::i64, ArgVal,
+ ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
DAG.getValueType(ObjectVT));
else if (Flags.isZExt())
- ArgVal = DAG.getNode(ISD::AssertZext, dl, EVT::i64, ArgVal,
+ ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
DAG.getValueType(ObjectVT));
- ArgVal = DAG.getNode(ISD::TRUNCATE, dl, EVT::i32, ArgVal);
+ ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
}
++GPR_idx;
@@ -1943,8 +1943,8 @@
ArgOffset += 8;
break;
- case EVT::f32:
- case EVT::f64:
+ case MVT::f32:
+ case MVT::f64:
// Every 4 bytes of argument space consumes one of the GPRs available for
// argument passing.
if (GPR_idx != Num_GPR_Regs) {
@@ -1955,7 +1955,7 @@
if (FPR_idx != Num_FPR_Regs) {
unsigned VReg;
- if (ObjectVT == EVT::f32)
+ if (ObjectVT == MVT::f32)
VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
else
VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
@@ -1969,10 +1969,10 @@
// All FP arguments reserve stack space in the Darwin ABI.
ArgOffset += isPPC64 ? 8 : ObjSize;
break;
- case EVT::v4f32:
- case EVT::v4i32:
- case EVT::v8i16:
- case EVT::v16i8:
+ case MVT::v4f32:
+ case MVT::v4i32:
+ case MVT::v8i16:
+ case MVT::v16i8:
// Note that vector arguments in registers don't reserve stack space,
// except in varargs functions.
if (VR_idx != Num_VR_Regs) {
@@ -2067,7 +2067,7 @@
if (!MemOps.empty())
Chain = DAG.getNode(ISD::TokenFactor, dl,
- EVT::Other, &MemOps[0], MemOps.size());
+ MVT::Other, &MemOps[0], MemOps.size());
return Chain;
}
@@ -2101,8 +2101,8 @@
ISD::ArgFlagsTy Flags = Outs[i].Flags;
EVT ArgVT = Arg.getValueType();
// Varargs Altivec parameters are padded to a 16 byte boundary.
- if (ArgVT==EVT::v4f32 || ArgVT==EVT::v4i32 ||
- ArgVT==EVT::v8i16 || ArgVT==EVT::v16i8) {
+ if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
+ ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
if (!isVarArg && !isPPC64) {
// Non-varargs Altivec parameters go after all the non-Altivec
// parameters; handle those later so we know how much padding we need.
@@ -2256,7 +2256,7 @@
isDarwinABI);
int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
NewRetAddrLoc);
- EVT VT = isPPC64 ? EVT::i64 : EVT::i32;
+ EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
PseudoSourceValue::getFixedStack(NewRetAddr), 0);
@@ -2284,7 +2284,7 @@
int Offset = ArgOffset + SPDiff;
uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
- EVT VT = isPPC64 ? EVT::i64 : EVT::i32;
+ EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
SDValue FIN = DAG.getFrameIndex(FI, VT);
TailCallArgumentInfo Info;
Info.Arg = Arg;
@@ -2305,7 +2305,7 @@
DebugLoc dl) {
if (SPDiff) {
// Load the LR and FP stack slot for later adjusting.
- EVT VT = PPCSubTarget.isPPC64() ? EVT::i64 : EVT::i32;
+ EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
LROpOut = getReturnAddrFrameIndex(DAG);
LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, NULL, 0);
Chain = SDValue(LROpOut.getNode(), 1);
@@ -2331,7 +2331,7 @@
CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
DebugLoc dl) {
- SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), EVT::i32);
+ SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
false, NULL, 0, NULL, 0);
}
@@ -2350,9 +2350,9 @@
if (isVector) {
SDValue StackPtr;
if (isPPC64)
- StackPtr = DAG.getRegister(PPC::X1, EVT::i64);
+ StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
else
- StackPtr = DAG.getRegister(PPC::R1, EVT::i32);
+ StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
DAG.getConstant(ArgOffset, PtrVT));
}
@@ -2377,7 +2377,7 @@
StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
MemOpChains2, dl);
if (!MemOpChains2.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains2[0], MemOpChains2.size());
// Store the return address to the appropriate stack slot.
@@ -2397,8 +2397,8 @@
SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
bool isSVR4ABI) {
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
- NodeTys.push_back(EVT::Other); // Returns a chain
- NodeTys.push_back(EVT::Flag); // Returns a flag for retval copy to use.
+ NodeTys.push_back(MVT::Other); // Returns a chain
+ NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin;
@@ -2421,8 +2421,8 @@
InFlag = Chain.getValue(1);
NodeTys.clear();
- NodeTys.push_back(EVT::Other);
- NodeTys.push_back(EVT::Flag);
+ NodeTys.push_back(MVT::Other);
+ NodeTys.push_back(MVT::Flag);
Ops.push_back(Chain);
CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin;
Callee.setNode(0);
@@ -2438,7 +2438,7 @@
}
// If this is a tail call add stack pointer delta.
if (isTailCall)
- Ops.push_back(DAG.getConstant(SPDiff, EVT::i32));
+ Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
// Add argument registers to the end of the list so that they are known live
// into the call.
@@ -2522,7 +2522,7 @@
isa<ConstantSDNode>(Callee)) &&
"Expecting an global address, external symbol, absolute value or register");
- return DAG.getNode(PPCISD::TC_RETURN, dl, EVT::Other, &Ops[0], Ops.size());
+ return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
}
Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
@@ -2665,7 +2665,7 @@
// Set up a copy of the stack pointer for use loading and storing any
// arguments that may not fit in the registers available for argument
// passing.
- SDValue StackPtr = DAG.getRegister(PPC::R1, EVT::i32);
+ SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
@@ -2737,7 +2737,7 @@
}
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token chain
@@ -2751,7 +2751,7 @@
// Set CR6 to true if this is a vararg call.
if (isVarArg) {
- SDValue SetCR(DAG.getTargetNode(PPC::CRSET, dl, EVT::i32), 0);
+ SDValue SetCR(DAG.getTargetNode(PPC::CRSET, dl, MVT::i32), 0);
Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag);
InFlag = Chain.getValue(1);
}
@@ -2778,7 +2778,7 @@
unsigned NumOps = Outs.size();
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
- bool isPPC64 = PtrVT == EVT::i64;
+ bool isPPC64 = PtrVT == MVT::i64;
unsigned PtrByteSize = isPPC64 ? 8 : 4;
MachineFunction &MF = DAG.getMachineFunction();
@@ -2826,9 +2826,9 @@
// passing.
SDValue StackPtr;
if (isPPC64)
- StackPtr = DAG.getRegister(PPC::X1, EVT::i64);
+ StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
else
- StackPtr = DAG.getRegister(PPC::R1, EVT::i32);
+ StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
// Figure out which arguments are going to go in registers, and which in
// memory. Also, if this is a vararg function, floating point operations
@@ -2875,10 +2875,10 @@
PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
// On PPC64, promote integers to 64-bit values.
- if (isPPC64 && Arg.getValueType() == EVT::i32) {
+ if (isPPC64 && Arg.getValueType() == MVT::i32) {
// FIXME: Should this use ANY_EXTEND if neither sext nor zext?
unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
- Arg = DAG.getNode(ExtOp, dl, EVT::i64, Arg);
+ Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
}
// FIXME memcpy is used way more than necessary. Correctness first.
@@ -2887,7 +2887,7 @@
if (Size==1 || Size==2) {
// Very small objects are passed right-justified.
// Everything else is passed left-justified.
- EVT VT = (Size==1) ? EVT::i8 : EVT::i16;
+ EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
if (GPR_idx != NumGPRs) {
SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
NULL, 0, VT);
@@ -2939,10 +2939,10 @@
continue;
}
- switch (Arg.getValueType().getSimpleVT()) {
+ switch (Arg.getValueType().getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unexpected ValueType for argument!");
- case EVT::i32:
- case EVT::i64:
+ case MVT::i32:
+ case MVT::i64:
if (GPR_idx != NumGPRs) {
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
} else {
@@ -2953,8 +2953,8 @@
}
ArgOffset += PtrByteSize;
break;
- case EVT::f32:
- case EVT::f64:
+ case MVT::f32:
+ case MVT::f64:
if (FPR_idx != NumFPRs) {
RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
@@ -2968,7 +2968,7 @@
MemOpChains.push_back(Load.getValue(1));
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
}
- if (GPR_idx != NumGPRs && Arg.getValueType() == EVT::f64 && !isPPC64){
+ if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0);
@@ -2981,7 +2981,7 @@
// GPRs.
if (GPR_idx != NumGPRs)
++GPR_idx;
- if (GPR_idx != NumGPRs && Arg.getValueType() == EVT::f64 &&
+ if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
!isPPC64) // PPC64 has 64-bit GPR's obviously :)
++GPR_idx;
}
@@ -2994,12 +2994,12 @@
if (isPPC64)
ArgOffset += 8;
else
- ArgOffset += Arg.getValueType() == EVT::f32 ? 4 : 8;
+ ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
break;
- case EVT::v4f32:
- case EVT::v4i32:
- case EVT::v8i16:
- case EVT::v16i8:
+ case MVT::v4f32:
+ case MVT::v4i32:
+ case MVT::v8i16:
+ case MVT::v16i8:
if (isVarArg) {
// These go aligned on the stack, or in the corresponding R registers
// when within range. The Darwin PPC ABI doc claims they also go in
@@ -3018,7 +3018,7 @@
SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0);
MemOpChains.push_back(Store);
if (VR_idx != NumVRs) {
- SDValue Load = DAG.getLoad(EVT::v4f32, dl, Store, PtrOff, NULL, 0);
+ SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, NULL, 0);
MemOpChains.push_back(Load.getValue(1));
RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
}
@@ -3063,8 +3063,8 @@
for (unsigned i = 0; i != NumOps; ++i) {
SDValue Arg = Outs[i].Val;
EVT ArgType = Arg.getValueType();
- if (ArgType==EVT::v4f32 || ArgType==EVT::v4i32 ||
- ArgType==EVT::v8i16 || ArgType==EVT::v16i8) {
+ if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
+ ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
if (++j > NumVRs) {
SDValue PtrOff;
// We are emitting Altivec params in order.
@@ -3078,7 +3078,7 @@
}
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token chain
@@ -3130,9 +3130,9 @@
}
if (Flag.getNode())
- return DAG.getNode(PPCISD::RET_FLAG, dl, EVT::Other, Chain, Flag);
+ return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
else
- return DAG.getNode(PPCISD::RET_FLAG, dl, EVT::Other, Chain);
+ return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain);
}
SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
@@ -3231,7 +3231,7 @@
SDValue FPSIdx = getFramePointerFrameIndex(DAG);
// Build a DYNALLOC node.
SDValue Ops[3] = { Chain, NegSize, FPSIdx };
- SDVTList VTs = DAG.getVTList(PtrVT, EVT::Other);
+ SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
}
@@ -3264,18 +3264,18 @@
std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
case ISD::SETOGE:
case ISD::SETGE:
- if (LHS.getValueType() == EVT::f32) // Comparison is always 64-bits
- LHS = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, LHS);
+ if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
+ LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
case ISD::SETUGT:
case ISD::SETGT:
std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
case ISD::SETOLE:
case ISD::SETLE:
- if (LHS.getValueType() == EVT::f32) // Comparison is always 64-bits
- LHS = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, LHS);
+ if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
+ LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
return DAG.getNode(PPCISD::FSEL, dl, ResVT,
- DAG.getNode(ISD::FNEG, dl, EVT::f64, LHS), TV, FV);
+ DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
}
SDValue Cmp;
@@ -3284,26 +3284,26 @@
case ISD::SETULT:
case ISD::SETLT:
Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
- if (Cmp.getValueType() == EVT::f32) // Comparison is always 64-bits
- Cmp = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, Cmp);
+ if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
+ Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
case ISD::SETOGE:
case ISD::SETGE:
Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
- if (Cmp.getValueType() == EVT::f32) // Comparison is always 64-bits
- Cmp = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, Cmp);
+ if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
+ Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
case ISD::SETUGT:
case ISD::SETGT:
Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
- if (Cmp.getValueType() == EVT::f32) // Comparison is always 64-bits
- Cmp = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, Cmp);
+ if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
+ Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
case ISD::SETOLE:
case ISD::SETLE:
Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
- if (Cmp.getValueType() == EVT::f32) // Comparison is always 64-bits
- Cmp = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, Cmp);
+ if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
+ Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
}
return Op;
@@ -3314,31 +3314,31 @@
DebugLoc dl) {
assert(Op.getOperand(0).getValueType().isFloatingPoint());
SDValue Src = Op.getOperand(0);
- if (Src.getValueType() == EVT::f32)
- Src = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, Src);
+ if (Src.getValueType() == MVT::f32)
+ Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
SDValue Tmp;
- switch (Op.getValueType().getSimpleVT()) {
+ switch (Op.getValueType().getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
- case EVT::i32:
+ case MVT::i32:
Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
PPCISD::FCTIDZ,
- dl, EVT::f64, Src);
+ dl, MVT::f64, Src);
break;
- case EVT::i64:
- Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, EVT::f64, Src);
+ case MVT::i64:
+ Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
break;
}
// Convert the FP value to an int value through memory.
- SDValue FIPtr = DAG.CreateStackTemporary(EVT::f64);
+ SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
// Emit a store to the stack slot.
SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, NULL, 0);
// Result is a load from the stack slot. If loading 4 bytes, make sure to
// add in a bias.
- if (Op.getValueType() == EVT::i32)
+ if (Op.getValueType() == MVT::i32)
FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
DAG.getConstant(4, FIPtr.getValueType()));
return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, NULL, 0);
@@ -3347,20 +3347,20 @@
SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
// Don't handle ppc_fp128 here; let it be lowered to a libcall.
- if (Op.getValueType() != EVT::f32 && Op.getValueType() != EVT::f64)
+ if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
return SDValue();
- if (Op.getOperand(0).getValueType() == EVT::i64) {
+ if (Op.getOperand(0).getValueType() == MVT::i64) {
SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl,
- EVT::f64, Op.getOperand(0));
- SDValue FP = DAG.getNode(PPCISD::FCFID, dl, EVT::f64, Bits);
- if (Op.getValueType() == EVT::f32)
+ MVT::f64, Op.getOperand(0));
+ SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
+ if (Op.getValueType() == MVT::f32)
FP = DAG.getNode(ISD::FP_ROUND, dl,
- EVT::f32, FP, DAG.getIntPtrConstant(0));
+ MVT::f32, FP, DAG.getIntPtrConstant(0));
return FP;
}
- assert(Op.getOperand(0).getValueType() == EVT::i32 &&
+ assert(Op.getOperand(0).getValueType() == MVT::i32 &&
"Unhandled SINT_TO_FP type in custom expander!");
// Since we only generate this in 64-bit mode, we can take advantage of
// 64-bit registers. In particular, sign extend the input value into the
@@ -3371,22 +3371,22 @@
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
- SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, EVT::i32,
+ SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32,
Op.getOperand(0));
// STD the extended value into the stack slot.
MachineMemOperand MO(PseudoSourceValue::getFixedStack(FrameIdx),
MachineMemOperand::MOStore, 0, 8, 8);
- SDValue Store = DAG.getNode(PPCISD::STD_32, dl, EVT::Other,
+ SDValue Store = DAG.getNode(PPCISD::STD_32, dl, MVT::Other,
DAG.getEntryNode(), Ext64, FIdx,
DAG.getMemOperand(MO));
// Load the value as a double.
- SDValue Ld = DAG.getLoad(EVT::f64, dl, Store, FIdx, NULL, 0);
+ SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, NULL, 0);
// FCFID it and return it.
- SDValue FP = DAG.getNode(PPCISD::FCFID, dl, EVT::f64, Ld);
- if (Op.getValueType() == EVT::f32)
- FP = DAG.getNode(ISD::FP_ROUND, dl, EVT::f32, FP, DAG.getIntPtrConstant(0));
+ SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
+ if (Op.getValueType() == MVT::f32)
+ FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
return FP;
}
@@ -3418,8 +3418,8 @@
SDValue MFFSreg, InFlag;
// Save FP Control Word to register
- NodeTys.push_back(EVT::f64); // return register
- NodeTys.push_back(EVT::Flag); // unused in this context
+ NodeTys.push_back(MVT::f64); // return register
+ NodeTys.push_back(MVT::Flag); // unused in this context
SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
// Save FP register to stack slot
@@ -3431,22 +3431,22 @@
// Load FP Control Word from low 32 bits of stack slot.
SDValue Four = DAG.getConstant(4, PtrVT);
SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
- SDValue CWD = DAG.getLoad(EVT::i32, dl, Store, Addr, NULL, 0);
+ SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, NULL, 0);
// Transform as necessary
SDValue CWD1 =
- DAG.getNode(ISD::AND, dl, EVT::i32,
- CWD, DAG.getConstant(3, EVT::i32));
+ DAG.getNode(ISD::AND, dl, MVT::i32,
+ CWD, DAG.getConstant(3, MVT::i32));
SDValue CWD2 =
- DAG.getNode(ISD::SRL, dl, EVT::i32,
- DAG.getNode(ISD::AND, dl, EVT::i32,
- DAG.getNode(ISD::XOR, dl, EVT::i32,
- CWD, DAG.getConstant(3, EVT::i32)),
- DAG.getConstant(3, EVT::i32)),
- DAG.getConstant(1, EVT::i32));
+ DAG.getNode(ISD::SRL, dl, MVT::i32,
+ DAG.getNode(ISD::AND, dl, MVT::i32,
+ DAG.getNode(ISD::XOR, dl, MVT::i32,
+ CWD, DAG.getConstant(3, MVT::i32)),
+ DAG.getConstant(3, MVT::i32)),
+ DAG.getConstant(1, MVT::i32));
SDValue RetVal =
- DAG.getNode(ISD::XOR, dl, EVT::i32, CWD1, CWD2);
+ DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
return DAG.getNode((VT.getSizeInBits() < 16 ?
ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
@@ -3550,10 +3550,10 @@
assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
static const EVT VTys[] = { // canonical VT to use for each size.
- EVT::v16i8, EVT::v8i16, EVT::Other, EVT::v4i32
+ MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
};
- EVT ReqVT = VT != EVT::Other ? VT : VTys[SplatSize-1];
+ EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
// Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
if (Val == -1)
@@ -3562,7 +3562,7 @@
EVT CanonicalVT = VTys[SplatSize-1];
// Build a canonical splat for this value.
- SDValue Elt = DAG.getConstant(Val, EVT::i32);
+ SDValue Elt = DAG.getConstant(Val, MVT::i32);
SmallVector<SDValue, 8> Ops;
Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
@@ -3574,20 +3574,20 @@
/// specified intrinsic ID.
static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
SelectionDAG &DAG, DebugLoc dl,
- EVT DestVT = EVT::Other) {
- if (DestVT == EVT::Other) DestVT = LHS.getValueType();
+ EVT DestVT = MVT::Other) {
+ if (DestVT == MVT::Other) DestVT = LHS.getValueType();
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
- DAG.getConstant(IID, EVT::i32), LHS, RHS);
+ DAG.getConstant(IID, MVT::i32), LHS, RHS);
}
/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
/// specified intrinsic ID.
static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
SDValue Op2, SelectionDAG &DAG,
- DebugLoc dl, EVT DestVT = EVT::Other) {
- if (DestVT == EVT::Other) DestVT = Op0.getValueType();
+ DebugLoc dl, EVT DestVT = MVT::Other) {
+ if (DestVT == MVT::Other) DestVT = Op0.getValueType();
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
- DAG.getConstant(IID, EVT::i32), Op0, Op1, Op2);
+ DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
}
@@ -3596,13 +3596,13 @@
static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
EVT VT, SelectionDAG &DAG, DebugLoc dl) {
// Force LHS/RHS to be the right type.
- LHS = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, LHS);
- RHS = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, RHS);
+ LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, LHS);
+ RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, RHS);
int Ops[16];
for (unsigned i = 0; i != 16; ++i)
Ops[i] = i + Amt;
- SDValue T = DAG.getVectorShuffle(EVT::v16i8, dl, LHS, RHS, Ops);
+ SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
}
@@ -3633,9 +3633,9 @@
// All zeros?
if (SplatBits == 0) {
// Canonicalize all zero vectors to be v4i32.
- if (Op.getValueType() != EVT::v4i32 || HasAnyUndefs) {
- SDValue Z = DAG.getConstant(0, EVT::i32);
- Z = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, Z, Z, Z, Z);
+ if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
+ SDValue Z = DAG.getConstant(0, MVT::i32);
+ Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
Op = DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Z);
}
return Op;
@@ -3653,7 +3653,7 @@
// If this value is in the range [-32,30] and is even, use:
// tmp = VSPLTI[bhw], result = add tmp, tmp
if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
- SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, EVT::Other, DAG, dl);
+ SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl);
Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
}
@@ -3663,14 +3663,14 @@
// for fneg/fabs.
if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
// Make -1 and vspltisw -1:
- SDValue OnesV = BuildSplatI(-1, 4, EVT::v4i32, DAG, dl);
+ SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
// Make the VSLW intrinsic, computing 0x8000_0000.
SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
OnesV, DAG, dl);
// xor by OnesV to invert it.
- Res = DAG.getNode(ISD::XOR, dl, EVT::v4i32, Res, OnesV);
+ Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
}
@@ -3691,7 +3691,7 @@
// vsplti + shl self.
if (SextVal == (i << (int)TypeShiftAmt)) {
- SDValue Res = BuildSplatI(i, SplatSize, EVT::Other, DAG, dl);
+ SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
static const unsigned IIDs[] = { // Intrinsic to use for each size.
Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
Intrinsic::ppc_altivec_vslw
@@ -3702,7 +3702,7 @@
// vsplti + srl self.
if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
- SDValue Res = BuildSplatI(i, SplatSize, EVT::Other, DAG, dl);
+ SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
static const unsigned IIDs[] = { // Intrinsic to use for each size.
Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
Intrinsic::ppc_altivec_vsrw
@@ -3713,7 +3713,7 @@
// vsplti + sra self.
if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
- SDValue Res = BuildSplatI(i, SplatSize, EVT::Other, DAG, dl);
+ SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
static const unsigned IIDs[] = { // Intrinsic to use for each size.
Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
Intrinsic::ppc_altivec_vsraw
@@ -3725,7 +3725,7 @@
// vsplti + rol self.
if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
- SDValue Res = BuildSplatI(i, SplatSize, EVT::Other, DAG, dl);
+ SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
static const unsigned IIDs[] = { // Intrinsic to use for each size.
Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
Intrinsic::ppc_altivec_vrlw
@@ -3736,17 +3736,17 @@
// t = vsplti c, result = vsldoi t, t, 1
if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
- SDValue T = BuildSplatI(i, SplatSize, EVT::v16i8, DAG, dl);
+ SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
}
// t = vsplti c, result = vsldoi t, t, 2
if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
- SDValue T = BuildSplatI(i, SplatSize, EVT::v16i8, DAG, dl);
+ SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
}
// t = vsplti c, result = vsldoi t, t, 3
if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
- SDValue T = BuildSplatI(i, SplatSize, EVT::v16i8, DAG, dl);
+ SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
}
}
@@ -3755,15 +3755,15 @@
// Odd, in range [17,31]: (vsplti C)-(vsplti -16).
if (SextVal >= 0 && SextVal <= 31) {
- SDValue LHS = BuildSplatI(SextVal-16, SplatSize, EVT::Other, DAG, dl);
- SDValue RHS = BuildSplatI(-16, SplatSize, EVT::Other, DAG, dl);
+ SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
+ SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
}
// Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
if (SextVal >= -31 && SextVal <= 0) {
- SDValue LHS = BuildSplatI(SextVal+16, SplatSize, EVT::Other, DAG, dl);
- SDValue RHS = BuildSplatI(-16, SplatSize, EVT::Other, DAG, dl);
+ SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl);
+ SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
}
@@ -3842,9 +3842,9 @@
return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
}
EVT VT = OpLHS.getValueType();
- OpLHS = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, OpLHS);
- OpRHS = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, OpRHS);
- SDValue T = DAG.getVectorShuffle(EVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
+ OpLHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpLHS);
+ OpRHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpRHS);
+ SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
}
@@ -3964,10 +3964,10 @@
for (unsigned j = 0; j != BytesPerElement; ++j)
ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
- EVT::i32));
+ MVT::i32));
}
- SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v16i8,
+ SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
&ResultMask[0], ResultMask.size());
return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
}
@@ -4032,7 +4032,7 @@
if (!isDot) {
SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
Op.getOperand(1), Op.getOperand(2),
- DAG.getConstant(CompareOpc, EVT::i32));
+ DAG.getConstant(CompareOpc, MVT::i32));
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Tmp);
}
@@ -4040,17 +4040,17 @@
SDValue Ops[] = {
Op.getOperand(2), // LHS
Op.getOperand(3), // RHS
- DAG.getConstant(CompareOpc, EVT::i32)
+ DAG.getConstant(CompareOpc, MVT::i32)
};
std::vector<EVT> VTs;
VTs.push_back(Op.getOperand(2).getValueType());
- VTs.push_back(EVT::Flag);
+ VTs.push_back(MVT::Flag);
SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
// Now that we have the comparison, emit a copy from the CR to a GPR.
// This is flagged to the above dot comparison.
- SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, EVT::i32,
- DAG.getRegister(PPC::CR6, EVT::i32),
+ SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
+ DAG.getRegister(PPC::CR6, MVT::i32),
CompNode.getValue(1));
// Unpack the result based on how the target uses it.
@@ -4073,16 +4073,16 @@
}
// Shift the bit into the low position.
- Flags = DAG.getNode(ISD::SRL, dl, EVT::i32, Flags,
- DAG.getConstant(8-(3-BitNo), EVT::i32));
+ Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
+ DAG.getConstant(8-(3-BitNo), MVT::i32));
// Isolate the bit.
- Flags = DAG.getNode(ISD::AND, dl, EVT::i32, Flags,
- DAG.getConstant(1, EVT::i32));
+ Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
+ DAG.getConstant(1, MVT::i32));
// If we are supposed to, toggle the bit.
if (InvertBit)
- Flags = DAG.getNode(ISD::XOR, dl, EVT::i32, Flags,
- DAG.getConstant(1, EVT::i32));
+ Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
+ DAG.getConstant(1, MVT::i32));
return Flags;
}
@@ -4104,50 +4104,50 @@
SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
- if (Op.getValueType() == EVT::v4i32) {
+ if (Op.getValueType() == MVT::v4i32) {
SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
- SDValue Zero = BuildSplatI( 0, 1, EVT::v4i32, DAG, dl);
- SDValue Neg16 = BuildSplatI(-16, 4, EVT::v4i32, DAG, dl);//+16 as shift amt.
+ SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
+ SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
SDValue RHSSwap = // = vrlw RHS, 16
BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
// Shrinkify inputs to v8i16.
- LHS = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v8i16, LHS);
- RHS = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v8i16, RHS);
- RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v8i16, RHSSwap);
+ LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, LHS);
+ RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHS);
+ RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHSSwap);
// Low parts multiplied together, generating 32-bit results (we ignore the
// top parts).
SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
- LHS, RHS, DAG, dl, EVT::v4i32);
+ LHS, RHS, DAG, dl, MVT::v4i32);
SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
- LHS, RHSSwap, Zero, DAG, dl, EVT::v4i32);
+ LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
// Shift the high parts up 16 bits.
HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
Neg16, DAG, dl);
- return DAG.getNode(ISD::ADD, dl, EVT::v4i32, LoProd, HiProd);
- } else if (Op.getValueType() == EVT::v8i16) {
+ return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
+ } else if (Op.getValueType() == MVT::v8i16) {
SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
- SDValue Zero = BuildSplatI(0, 1, EVT::v8i16, DAG, dl);
+ SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
LHS, RHS, Zero, DAG, dl);
- } else if (Op.getValueType() == EVT::v16i8) {
+ } else if (Op.getValueType() == MVT::v16i8) {
SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
// Multiply the even 8-bit parts, producing 16-bit sums.
SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
- LHS, RHS, DAG, dl, EVT::v8i16);
- EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, EvenParts);
+ LHS, RHS, DAG, dl, MVT::v8i16);
+ EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, EvenParts);
// Multiply the odd 8-bit parts, producing 16-bit sums.
SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
- LHS, RHS, DAG, dl, EVT::v8i16);
- OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, OddParts);
+ LHS, RHS, DAG, dl, MVT::v8i16);
+ OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OddParts);
// Merge the results together.
int Ops[16];
@@ -4155,7 +4155,7 @@
Ops[i*2 ] = 2*i+1;
Ops[i*2+1] = 2*i+1+16;
}
- return DAG.getVectorShuffle(EVT::v16i8, dl, EvenParts, OddParts, Ops);
+ return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
} else {
llvm_unreachable("Unknown mul to lower!");
}
@@ -4219,13 +4219,13 @@
assert(false && "Do not know how to custom type legalize this operation!");
return;
case ISD::FP_ROUND_INREG: {
- assert(N->getValueType(0) == EVT::ppcf128);
- assert(N->getOperand(0).getValueType() == EVT::ppcf128);
+ assert(N->getValueType(0) == MVT::ppcf128);
+ assert(N->getOperand(0).getValueType() == MVT::ppcf128);
SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
- EVT::f64, N->getOperand(0),
+ MVT::f64, N->getOperand(0),
DAG.getIntPtrConstant(0));
SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
- EVT::f64, N->getOperand(0),
+ MVT::f64, N->getOperand(0),
DAG.getIntPtrConstant(1));
// This sequence changes FPSCR to do round-to-zero, adds the two halves
@@ -4234,29 +4234,29 @@
std::vector<EVT> NodeTys;
SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
- NodeTys.push_back(EVT::f64); // Return register
- NodeTys.push_back(EVT::Flag); // Returns a flag for later insns
+ NodeTys.push_back(MVT::f64); // Return register
+ NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
MFFSreg = Result.getValue(0);
InFlag = Result.getValue(1);
NodeTys.clear();
- NodeTys.push_back(EVT::Flag); // Returns a flag
- Ops[0] = DAG.getConstant(31, EVT::i32);
+ NodeTys.push_back(MVT::Flag); // Returns a flag
+ Ops[0] = DAG.getConstant(31, MVT::i32);
Ops[1] = InFlag;
Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2);
InFlag = Result.getValue(0);
NodeTys.clear();
- NodeTys.push_back(EVT::Flag); // Returns a flag
- Ops[0] = DAG.getConstant(30, EVT::i32);
+ NodeTys.push_back(MVT::Flag); // Returns a flag
+ Ops[0] = DAG.getConstant(30, MVT::i32);
Ops[1] = InFlag;
Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2);
InFlag = Result.getValue(0);
NodeTys.clear();
- NodeTys.push_back(EVT::f64); // result of add
- NodeTys.push_back(EVT::Flag); // Returns a flag
+ NodeTys.push_back(MVT::f64); // result of add
+ NodeTys.push_back(MVT::Flag); // Returns a flag
Ops[0] = Lo;
Ops[1] = Hi;
Ops[2] = InFlag;
@@ -4265,8 +4265,8 @@
InFlag = Result.getValue(1);
NodeTys.clear();
- NodeTys.push_back(EVT::f64);
- Ops[0] = DAG.getConstant(1, EVT::i32);
+ NodeTys.push_back(MVT::f64);
+ Ops[0] = DAG.getConstant(1, MVT::i32);
Ops[1] = MFFSreg;
Ops[2] = FPreg;
Ops[3] = InFlag;
@@ -4275,7 +4275,7 @@
// We know the low half is about to be thrown away, so just use something
// convenient.
- Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, EVT::ppcf128,
+ Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
FPreg, FPreg));
return;
}
@@ -4853,25 +4853,25 @@
// Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
// We allow the src/dst to be either f32/f64, but the intermediate
// type must be i64.
- if (N->getOperand(0).getValueType() == EVT::i64 &&
- N->getOperand(0).getOperand(0).getValueType() != EVT::ppcf128) {
+ if (N->getOperand(0).getValueType() == MVT::i64 &&
+ N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
SDValue Val = N->getOperand(0).getOperand(0);
- if (Val.getValueType() == EVT::f32) {
- Val = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, Val);
+ if (Val.getValueType() == MVT::f32) {
+ Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
DCI.AddToWorklist(Val.getNode());
}
- Val = DAG.getNode(PPCISD::FCTIDZ, dl, EVT::f64, Val);
+ Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
DCI.AddToWorklist(Val.getNode());
- Val = DAG.getNode(PPCISD::FCFID, dl, EVT::f64, Val);
+ Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
DCI.AddToWorklist(Val.getNode());
- if (N->getValueType(0) == EVT::f32) {
- Val = DAG.getNode(ISD::FP_ROUND, dl, EVT::f32, Val,
+ if (N->getValueType(0) == MVT::f32) {
+ Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
DAG.getIntPtrConstant(0));
DCI.AddToWorklist(Val.getNode());
}
return Val;
- } else if (N->getOperand(0).getValueType() == EVT::i32) {
+ } else if (N->getOperand(0).getValueType() == MVT::i32) {
// If the intermediate type is i32, we can avoid the load/store here
// too.
}
@@ -4883,17 +4883,17 @@
if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
!cast<StoreSDNode>(N)->isTruncatingStore() &&
N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
- N->getOperand(1).getValueType() == EVT::i32 &&
- N->getOperand(1).getOperand(0).getValueType() != EVT::ppcf128) {
+ N->getOperand(1).getValueType() == MVT::i32 &&
+ N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
SDValue Val = N->getOperand(1).getOperand(0);
- if (Val.getValueType() == EVT::f32) {
- Val = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, Val);
+ if (Val.getValueType() == MVT::f32) {
+ Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
DCI.AddToWorklist(Val.getNode());
}
- Val = DAG.getNode(PPCISD::FCTIWZ, dl, EVT::f64, Val);
+ Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
DCI.AddToWorklist(Val.getNode());
- Val = DAG.getNode(PPCISD::STFIWX, dl, EVT::Other, N->getOperand(0), Val,
+ Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val,
N->getOperand(2), N->getOperand(3));
DCI.AddToWorklist(Val.getNode());
return Val;
@@ -4902,14 +4902,14 @@
// Turn STORE (BSWAP) -> sthbrx/stwbrx.
if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
N->getOperand(1).getNode()->hasOneUse() &&
- (N->getOperand(1).getValueType() == EVT::i32 ||
- N->getOperand(1).getValueType() == EVT::i16)) {
+ (N->getOperand(1).getValueType() == MVT::i32 ||
+ N->getOperand(1).getValueType() == MVT::i16)) {
SDValue BSwapOp = N->getOperand(1).getOperand(0);
// Do an any-extend to 32-bits if this is a half-word input.
- if (BSwapOp.getValueType() == EVT::i16)
- BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, EVT::i32, BSwapOp);
+ if (BSwapOp.getValueType() == MVT::i16)
+ BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
- return DAG.getNode(PPCISD::STBRX, dl, EVT::Other, N->getOperand(0),
+ return DAG.getNode(PPCISD::STBRX, dl, MVT::Other, N->getOperand(0),
BSwapOp, N->getOperand(2), N->getOperand(3),
DAG.getValueType(N->getOperand(1).getValueType()));
}
@@ -4918,13 +4918,13 @@
// Turn BSWAP (LOAD) -> lhbrx/lwbrx.
if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
N->getOperand(0).hasOneUse() &&
- (N->getValueType(0) == EVT::i32 || N->getValueType(0) == EVT::i16)) {
+ (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
SDValue Load = N->getOperand(0);
LoadSDNode *LD = cast<LoadSDNode>(Load);
// Create the byte-swapping load.
std::vector<EVT> VTs;
- VTs.push_back(EVT::i32);
- VTs.push_back(EVT::Other);
+ VTs.push_back(MVT::i32);
+ VTs.push_back(MVT::Other);
SDValue MO = DAG.getMemOperand(LD->getMemOperand());
SDValue Ops[] = {
LD->getChain(), // Chain
@@ -4936,8 +4936,8 @@
// If this is an i16 load, insert the truncate.
SDValue ResVal = BSLoad;
- if (N->getValueType(0) == EVT::i16)
- ResVal = DAG.getNode(ISD::TRUNCATE, dl, EVT::i16, BSLoad);
+ if (N->getValueType(0) == MVT::i16)
+ ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
// First, combine the bswap away. This makes the value produced by the
// load dead.
@@ -5025,7 +5025,7 @@
if (CC == ISD::SETEQ) // Cond never true, remove branch.
return N->getOperand(0);
// Always !=, turn it into an unconditional branch.
- return DAG.getNode(ISD::BR, dl, EVT::Other,
+ return DAG.getNode(ISD::BR, dl, MVT::Other,
N->getOperand(0), N->getOperand(4));
}
@@ -5036,10 +5036,10 @@
SDValue Ops[] = {
LHS.getOperand(2), // LHS of compare
LHS.getOperand(3), // RHS of compare
- DAG.getConstant(CompareOpc, EVT::i32)
+ DAG.getConstant(CompareOpc, MVT::i32)
};
VTs.push_back(LHS.getOperand(2).getValueType());
- VTs.push_back(EVT::Flag);
+ VTs.push_back(MVT::Flag);
SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
// Unpack the result based on how the target uses it.
@@ -5060,9 +5060,9 @@
break;
}
- return DAG.getNode(PPCISD::COND_BRANCH, dl, EVT::Other, N->getOperand(0),
- DAG.getConstant(CompOpc, EVT::i32),
- DAG.getRegister(PPC::CR6, EVT::i32),
+ return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
+ DAG.getConstant(CompOpc, MVT::i32),
+ DAG.getRegister(PPC::CR6, MVT::i32),
N->getOperand(4), CompNode.getValue(1));
}
break;
@@ -5087,7 +5087,7 @@
default: break;
case PPCISD::LBRX: {
// lhbrx is known to have the top bits cleared out.
- if (cast<VTSDNode>(Op.getOperand(3))->getVT() == EVT::i16)
+ if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
KnownZero = 0xFFFF0000;
break;
}
@@ -5141,13 +5141,13 @@
switch (Constraint[0]) {
case 'b': // R1-R31
case 'r': // R0-R31
- if (VT == EVT::i64 && PPCSubTarget.isPPC64())
+ if (VT == MVT::i64 && PPCSubTarget.isPPC64())
return std::make_pair(0U, PPC::G8RCRegisterClass);
return std::make_pair(0U, PPC::GPRCRegisterClass);
case 'f':
- if (VT == EVT::f32)
+ if (VT == MVT::f32)
return std::make_pair(0U, PPC::F4RCRegisterClass);
- else if (VT == EVT::f64)
+ else if (VT == MVT::f64)
return std::make_pair(0U, PPC::F8RCRegisterClass);
break;
case 'v':
@@ -5302,7 +5302,7 @@
return SDValue();
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
- bool isPPC64 = PtrVT == EVT::i64;
+ bool isPPC64 = PtrVT == MVT::i64;
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
@@ -5311,10 +5311,10 @@
if (isPPC64)
return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::X31 : PPC::X1,
- EVT::i64);
+ MVT::i64);
else
return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::R31 : PPC::R1,
- EVT::i32);
+ MVT::i32);
}
bool
@@ -5327,8 +5327,8 @@
bool isSrcConst, bool isSrcStr,
SelectionDAG &DAG) const {
if (this->PPCSubTarget.isPPC64()) {
- return EVT::i64;
+ return MVT::i64;
} else {
- return EVT::i32;
+ return MVT::i32;
}
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Tue Aug 11 15:47:22 2009
@@ -230,7 +230,7 @@
virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - Return the ISD::SETCC ValueType
- virtual EVT::SimpleValueType getSetCCResultType(EVT VT) const;
+ virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
/// getPreIndexedAddressParts - returns true by value, base pointer and
/// offset pointer and addressing mode by reference if the node's address
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Tue Aug 11 15:47:22 2009
@@ -191,7 +191,7 @@
def maskimm32 : PatLeaf<(imm), [{
// maskImm predicate - True if immediate is a run of ones.
unsigned mb, me;
- if (N->getValueType(0) == EVT::i32)
+ if (N->getValueType(0) == MVT::i32)
return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
else
return false;
@@ -200,7 +200,7 @@
def immSExt16 : PatLeaf<(imm), [{
// immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
// field. Used by instructions like 'addi'.
- if (N->getValueType(0) == EVT::i32)
+ if (N->getValueType(0) == MVT::i32)
return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
else
return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
@@ -227,7 +227,7 @@
// immediate are set. Used by instructions like 'addis'. Identical to
// imm16ShiftedZExt in 32-bit mode.
if (N->getZExtValue() & 0xFFFF) return false;
- if (N->getValueType(0) == EVT::i32)
+ if (N->getValueType(0) == MVT::i32)
return true;
// For 64-bit, make sure it is sext right.
return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
Modified: llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp Tue Aug 11 15:47:22 2009
@@ -79,8 +79,8 @@
bool SparcDAGToDAGISel::SelectADDRri(SDValue Op, SDValue Addr,
SDValue &Base, SDValue &Offset) {
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i32);
- Offset = CurDAG->getTargetConstant(0, EVT::i32);
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
+ Offset = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
@@ -93,11 +93,11 @@
if (FrameIndexSDNode *FIN =
dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
// Constant offset from frame ref.
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i32);
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
} else {
Base = Addr.getOperand(0);
}
- Offset = CurDAG->getTargetConstant(CN->getZExtValue(), EVT::i32);
+ Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
return true;
}
}
@@ -113,7 +113,7 @@
}
}
Base = Addr;
- Offset = CurDAG->getTargetConstant(0, EVT::i32);
+ Offset = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
@@ -137,7 +137,7 @@
}
R1 = Addr;
- R2 = CurDAG->getRegister(SP::G0, EVT::i32);
+ R2 = CurDAG->getRegister(SP::G0, MVT::i32);
return true;
}
@@ -158,17 +158,17 @@
// Set the Y register to the high-part.
SDValue TopPart;
if (N->getOpcode() == ISD::SDIV) {
- TopPart = SDValue(CurDAG->getTargetNode(SP::SRAri, dl, EVT::i32, DivLHS,
- CurDAG->getTargetConstant(31, EVT::i32)), 0);
+ TopPart = SDValue(CurDAG->getTargetNode(SP::SRAri, dl, MVT::i32, DivLHS,
+ CurDAG->getTargetConstant(31, MVT::i32)), 0);
} else {
- TopPart = CurDAG->getRegister(SP::G0, EVT::i32);
+ TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
}
- TopPart = SDValue(CurDAG->getTargetNode(SP::WRYrr, dl, EVT::Flag, TopPart,
- CurDAG->getRegister(SP::G0, EVT::i32)), 0);
+ TopPart = SDValue(CurDAG->getTargetNode(SP::WRYrr, dl, MVT::Flag, TopPart,
+ CurDAG->getRegister(SP::G0, MVT::i32)), 0);
// FIXME: Handle div by immediate.
unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
- return CurDAG->SelectNodeTo(N, Opcode, EVT::i32, DivLHS, DivRHS,
+ return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
TopPart);
}
case ISD::MULHU:
@@ -177,10 +177,10 @@
SDValue MulLHS = N->getOperand(0);
SDValue MulRHS = N->getOperand(1);
unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
- SDNode *Mul = CurDAG->getTargetNode(Opcode, dl, EVT::i32, EVT::Flag,
+ SDNode *Mul = CurDAG->getTargetNode(Opcode, dl, MVT::i32, MVT::Flag,
MulLHS, MulRHS);
// The high part is in the Y register.
- return CurDAG->SelectNodeTo(N, SP::RDY, EVT::i32, SDValue(Mul, 1));
+ return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1));
return NULL;
}
}
Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Tue Aug 11 15:47:22 2009
@@ -72,8 +72,8 @@
}
if (Flag.getNode())
- return DAG.getNode(SPISD::RET_FLAG, dl, EVT::Other, Chain, Flag);
- return DAG.getNode(SPISD::RET_FLAG, dl, EVT::Other, Chain);
+ return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
+ return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain);
}
/// LowerFormalArguments - V8 uses a very simple ABI, where all values are
@@ -108,40 +108,40 @@
// FIXME: We ignore the register assignments of AnalyzeFormalArguments
// because it doesn't know how to split a double into two i32 registers.
EVT ObjectVT = VA.getValVT();
- switch (ObjectVT.getSimpleVT()) {
+ switch (ObjectVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unhandled argument type!");
- case EVT::i1:
- case EVT::i8:
- case EVT::i16:
- case EVT::i32:
+ case MVT::i1:
+ case MVT::i8:
+ case MVT::i16:
+ case MVT::i32:
if (!Ins[i].Used) { // Argument is dead.
if (CurArgReg < ArgRegEnd) ++CurArgReg;
InVals.push_back(DAG.getUNDEF(ObjectVT));
} else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
- SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, EVT::i32);
- if (ObjectVT != EVT::i32) {
+ SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
+ if (ObjectVT != MVT::i32) {
unsigned AssertOp = ISD::AssertSext;
- Arg = DAG.getNode(AssertOp, dl, EVT::i32, Arg,
+ Arg = DAG.getNode(AssertOp, dl, MVT::i32, Arg,
DAG.getValueType(ObjectVT));
Arg = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Arg);
}
InVals.push_back(Arg);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
- SDValue FIPtr = DAG.getFrameIndex(FrameIdx, EVT::i32);
+ SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
SDValue Load;
- if (ObjectVT == EVT::i32) {
- Load = DAG.getLoad(EVT::i32, dl, Chain, FIPtr, NULL, 0);
+ if (ObjectVT == MVT::i32) {
+ Load = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0);
} else {
ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
// Sparc is big endian, so add an offset based on the ObjectVT.
unsigned Offset = 4-std::max(1U, ObjectVT.getSizeInBits()/8);
- FIPtr = DAG.getNode(ISD::ADD, dl, EVT::i32, FIPtr,
- DAG.getConstant(Offset, EVT::i32));
- Load = DAG.getExtLoad(LoadOp, dl, EVT::i32, Chain, FIPtr,
+ FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
+ DAG.getConstant(Offset, MVT::i32));
+ Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr,
NULL, 0, ObjectVT);
Load = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Load);
}
@@ -150,7 +150,7 @@
ArgOffset += 4;
break;
- case EVT::f32:
+ case MVT::f32:
if (!Ins[i].Used) { // Argument is dead.
if (CurArgReg < ArgRegEnd) ++CurArgReg;
InVals.push_back(DAG.getUNDEF(ObjectVT));
@@ -158,21 +158,21 @@
// FP value is passed in an integer register.
unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
- SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, EVT::i32);
+ SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
- Arg = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, Arg);
+ Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Arg);
InVals.push_back(Arg);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
- SDValue FIPtr = DAG.getFrameIndex(FrameIdx, EVT::i32);
- SDValue Load = DAG.getLoad(EVT::f32, dl, Chain, FIPtr, NULL, 0);
+ SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
+ SDValue Load = DAG.getLoad(MVT::f32, dl, Chain, FIPtr, NULL, 0);
InVals.push_back(Load);
}
ArgOffset += 4;
break;
- case EVT::i64:
- case EVT::f64:
+ case MVT::i64:
+ case MVT::f64:
if (!Ins[i].Used) { // Argument is dead.
if (CurArgReg < ArgRegEnd) ++CurArgReg;
if (CurArgReg < ArgRegEnd) ++CurArgReg;
@@ -182,31 +182,31 @@
if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi);
- HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, EVT::i32);
+ HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
- SDValue FIPtr = DAG.getFrameIndex(FrameIdx, EVT::i32);
- HiVal = DAG.getLoad(EVT::i32, dl, Chain, FIPtr, NULL, 0);
+ SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
+ HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0);
}
SDValue LoVal;
if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo);
- LoVal = DAG.getCopyFromReg(Chain, dl, VRegLo, EVT::i32);
+ LoVal = DAG.getCopyFromReg(Chain, dl, VRegLo, MVT::i32);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
- SDValue FIPtr = DAG.getFrameIndex(FrameIdx, EVT::i32);
- LoVal = DAG.getLoad(EVT::i32, dl, Chain, FIPtr, NULL, 0);
+ SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
+ LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0);
}
// Compose the two halves together into an i64 unit.
SDValue WholeValue =
- DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i64, LoVal, HiVal);
+ DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
// If we want a double, do a bit convert.
- if (ObjectVT == EVT::f64)
- WholeValue = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f64, WholeValue);
+ if (ObjectVT == MVT::f64)
+ WholeValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, WholeValue);
InVals.push_back(WholeValue);
}
@@ -225,10 +225,10 @@
for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
- SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, EVT::i32);
+ SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
- SDValue FIPtr = DAG.getFrameIndex(FrameIdx, EVT::i32);
+ SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, NULL, 0));
ArgOffset += 4;
@@ -236,7 +236,7 @@
if (!OutChains.empty()) {
OutChains.push_back(Chain);
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&OutChains[0], OutChains.size());
}
}
@@ -268,17 +268,17 @@
// Count the size of the outgoing arguments.
unsigned ArgsSize = 0;
for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
- switch (Outs[i].Val.getValueType().getSimpleVT()) {
+ switch (Outs[i].Val.getValueType().getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unknown value type!");
- case EVT::i1:
- case EVT::i8:
- case EVT::i16:
- case EVT::i32:
- case EVT::f32:
+ case MVT::i1:
+ case MVT::i8:
+ case MVT::i16:
+ case MVT::i32:
+ case MVT::f32:
ArgsSize += 4;
break;
- case EVT::i64:
- case EVT::f64:
+ case MVT::i64:
+ case MVT::f64:
ArgsSize += 8;
break;
}
@@ -328,10 +328,10 @@
assert(VA.isMemLoc());
// Create a store off the stack pointer for this argument.
- SDValue StackPtr = DAG.getRegister(SP::O6, EVT::i32);
+ SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
// FIXME: VERIFY THAT 68 IS RIGHT.
SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+68);
- PtrOff = DAG.getNode(ISD::ADD, EVT::i32, StackPtr, PtrOff);
+ PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
}
@@ -346,9 +346,9 @@
EVT ObjectVT = Val.getValueType();
SDValue ValToStore(0, 0);
unsigned ObjSize;
- switch (ObjectVT.getSimpleVT()) {
+ switch (ObjectVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unhandled argument type!");
- case EVT::i32:
+ case MVT::i32:
ObjSize = 4;
if (RegsToPass.size() >= 6) {
@@ -357,17 +357,17 @@
RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
}
break;
- case EVT::f32:
+ case MVT::f32:
ObjSize = 4;
if (RegsToPass.size() >= 6) {
ValToStore = Val;
} else {
// Convert this to a FP value in an int reg.
- Val = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Val);
+ Val = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Val);
RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
}
break;
- case EVT::f64: {
+ case MVT::f64: {
ObjSize = 8;
if (RegsToPass.size() >= 6) {
ValToStore = Val; // Whole thing is passed in memory.
@@ -376,16 +376,16 @@
// Break into top and bottom parts by storing to the stack and loading
// out the parts as integers. Top part goes in a reg.
- SDValue StackPtr = DAG.CreateStackTemporary(EVT::f64, EVT::i32);
+ SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);
SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
Val, StackPtr, NULL, 0);
// Sparc is big-endian, so the high part comes first.
- SDValue Hi = DAG.getLoad(EVT::i32, dl, Store, StackPtr, NULL, 0, 0);
+ SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0, 0);
// Increment the pointer to the other half.
StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
DAG.getIntPtrConstant(4));
// Load the low part.
- SDValue Lo = DAG.getLoad(EVT::i32, dl, Store, StackPtr, NULL, 0, 0);
+ SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0, 0);
RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
@@ -398,7 +398,7 @@
}
break;
}
- case EVT::i64: {
+ case MVT::i64: {
ObjSize = 8;
if (RegsToPass.size() >= 6) {
ValToStore = Val; // Whole thing is passed in memory.
@@ -406,10 +406,10 @@
}
// Split the value into top and bottom part. Top part goes in a reg.
- SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Val,
- DAG.getConstant(1, EVT::i32));
- SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Val,
- DAG.getConstant(0, EVT::i32));
+ SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val,
+ DAG.getConstant(1, MVT::i32));
+ SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val,
+ DAG.getConstant(0, MVT::i32));
RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
if (RegsToPass.size() >= 6) {
@@ -424,9 +424,9 @@
}
if (ValToStore.getNode()) {
- SDValue StackPtr = DAG.getRegister(SP::O6, EVT::i32);
- SDValue PtrOff = DAG.getConstant(ArgOffset, EVT::i32);
- PtrOff = DAG.getNode(ISD::ADD, dl, EVT::i32, StackPtr, PtrOff);
+ SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
+ SDValue PtrOff = DAG.getConstant(ArgOffset, MVT::i32);
+ PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, dl, ValToStore,
PtrOff, NULL, 0));
}
@@ -436,7 +436,7 @@
// Emit all stores, make sure the occur before any copies into physregs.
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token
@@ -458,13 +458,13 @@
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
// Likewise ExternalSymbol -> TargetExternalSymbol.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
- Callee = DAG.getTargetGlobalAddress(G->getGlobal(), EVT::i32);
+ Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
- Callee = DAG.getTargetExternalSymbol(E->getSymbol(), EVT::i32);
+ Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
std::vector<EVT> NodeTys;
- NodeTys.push_back(EVT::Other); // Returns a chain
- NodeTys.push_back(EVT::Flag); // Returns a flag for retval copy to use.
+ NodeTys.push_back(MVT::Other); // Returns a chain
+ NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
SDValue Ops[] = { Chain, Callee, InFlag };
Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops, InFlag.getNode() ? 3 : 2);
InFlag = Chain.getValue(1);
@@ -553,120 +553,120 @@
: TargetLowering(TM, new TargetLoweringObjectFileELF()) {
// Set up the register classes.
- addRegisterClass(EVT::i32, SP::IntRegsRegisterClass);
- addRegisterClass(EVT::f32, SP::FPRegsRegisterClass);
- addRegisterClass(EVT::f64, SP::DFPRegsRegisterClass);
+ addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
+ addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
+ addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
// Turn FP extload into load/fextend
- setLoadExtAction(ISD::EXTLOAD, EVT::f32, Expand);
+ setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
// Sparc doesn't have i1 sign extending load
- setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
// Turn FP truncstore into trunc + store.
- setTruncStoreAction(EVT::f64, EVT::f32, Expand);
+ setTruncStoreAction(MVT::f64, MVT::f32, Expand);
// Custom legalize GlobalAddress nodes into LO/HI parts.
- setOperationAction(ISD::GlobalAddress, EVT::i32, Custom);
- setOperationAction(ISD::GlobalTLSAddress, EVT::i32, Custom);
- setOperationAction(ISD::ConstantPool , EVT::i32, Custom);
+ setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
+ setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
+ setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
// Sparc doesn't have sext_inreg, replace them with shl/sra
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i16, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i8 , Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1 , Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
// Sparc has no REM or DIVREM operations.
- setOperationAction(ISD::UREM, EVT::i32, Expand);
- setOperationAction(ISD::SREM, EVT::i32, Expand);
- setOperationAction(ISD::SDIVREM, EVT::i32, Expand);
- setOperationAction(ISD::UDIVREM, EVT::i32, Expand);
+ setOperationAction(ISD::UREM, MVT::i32, Expand);
+ setOperationAction(ISD::SREM, MVT::i32, Expand);
+ setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
+ setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
// Custom expand fp<->sint
- setOperationAction(ISD::FP_TO_SINT, EVT::i32, Custom);
- setOperationAction(ISD::SINT_TO_FP, EVT::i32, Custom);
+ setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
+ setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
// Expand fp<->uint
- setOperationAction(ISD::FP_TO_UINT, EVT::i32, Expand);
- setOperationAction(ISD::UINT_TO_FP, EVT::i32, Expand);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
+ setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
- setOperationAction(ISD::BIT_CONVERT, EVT::f32, Expand);
- setOperationAction(ISD::BIT_CONVERT, EVT::i32, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
// Sparc has no select or setcc: expand to SELECT_CC.
- setOperationAction(ISD::SELECT, EVT::i32, Expand);
- setOperationAction(ISD::SELECT, EVT::f32, Expand);
- setOperationAction(ISD::SELECT, EVT::f64, Expand);
- setOperationAction(ISD::SETCC, EVT::i32, Expand);
- setOperationAction(ISD::SETCC, EVT::f32, Expand);
- setOperationAction(ISD::SETCC, EVT::f64, Expand);
+ setOperationAction(ISD::SELECT, MVT::i32, Expand);
+ setOperationAction(ISD::SELECT, MVT::f32, Expand);
+ setOperationAction(ISD::SELECT, MVT::f64, Expand);
+ setOperationAction(ISD::SETCC, MVT::i32, Expand);
+ setOperationAction(ISD::SETCC, MVT::f32, Expand);
+ setOperationAction(ISD::SETCC, MVT::f64, Expand);
// Sparc doesn't have BRCOND either, it has BR_CC.
- setOperationAction(ISD::BRCOND, EVT::Other, Expand);
- setOperationAction(ISD::BRIND, EVT::Other, Expand);
- setOperationAction(ISD::BR_JT, EVT::Other, Expand);
- setOperationAction(ISD::BR_CC, EVT::i32, Custom);
- setOperationAction(ISD::BR_CC, EVT::f32, Custom);
- setOperationAction(ISD::BR_CC, EVT::f64, Custom);
-
- setOperationAction(ISD::SELECT_CC, EVT::i32, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::f32, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::f64, Custom);
+ setOperationAction(ISD::BRCOND, MVT::Other, Expand);
+ setOperationAction(ISD::BRIND, MVT::Other, Expand);
+ setOperationAction(ISD::BR_JT, MVT::Other, Expand);
+ setOperationAction(ISD::BR_CC, MVT::i32, Custom);
+ setOperationAction(ISD::BR_CC, MVT::f32, Custom);
+ setOperationAction(ISD::BR_CC, MVT::f64, Custom);
+
+ setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
// SPARC has no intrinsics for these particular operations.
- setOperationAction(ISD::MEMBARRIER, EVT::Other, Expand);
+ setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
- setOperationAction(ISD::FSIN , EVT::f64, Expand);
- setOperationAction(ISD::FCOS , EVT::f64, Expand);
- setOperationAction(ISD::FREM , EVT::f64, Expand);
- setOperationAction(ISD::FSIN , EVT::f32, Expand);
- setOperationAction(ISD::FCOS , EVT::f32, Expand);
- setOperationAction(ISD::FREM , EVT::f32, Expand);
- setOperationAction(ISD::CTPOP, EVT::i32, Expand);
- setOperationAction(ISD::CTTZ , EVT::i32, Expand);
- setOperationAction(ISD::CTLZ , EVT::i32, Expand);
- setOperationAction(ISD::ROTL , EVT::i32, Expand);
- setOperationAction(ISD::ROTR , EVT::i32, Expand);
- setOperationAction(ISD::BSWAP, EVT::i32, Expand);
- setOperationAction(ISD::FCOPYSIGN, EVT::f64, Expand);
- setOperationAction(ISD::FCOPYSIGN, EVT::f32, Expand);
- setOperationAction(ISD::FPOW , EVT::f64, Expand);
- setOperationAction(ISD::FPOW , EVT::f32, Expand);
-
- setOperationAction(ISD::SHL_PARTS, EVT::i32, Expand);
- setOperationAction(ISD::SRA_PARTS, EVT::i32, Expand);
- setOperationAction(ISD::SRL_PARTS, EVT::i32, Expand);
+ setOperationAction(ISD::FSIN , MVT::f64, Expand);
+ setOperationAction(ISD::FCOS , MVT::f64, Expand);
+ setOperationAction(ISD::FREM , MVT::f64, Expand);
+ setOperationAction(ISD::FSIN , MVT::f32, Expand);
+ setOperationAction(ISD::FCOS , MVT::f32, Expand);
+ setOperationAction(ISD::FREM , MVT::f32, Expand);
+ setOperationAction(ISD::CTPOP, MVT::i32, Expand);
+ setOperationAction(ISD::CTTZ , MVT::i32, Expand);
+ setOperationAction(ISD::CTLZ , MVT::i32, Expand);
+ setOperationAction(ISD::ROTL , MVT::i32, Expand);
+ setOperationAction(ISD::ROTR , MVT::i32, Expand);
+ setOperationAction(ISD::BSWAP, MVT::i32, Expand);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
+ setOperationAction(ISD::FPOW , MVT::f64, Expand);
+ setOperationAction(ISD::FPOW , MVT::f32, Expand);
+
+ setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
// FIXME: Sparc provides these multiplies, but we don't have them yet.
- setOperationAction(ISD::UMUL_LOHI, EVT::i32, Expand);
- setOperationAction(ISD::SMUL_LOHI, EVT::i32, Expand);
+ setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
+ setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
// We don't have line number support yet.
- setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand);
- setOperationAction(ISD::DBG_LABEL, EVT::Other, Expand);
- setOperationAction(ISD::EH_LABEL, EVT::Other, Expand);
+ setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
+ setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
// VASTART needs to be custom lowered to use the VarArgsFrameIndex.
- setOperationAction(ISD::VASTART , EVT::Other, Custom);
+ setOperationAction(ISD::VASTART , MVT::Other, Custom);
// VAARG needs to be lowered to not do unaligned accesses for doubles.
- setOperationAction(ISD::VAARG , EVT::Other, Custom);
+ setOperationAction(ISD::VAARG , MVT::Other, Custom);
// Use the default implementation.
- setOperationAction(ISD::VACOPY , EVT::Other, Expand);
- setOperationAction(ISD::VAEND , EVT::Other, Expand);
- setOperationAction(ISD::STACKSAVE , EVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE , EVT::Other, Expand);
- setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32 , Custom);
+ setOperationAction(ISD::VACOPY , MVT::Other, Expand);
+ setOperationAction(ISD::VAEND , MVT::Other, Expand);
+ setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
// No debug info support yet.
- setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand);
- setOperationAction(ISD::DBG_LABEL, EVT::Other, Expand);
- setOperationAction(ISD::EH_LABEL, EVT::Other, Expand);
- setOperationAction(ISD::DECLARE, EVT::Other, Expand);
+ setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
+ setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::DECLARE, MVT::Other, Expand);
setStackPointerRegisterToSaveRestore(SP::O6);
if (TM.getSubtarget<SparcSubtarget>().isV9())
- setOperationAction(ISD::CTPOP, EVT::i32, Legal);
+ setOperationAction(ISD::CTPOP, MVT::i32, Legal);
computeRegisterProperties();
}
@@ -745,10 +745,10 @@
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
// FIXME there isn't really any debug info here
DebugLoc dl = Op.getDebugLoc();
- SDValue GA = DAG.getTargetGlobalAddress(GV, EVT::i32);
- SDValue Hi = DAG.getNode(SPISD::Hi, dl, EVT::i32, GA);
- SDValue Lo = DAG.getNode(SPISD::Lo, dl, EVT::i32, GA);
- return DAG.getNode(ISD::ADD, dl, EVT::i32, Lo, Hi);
+ SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
+ SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, GA);
+ SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, GA);
+ return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
}
static SDValue LowerCONSTANTPOOL(SDValue Op, SelectionDAG &DAG) {
@@ -756,24 +756,24 @@
// FIXME there isn't really any debug info here
DebugLoc dl = Op.getDebugLoc();
Constant *C = N->getConstVal();
- SDValue CP = DAG.getTargetConstantPool(C, EVT::i32, N->getAlignment());
- SDValue Hi = DAG.getNode(SPISD::Hi, dl, EVT::i32, CP);
- SDValue Lo = DAG.getNode(SPISD::Lo, dl, EVT::i32, CP);
- return DAG.getNode(ISD::ADD, dl, EVT::i32, Lo, Hi);
+ SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
+ SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, CP);
+ SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, CP);
+ return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
}
static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
// Convert the fp value to integer in an FP register.
- assert(Op.getValueType() == EVT::i32);
- Op = DAG.getNode(SPISD::FTOI, dl, EVT::f32, Op.getOperand(0));
- return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op);
+ assert(Op.getValueType() == MVT::i32);
+ Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
+ return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
}
static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
- assert(Op.getOperand(0).getValueType() == EVT::i32);
- SDValue Tmp = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, Op.getOperand(0));
+ assert(Op.getOperand(0).getValueType() == MVT::i32);
+ SDValue Tmp = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
// Convert the int value to FP in an FP register.
return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp);
}
@@ -793,21 +793,21 @@
// Get the condition flag.
SDValue CompareFlag;
- if (LHS.getValueType() == EVT::i32) {
+ if (LHS.getValueType() == MVT::i32) {
std::vector<EVT> VTs;
- VTs.push_back(EVT::i32);
- VTs.push_back(EVT::Flag);
+ VTs.push_back(MVT::i32);
+ VTs.push_back(MVT::Flag);
SDValue Ops[2] = { LHS, RHS };
CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
Opc = SPISD::BRICC;
} else {
- CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, EVT::Flag, LHS, RHS);
+ CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Flag, LHS, RHS);
if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
Opc = SPISD::BRFCC;
}
- return DAG.getNode(Opc, dl, EVT::Other, Chain, Dest,
- DAG.getConstant(SPCC, EVT::i32), CompareFlag);
+ return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
+ DAG.getConstant(SPCC, MVT::i32), CompareFlag);
}
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
@@ -824,21 +824,21 @@
LookThroughSetCC(LHS, RHS, CC, SPCC);
SDValue CompareFlag;
- if (LHS.getValueType() == EVT::i32) {
+ if (LHS.getValueType() == MVT::i32) {
std::vector<EVT> VTs;
VTs.push_back(LHS.getValueType()); // subcc returns a value
- VTs.push_back(EVT::Flag);
+ VTs.push_back(MVT::Flag);
SDValue Ops[2] = { LHS, RHS };
CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
Opc = SPISD::SELECT_ICC;
if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
} else {
- CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, EVT::Flag, LHS, RHS);
+ CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Flag, LHS, RHS);
Opc = SPISD::SELECT_FCC;
if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
}
return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
- DAG.getConstant(SPCC, EVT::i32), CompareFlag);
+ DAG.getConstant(SPCC, MVT::i32), CompareFlag);
}
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
@@ -846,10 +846,10 @@
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
DebugLoc dl = Op.getDebugLoc();
- SDValue Offset = DAG.getNode(ISD::ADD, dl, EVT::i32,
- DAG.getRegister(SP::I6, EVT::i32),
+ SDValue Offset = DAG.getNode(ISD::ADD, dl, MVT::i32,
+ DAG.getRegister(SP::I6, MVT::i32),
DAG.getConstant(TLI.getVarArgsFrameOffset(),
- EVT::i32));
+ MVT::i32));
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1), SV, 0);
}
@@ -861,25 +861,25 @@
SDValue VAListPtr = Node->getOperand(1);
const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
DebugLoc dl = Node->getDebugLoc();
- SDValue VAList = DAG.getLoad(EVT::i32, dl, InChain, VAListPtr, SV, 0);
+ SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr, SV, 0);
// Increment the pointer, VAList, to the next vaarg
- SDValue NextPtr = DAG.getNode(ISD::ADD, dl, EVT::i32, VAList,
+ SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList,
DAG.getConstant(VT.getSizeInBits()/8,
- EVT::i32));
+ MVT::i32));
// Store the incremented VAList to the legalized pointer
InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr,
VAListPtr, SV, 0);
// Load the actual argument out of the pointer VAList, unless this is an
// f64 load.
- if (VT != EVT::f64)
+ if (VT != MVT::f64)
return DAG.getLoad(VT, dl, InChain, VAList, NULL, 0);
// Otherwise, load it as i64, then do a bitconvert.
- SDValue V = DAG.getLoad(EVT::i64, dl, InChain, VAList, NULL, 0);
+ SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, NULL, 0);
// Bit-Convert the value to f64.
SDValue Ops[2] = {
- DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f64, V),
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, V),
V.getValue(1)
};
return DAG.getMergeValues(Ops, 2, dl);
@@ -891,14 +891,14 @@
DebugLoc dl = Op.getDebugLoc();
unsigned SPReg = SP::O6;
- SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, EVT::i32);
- SDValue NewSP = DAG.getNode(ISD::SUB, dl, EVT::i32, SP, Size); // Value
+ SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32);
+ SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value
Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
// The resultant pointer is actually 16 words from the bottom of the stack,
// to provide a register spill area.
- SDValue NewVal = DAG.getNode(ISD::ADD, dl, EVT::i32, NewSP,
- DAG.getConstant(96, EVT::i32));
+ SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP,
+ DAG.getConstant(96, MVT::i32));
SDValue Ops[2] = { NewVal, Chain };
return DAG.getMergeValues(Ops, 2, dl);
}
Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td Tue Aug 11 15:47:22 2009
@@ -57,12 +57,12 @@
def LO10 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023,
- EVT::i32);
+ MVT::i32);
}]>;
def HI22 : SDNodeXForm<imm, [{
// Transformation function: shift the immediate value down into the low bits.
- return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, EVT::i32);
+ return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32);
}]>;
def SETHIimm : PatLeaf<(imm), [{
Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp Tue Aug 11 15:47:22 2009
@@ -107,19 +107,19 @@
/// getI8Imm - Return a target constant with the specified value, of type
/// i8.
inline SDValue getI8Imm(uint64_t Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i8);
+ return CurDAG->getTargetConstant(Imm, MVT::i8);
}
/// getI16Imm - Return a target constant with the specified value, of type
/// i16.
inline SDValue getI16Imm(uint64_t Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i16);
+ return CurDAG->getTargetConstant(Imm, MVT::i16);
}
/// getI32Imm - Return a target constant with the specified value, of type
/// i32.
inline SDValue getI32Imm(uint64_t Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i32);
+ return CurDAG->getTargetConstant(Imm, MVT::i32);
}
// Include the pieces autogenerated from the target description.
@@ -353,7 +353,7 @@
Base = AM.Base.Reg;
else
Base = CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy());
- Disp = CurDAG->getTargetConstant(AM.Disp, EVT::i64);
+ Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i64);
}
void SystemZDAGToDAGISel::getAddressOperands(const SystemZRRIAddressMode &AM,
@@ -650,16 +650,16 @@
EVT ResVT;
bool is32Bit = false;
- switch (NVT.getSimpleVT()) {
+ switch (NVT.getSimpleVT().SimpleTy) {
default: assert(0 && "Unsupported VT!");
- case EVT::i32:
+ case MVT::i32:
Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m;
- ResVT = EVT::v2i64;
+ ResVT = MVT::v2i64;
is32Bit = true;
break;
- case EVT::i64:
+ case MVT::i64:
Opc = SystemZ::SDIVREM64r; MOpc = SystemZ::SDIVREM64m;
- ResVT = EVT::v2i64;
+ ResVT = MVT::v2i64;
break;
}
@@ -669,7 +669,7 @@
// Prepare the dividend
SDNode *Dividend;
if (is32Bit)
- Dividend = CurDAG->getTargetNode(SystemZ::MOVSX64rr32, dl, EVT::i64, N0);
+ Dividend = CurDAG->getTargetNode(SystemZ::MOVSX64rr32, dl, MVT::i64, N0);
else
Dividend = N0.getNode();
@@ -679,7 +679,7 @@
Dividend =
CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
SDValue(Tmp, 0), SDValue(Dividend, 0),
- CurDAG->getTargetConstant(subreg_odd, EVT::i32));
+ CurDAG->getTargetConstant(subreg_odd, MVT::i32));
SDNode *Result;
SDValue DivVal = SDValue(Dividend, 0);
@@ -699,7 +699,7 @@
dl, NVT,
SDValue(Result, 0),
CurDAG->getTargetConstant(SubRegIdx,
- EVT::i32));
+ MVT::i32));
ReplaceUses(Op.getValue(0), SDValue(Div, 0));
#ifndef NDEBUG
@@ -716,7 +716,7 @@
dl, NVT,
SDValue(Result, 0),
CurDAG->getTargetConstant(SubRegIdx,
- EVT::i32));
+ MVT::i32));
ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
#ifndef NDEBUG
@@ -739,18 +739,18 @@
EVT ResVT;
bool is32Bit = false;
- switch (NVT.getSimpleVT()) {
+ switch (NVT.getSimpleVT().SimpleTy) {
default: assert(0 && "Unsupported VT!");
- case EVT::i32:
+ case MVT::i32:
Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m;
ClrOpc = SystemZ::MOV64Pr0_even;
- ResVT = EVT::v2i32;
+ ResVT = MVT::v2i32;
is32Bit = true;
break;
- case EVT::i64:
+ case MVT::i64:
Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m;
ClrOpc = SystemZ::MOV128r0_even;
- ResVT = EVT::v2i64;
+ ResVT = MVT::v2i64;
break;
}
@@ -768,7 +768,7 @@
Dividend =
CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
SDValue(Tmp, 0), SDValue(Dividend, 0),
- CurDAG->getTargetConstant(SubRegIdx, EVT::i32));
+ CurDAG->getTargetConstant(SubRegIdx, MVT::i32));
}
// Zero out even subreg
@@ -793,7 +793,7 @@
dl, NVT,
SDValue(Result, 0),
CurDAG->getTargetConstant(SubRegIdx,
- EVT::i32));
+ MVT::i32));
ReplaceUses(Op.getValue(0), SDValue(Div, 0));
#ifndef NDEBUG
DOUT << std::string(Indent-2, ' ') << "=> ";
@@ -809,7 +809,7 @@
dl, NVT,
SDValue(Result, 0),
CurDAG->getTargetConstant(SubRegIdx,
- EVT::i32));
+ MVT::i32));
ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
#ifndef NDEBUG
DOUT << std::string(Indent-2, ' ') << "=> ";
Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp Tue Aug 11 15:47:22 2009
@@ -44,14 +44,14 @@
RegInfo = TM.getRegisterInfo();
// Set up the register classes.
- addRegisterClass(EVT::i32, SystemZ::GR32RegisterClass);
- addRegisterClass(EVT::i64, SystemZ::GR64RegisterClass);
- addRegisterClass(EVT::v2i32,SystemZ::GR64PRegisterClass);
- addRegisterClass(EVT::v2i64,SystemZ::GR128RegisterClass);
+ addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
+ addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
+ addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass);
+ addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass);
if (!UseSoftFloat) {
- addRegisterClass(EVT::f32, SystemZ::FP32RegisterClass);
- addRegisterClass(EVT::f64, SystemZ::FP64RegisterClass);
+ addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
+ addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
addLegalFPImmediate(APFloat(+0.0)); // lzer
addLegalFPImmediate(APFloat(+0.0f)); // lzdr
@@ -63,92 +63,92 @@
computeRegisterProperties();
// Set shifts properties
- setShiftAmountType(EVT::i64);
+ setShiftAmountType(MVT::i64);
// Provide all sorts of operation actions
- setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote);
- setLoadExtAction(ISD::EXTLOAD, EVT::i1, Promote);
-
- setLoadExtAction(ISD::SEXTLOAD, EVT::f32, Expand);
- setLoadExtAction(ISD::ZEXTLOAD, EVT::f32, Expand);
- setLoadExtAction(ISD::EXTLOAD, EVT::f32, Expand);
-
- setLoadExtAction(ISD::SEXTLOAD, EVT::f64, Expand);
- setLoadExtAction(ISD::ZEXTLOAD, EVT::f64, Expand);
- setLoadExtAction(ISD::EXTLOAD, EVT::f64, Expand);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
+
+ setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand);
+ setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand);
+ setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
+
+ setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand);
+ setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand);
+ setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
setStackPointerRegisterToSaveRestore(SystemZ::R15D);
setSchedulingPreference(SchedulingForLatency);
setBooleanContents(ZeroOrOneBooleanContent);
- setOperationAction(ISD::BR_JT, EVT::Other, Expand);
- setOperationAction(ISD::BRCOND, EVT::Other, Expand);
- setOperationAction(ISD::BR_CC, EVT::i32, Custom);
- setOperationAction(ISD::BR_CC, EVT::i64, Custom);
- setOperationAction(ISD::BR_CC, EVT::f32, Custom);
- setOperationAction(ISD::BR_CC, EVT::f64, Custom);
- setOperationAction(ISD::ConstantPool, EVT::i32, Custom);
- setOperationAction(ISD::ConstantPool, EVT::i64, Custom);
- setOperationAction(ISD::GlobalAddress, EVT::i64, Custom);
- setOperationAction(ISD::JumpTable, EVT::i64, Custom);
- setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i64, Expand);
-
- setOperationAction(ISD::SDIV, EVT::i32, Expand);
- setOperationAction(ISD::UDIV, EVT::i32, Expand);
- setOperationAction(ISD::SDIV, EVT::i64, Expand);
- setOperationAction(ISD::UDIV, EVT::i64, Expand);
- setOperationAction(ISD::SREM, EVT::i32, Expand);
- setOperationAction(ISD::UREM, EVT::i32, Expand);
- setOperationAction(ISD::SREM, EVT::i64, Expand);
- setOperationAction(ISD::UREM, EVT::i64, Expand);
-
- setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand);
-
- setOperationAction(ISD::CTPOP, EVT::i32, Expand);
- setOperationAction(ISD::CTPOP, EVT::i64, Expand);
- setOperationAction(ISD::CTTZ, EVT::i32, Expand);
- setOperationAction(ISD::CTTZ, EVT::i64, Expand);
- setOperationAction(ISD::CTLZ, EVT::i32, Promote);
- setOperationAction(ISD::CTLZ, EVT::i64, Legal);
+ setOperationAction(ISD::BR_JT, MVT::Other, Expand);
+ setOperationAction(ISD::BRCOND, MVT::Other, Expand);
+ setOperationAction(ISD::BR_CC, MVT::i32, Custom);
+ setOperationAction(ISD::BR_CC, MVT::i64, Custom);
+ setOperationAction(ISD::BR_CC, MVT::f32, Custom);
+ setOperationAction(ISD::BR_CC, MVT::f64, Custom);
+ setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
+ setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
+ setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
+ setOperationAction(ISD::JumpTable, MVT::i64, Custom);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
+
+ setOperationAction(ISD::SDIV, MVT::i32, Expand);
+ setOperationAction(ISD::UDIV, MVT::i32, Expand);
+ setOperationAction(ISD::SDIV, MVT::i64, Expand);
+ setOperationAction(ISD::UDIV, MVT::i64, Expand);
+ setOperationAction(ISD::SREM, MVT::i32, Expand);
+ setOperationAction(ISD::UREM, MVT::i32, Expand);
+ setOperationAction(ISD::SREM, MVT::i64, Expand);
+ setOperationAction(ISD::UREM, MVT::i64, Expand);
+
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
+
+ setOperationAction(ISD::CTPOP, MVT::i32, Expand);
+ setOperationAction(ISD::CTPOP, MVT::i64, Expand);
+ setOperationAction(ISD::CTTZ, MVT::i32, Expand);
+ setOperationAction(ISD::CTTZ, MVT::i64, Expand);
+ setOperationAction(ISD::CTLZ, MVT::i32, Promote);
+ setOperationAction(ISD::CTLZ, MVT::i64, Legal);
// FIXME: Can we lower these 2 efficiently?
- setOperationAction(ISD::SETCC, EVT::i32, Expand);
- setOperationAction(ISD::SETCC, EVT::i64, Expand);
- setOperationAction(ISD::SETCC, EVT::f32, Expand);
- setOperationAction(ISD::SETCC, EVT::f64, Expand);
- setOperationAction(ISD::SELECT, EVT::i32, Expand);
- setOperationAction(ISD::SELECT, EVT::i64, Expand);
- setOperationAction(ISD::SELECT, EVT::f32, Expand);
- setOperationAction(ISD::SELECT, EVT::f64, Expand);
- setOperationAction(ISD::SELECT_CC, EVT::i32, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::i64, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::f32, Custom);
- setOperationAction(ISD::SELECT_CC, EVT::f64, Custom);
+ setOperationAction(ISD::SETCC, MVT::i32, Expand);
+ setOperationAction(ISD::SETCC, MVT::i64, Expand);
+ setOperationAction(ISD::SETCC, MVT::f32, Expand);
+ setOperationAction(ISD::SETCC, MVT::f64, Expand);
+ setOperationAction(ISD::SELECT, MVT::i32, Expand);
+ setOperationAction(ISD::SELECT, MVT::i64, Expand);
+ setOperationAction(ISD::SELECT, MVT::f32, Expand);
+ setOperationAction(ISD::SELECT, MVT::f64, Expand);
+ setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
+ setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
// Funny enough: we don't have 64-bit signed versions of these stuff, but have
// unsigned.
- setOperationAction(ISD::MULHS, EVT::i64, Expand);
- setOperationAction(ISD::SMUL_LOHI, EVT::i64, Expand);
+ setOperationAction(ISD::MULHS, MVT::i64, Expand);
+ setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
// Lower some FP stuff
- setOperationAction(ISD::FSIN, EVT::f32, Expand);
- setOperationAction(ISD::FSIN, EVT::f64, Expand);
- setOperationAction(ISD::FCOS, EVT::f32, Expand);
- setOperationAction(ISD::FCOS, EVT::f64, Expand);
- setOperationAction(ISD::FREM, EVT::f32, Expand);
- setOperationAction(ISD::FREM, EVT::f64, Expand);
+ setOperationAction(ISD::FSIN, MVT::f32, Expand);
+ setOperationAction(ISD::FSIN, MVT::f64, Expand);
+ setOperationAction(ISD::FCOS, MVT::f32, Expand);
+ setOperationAction(ISD::FCOS, MVT::f64, Expand);
+ setOperationAction(ISD::FREM, MVT::f32, Expand);
+ setOperationAction(ISD::FREM, MVT::f64, Expand);
// We have only 64-bit bitconverts
- setOperationAction(ISD::BIT_CONVERT, EVT::f32, Expand);
- setOperationAction(ISD::BIT_CONVERT, EVT::i32, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
- setOperationAction(ISD::UINT_TO_FP, EVT::i32, Expand);
- setOperationAction(ISD::UINT_TO_FP, EVT::i64, Expand);
- setOperationAction(ISD::FP_TO_UINT, EVT::i32, Expand);
- setOperationAction(ISD::FP_TO_UINT, EVT::i64, Expand);
+ setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
+ setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
- setTruncStoreAction(EVT::f64, EVT::f32, Expand);
+ setTruncStoreAction(MVT::f64, MVT::f32, Expand);
}
SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
@@ -242,21 +242,21 @@
if (VA.isRegLoc()) {
// Arguments passed in registers
TargetRegisterClass *RC;
- switch (LocVT.getSimpleVT()) {
+ switch (LocVT.getSimpleVT().SimpleTy) {
default:
#ifndef NDEBUG
cerr << "LowerFormalArguments Unhandled argument type: "
- << LocVT.getSimpleVT()
+ << LocVT.getSimpleVT().SimpleTy
<< "\n";
#endif
llvm_unreachable(0);
- case EVT::i64:
+ case MVT::i64:
RC = SystemZ::GR64RegisterClass;
break;
- case EVT::f32:
+ case MVT::f32:
RC = SystemZ::FP32RegisterClass;
break;
- case EVT::f64:
+ case MVT::f64:
RC = SystemZ::FP64RegisterClass;
break;
}
@@ -382,7 +382,7 @@
// Transform all store nodes into one single node because all store nodes are
// independent of each other.
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token chain and
@@ -404,7 +404,7 @@
Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
// Returns a chain & a flag for retval copy to use.
- SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag);
+ SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
@@ -530,10 +530,10 @@
}
if (Flag.getNode())
- return DAG.getNode(SystemZISD::RET_FLAG, dl, EVT::Other, Chain, Flag);
+ return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
// Return Void
- return DAG.getNode(SystemZISD::RET_FLAG, dl, EVT::Other, Chain);
+ return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain);
}
SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
@@ -608,11 +608,11 @@
break;
}
- SystemZCC = DAG.getConstant(TCC, EVT::i32);
+ SystemZCC = DAG.getConstant(TCC, MVT::i32);
DebugLoc dl = LHS.getDebugLoc();
return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
- dl, EVT::Flag, LHS, RHS);
+ dl, MVT::Flag, LHS, RHS);
}
@@ -641,7 +641,7 @@
SDValue SystemZCC;
SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
- SDVTList VTs = DAG.getVTList(Op.getValueType(), EVT::Flag);
+ SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
SmallVector<SDValue, 4> Ops;
Ops.push_back(TrueV);
Ops.push_back(FalseV);
Modified: llvm/trunk/lib/Target/SystemZ/SystemZOperands.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZOperands.td?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZOperands.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZOperands.td Tue Aug 11 15:47:22 2009
@@ -134,10 +134,10 @@
def immSExt16 : PatLeaf<(imm), [{
// immSExt16 predicate - true if the immediate fits in a 16-bit sign extended
// field.
- if (N->getValueType(0) == EVT::i64) {
+ if (N->getValueType(0) == MVT::i64) {
uint64_t val = N->getZExtValue();
return ((int64_t)val == (int16_t)val);
- } else if (N->getValueType(0) == EVT::i32) {
+ } else if (N->getValueType(0) == MVT::i32) {
uint32_t val = N->getZExtValue();
return ((int32_t)val == (int16_t)val);
}
Modified: llvm/trunk/lib/Target/TargetRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetRegisterInfo.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/TargetRegisterInfo.cpp Tue Aug 11 15:47:22 2009
@@ -51,7 +51,7 @@
const TargetRegisterClass* BestRC = 0;
for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
const TargetRegisterClass* RC = *I;
- if ((VT == EVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
+ if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
(!BestRC || BestRC->hasSuperClass(RC)))
BestRC = RC;
}
Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Tue Aug 11 15:47:22 2009
@@ -426,8 +426,8 @@
unsigned Reg = MO.getReg();
if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
EVT VT = (strcmp(Modifier+6,"64") == 0) ?
- EVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? EVT::i32 :
- ((strcmp(Modifier+6,"16") == 0) ? EVT::i16 : EVT::i8));
+ MVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? MVT::i32 :
+ ((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
Reg = getX86SubSuperRegister(Reg, VT);
}
O << TRI->getAsmName(Reg);
@@ -573,19 +573,19 @@
switch (Mode) {
default: return true; // Unknown mode.
case 'b': // Print QImode register
- Reg = getX86SubSuperRegister(Reg, EVT::i8);
+ Reg = getX86SubSuperRegister(Reg, MVT::i8);
break;
case 'h': // Print QImode high register
- Reg = getX86SubSuperRegister(Reg, EVT::i8, true);
+ Reg = getX86SubSuperRegister(Reg, MVT::i8, true);
break;
case 'w': // Print HImode register
- Reg = getX86SubSuperRegister(Reg, EVT::i16);
+ Reg = getX86SubSuperRegister(Reg, MVT::i16);
break;
case 'k': // Print SImode register
- Reg = getX86SubSuperRegister(Reg, EVT::i32);
+ Reg = getX86SubSuperRegister(Reg, MVT::i32);
break;
case 'q': // Print DImode register
- Reg = getX86SubSuperRegister(Reg, EVT::i64);
+ Reg = getX86SubSuperRegister(Reg, MVT::i64);
break;
}
@@ -685,7 +685,7 @@
unsigned Reg = MI->getOperand(i).getReg();
if (Reg == 0) continue;
- MI->getOperand(i).setReg(getX86SubSuperRegister(Reg, EVT::i64));
+ MI->getOperand(i).setReg(getX86SubSuperRegister(Reg, MVT::i64));
}
}
Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp Tue Aug 11 15:47:22 2009
@@ -210,8 +210,8 @@
unsigned Reg = MO.getReg();
if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
EVT VT = (strcmp(Modifier,"subreg64") == 0) ?
- EVT::i64 : ((strcmp(Modifier, "subreg32") == 0) ? EVT::i32 :
- ((strcmp(Modifier,"subreg16") == 0) ? EVT::i16 :EVT::i8));
+ MVT::i64 : ((strcmp(Modifier, "subreg32") == 0) ? MVT::i32 :
+ ((strcmp(Modifier,"subreg16") == 0) ? MVT::i16 :MVT::i8));
Reg = getX86SubSuperRegister(Reg, VT);
}
O << TRI->getName(Reg);
@@ -376,16 +376,16 @@
switch (Mode) {
default: return true; // Unknown mode.
case 'b': // Print QImode register
- Reg = getX86SubSuperRegister(Reg, EVT::i8);
+ Reg = getX86SubSuperRegister(Reg, MVT::i8);
break;
case 'h': // Print QImode high register
- Reg = getX86SubSuperRegister(Reg, EVT::i8, true);
+ Reg = getX86SubSuperRegister(Reg, MVT::i8, true);
break;
case 'w': // Print HImode register
- Reg = getX86SubSuperRegister(Reg, EVT::i16);
+ Reg = getX86SubSuperRegister(Reg, MVT::i16);
break;
case 'k': // Print SImode register
- Reg = getX86SubSuperRegister(Reg, EVT::i32);
+ Reg = getX86SubSuperRegister(Reg, MVT::i32);
break;
}
Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Tue Aug 11 15:47:22 2009
@@ -134,8 +134,8 @@
/// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
/// computed in an SSE register, not on the X87 floating point stack.
bool isScalarFPTypeInSSEReg(EVT VT) const {
- return (VT == EVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
- (VT == EVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
+ return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
+ (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
}
bool isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1 = false);
@@ -145,24 +145,24 @@
bool X86FastISel::isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1) {
VT = TLI.getValueType(Ty, /*HandleUnknown=*/true);
- if (VT == EVT::Other || !VT.isSimple())
+ if (VT == MVT::Other || !VT.isSimple())
// Unhandled type. Halt "fast" selection and bail.
return false;
// For now, require SSE/SSE2 for performing floating-point operations,
// since x87 requires additional work.
- if (VT == EVT::f64 && !X86ScalarSSEf64)
+ if (VT == MVT::f64 && !X86ScalarSSEf64)
return false;
- if (VT == EVT::f32 && !X86ScalarSSEf32)
+ if (VT == MVT::f32 && !X86ScalarSSEf32)
return false;
// Similarly, no f80 support yet.
- if (VT == EVT::f80)
+ if (VT == MVT::f80)
return false;
// We only handle legal types. For example, on x86-32 the instruction
// selector contains all of the 64-bit instructions from x86-64,
// under the assumption that i64 won't be used if the target doesn't
// support it.
- return (AllowI1 && VT == EVT::i1) || TLI.isTypeLegal(VT);
+ return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
}
#include "X86GenCallingConv.inc"
@@ -193,26 +193,26 @@
// Get opcode and regclass of the output for the given load instruction.
unsigned Opc = 0;
const TargetRegisterClass *RC = NULL;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: return false;
- case EVT::i8:
+ case MVT::i8:
Opc = X86::MOV8rm;
RC = X86::GR8RegisterClass;
break;
- case EVT::i16:
+ case MVT::i16:
Opc = X86::MOV16rm;
RC = X86::GR16RegisterClass;
break;
- case EVT::i32:
+ case MVT::i32:
Opc = X86::MOV32rm;
RC = X86::GR32RegisterClass;
break;
- case EVT::i64:
+ case MVT::i64:
// Must be in x86-64 mode.
Opc = X86::MOV64rm;
RC = X86::GR64RegisterClass;
break;
- case EVT::f32:
+ case MVT::f32:
if (Subtarget->hasSSE1()) {
Opc = X86::MOVSSrm;
RC = X86::FR32RegisterClass;
@@ -221,7 +221,7 @@
RC = X86::RFP32RegisterClass;
}
break;
- case EVT::f64:
+ case MVT::f64:
if (Subtarget->hasSSE2()) {
Opc = X86::MOVSDrm;
RC = X86::FR64RegisterClass;
@@ -230,7 +230,7 @@
RC = X86::RFP64RegisterClass;
}
break;
- case EVT::f80:
+ case MVT::f80:
// No f80 support yet.
return false;
}
@@ -249,17 +249,17 @@
const X86AddressMode &AM) {
// Get opcode and regclass of the output for the given store instruction.
unsigned Opc = 0;
- switch (VT.getSimpleVT()) {
- case EVT::f80: // No f80 support yet.
+ switch (VT.getSimpleVT().SimpleTy) {
+ case MVT::f80: // No f80 support yet.
default: return false;
- case EVT::i8: Opc = X86::MOV8mr; break;
- case EVT::i16: Opc = X86::MOV16mr; break;
- case EVT::i32: Opc = X86::MOV32mr; break;
- case EVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
- case EVT::f32:
+ case MVT::i8: Opc = X86::MOV8mr; break;
+ case MVT::i16: Opc = X86::MOV16mr; break;
+ case MVT::i32: Opc = X86::MOV32mr; break;
+ case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
+ case MVT::f32:
Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m;
break;
- case EVT::f64:
+ case MVT::f64:
Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m;
break;
}
@@ -277,12 +277,12 @@
// If this is a store of a simple constant, fold the constant into the store.
if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
unsigned Opc = 0;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: break;
- case EVT::i8: Opc = X86::MOV8mi; break;
- case EVT::i16: Opc = X86::MOV16mi; break;
- case EVT::i32: Opc = X86::MOV32mi; break;
- case EVT::i64:
+ case MVT::i8: Opc = X86::MOV8mi; break;
+ case MVT::i16: Opc = X86::MOV16mi; break;
+ case MVT::i32: Opc = X86::MOV32mi; break;
+ case MVT::i64:
// Must be a 32-bit sign extended value.
if ((int)CI->getSExtValue() == CI->getSExtValue())
Opc = X86::MOV64mi32;
@@ -478,7 +478,7 @@
StubAM.GV = GV;
StubAM.GVOpFlags = GVFlags;
- if (TLI.getPointerTy() == EVT::i64) {
+ if (TLI.getPointerTy() == MVT::i64) {
Opc = X86::MOV64rm;
RC = X86::GR64RegisterClass;
@@ -636,14 +636,14 @@
}
static unsigned X86ChooseCmpOpcode(EVT VT) {
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: return 0;
- case EVT::i8: return X86::CMP8rr;
- case EVT::i16: return X86::CMP16rr;
- case EVT::i32: return X86::CMP32rr;
- case EVT::i64: return X86::CMP64rr;
- case EVT::f32: return X86::UCOMISSrr;
- case EVT::f64: return X86::UCOMISDrr;
+ case MVT::i8: return X86::CMP8rr;
+ case MVT::i16: return X86::CMP16rr;
+ case MVT::i32: return X86::CMP32rr;
+ case MVT::i64: return X86::CMP64rr;
+ case MVT::f32: return X86::UCOMISSrr;
+ case MVT::f64: return X86::UCOMISDrr;
}
}
@@ -651,13 +651,13 @@
/// of the comparison, return an opcode that works for the compare (e.g.
/// CMP32ri) otherwise return 0.
static unsigned X86ChooseCmpImmediateOpcode(EVT VT, ConstantInt *RHSC) {
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
// Otherwise, we can't fold the immediate into this comparison.
default: return 0;
- case EVT::i8: return X86::CMP8ri;
- case EVT::i16: return X86::CMP16ri;
- case EVT::i32: return X86::CMP32ri;
- case EVT::i64:
+ case MVT::i8: return X86::CMP8ri;
+ case MVT::i16: return X86::CMP16ri;
+ case MVT::i32: return X86::CMP32ri;
+ case MVT::i64:
// 64-bit comparisons are only valid if the immediate fits in a 32-bit sext
// field.
if ((int)RHSC->getSExtValue() == RHSC->getSExtValue())
@@ -778,7 +778,7 @@
unsigned ResultReg = getRegForValue(I->getOperand(0));
if (ResultReg == 0) return false;
// Set the high bits to zero.
- ResultReg = FastEmitZExtFromI1(EVT::i8, ResultReg);
+ ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg);
if (ResultReg == 0) return false;
UpdateValueMap(I, ResultReg);
return true;
@@ -976,7 +976,7 @@
}
EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
- if (VT == EVT::Other || !isTypeLegal(I->getType(), VT))
+ if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
return false;
unsigned Op0Reg = getRegForValue(I->getOperand(0));
@@ -1010,18 +1010,18 @@
bool X86FastISel::X86SelectSelect(Instruction *I) {
EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
- if (VT == EVT::Other || !isTypeLegal(I->getType(), VT))
+ if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
return false;
unsigned Opc = 0;
const TargetRegisterClass *RC = NULL;
- if (VT.getSimpleVT() == EVT::i16) {
+ if (VT.getSimpleVT() == MVT::i16) {
Opc = X86::CMOVE16rr;
RC = &X86::GR16RegClass;
- } else if (VT.getSimpleVT() == EVT::i32) {
+ } else if (VT.getSimpleVT() == MVT::i32) {
Opc = X86::CMOVE32rr;
RC = &X86::GR32RegClass;
- } else if (VT.getSimpleVT() == EVT::i64) {
+ } else if (VT.getSimpleVT() == MVT::i64) {
Opc = X86::CMOVE64rr;
RC = &X86::GR64RegClass;
} else {
@@ -1085,10 +1085,10 @@
EVT DstVT = TLI.getValueType(I->getType());
// This code only handles truncation to byte right now.
- if (DstVT != EVT::i8 && DstVT != EVT::i1)
+ if (DstVT != MVT::i8 && DstVT != MVT::i1)
// All other cases should be handled by the tblgen generated code.
return false;
- if (SrcVT != EVT::i16 && SrcVT != EVT::i32)
+ if (SrcVT != MVT::i16 && SrcVT != MVT::i32)
// All other cases should be handled by the tblgen generated code.
return false;
@@ -1098,14 +1098,14 @@
return false;
// First issue a copy to GR16_ABCD or GR32_ABCD.
- unsigned CopyOpc = (SrcVT == EVT::i16) ? X86::MOV16rr : X86::MOV32rr;
- const TargetRegisterClass *CopyRC = (SrcVT == EVT::i16)
+ unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16rr : X86::MOV32rr;
+ const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass;
unsigned CopyReg = createResultReg(CopyRC);
BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg);
// Then issue an extract_subreg.
- unsigned ResultReg = FastEmitInst_extractsubreg(EVT::i8,
+ unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8,
CopyReg, X86::SUBREG_8BIT);
if (!ResultReg)
return false;
@@ -1164,9 +1164,9 @@
return false;
unsigned OpC = 0;
- if (VT == EVT::i32)
+ if (VT == MVT::i32)
OpC = X86::ADD32rr;
- else if (VT == EVT::i64)
+ else if (VT == MVT::i64)
OpC = X86::ADD64rr;
else
return false;
@@ -1185,7 +1185,7 @@
if (DestReg1 != ResultReg)
ResultReg = DestReg1+1;
else
- ResultReg = createResultReg(TLI.getRegClassFor(EVT::i8));
+ ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8));
unsigned Opc = X86::SETBr;
if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow)
@@ -1231,7 +1231,7 @@
const Type *RetTy = CS.getType();
EVT RetVT;
if (RetTy == Type::VoidTy)
- RetVT = EVT::isVoid;
+ RetVT = MVT::isVoid;
else if (!isTypeLegal(RetTy, RetVT, true))
return false;
@@ -1251,8 +1251,8 @@
// Allow calls which produce i1 results.
bool AndToI1 = false;
- if (RetVT == EVT::i1) {
- RetVT = EVT::i8;
+ if (RetVT == MVT::i1) {
+ RetVT = MVT::i8;
AndToI1 = true;
}
@@ -1445,7 +1445,7 @@
BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
// Now handle call return value (if any).
- if (RetVT.getSimpleVT() != EVT::isVoid) {
+ if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) {
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CC, false, TM, RVLocs, I->getParent()->getContext());
CCInfo.AnalyzeCallResult(RetVT, RetCC_X86);
@@ -1462,7 +1462,7 @@
if ((RVLocs[0].getLocReg() == X86::ST0 ||
RVLocs[0].getLocReg() == X86::ST1) &&
isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) {
- CopyVT = EVT::f80;
+ CopyVT = MVT::f80;
SrcRC = X86::RSTRegisterClass;
DstRC = X86::RFP80RegisterClass;
}
@@ -1477,13 +1477,13 @@
// register. This is accomplished by storing the F80 value in memory and
// then loading it back. Ewww...
EVT ResVT = RVLocs[0].getValVT();
- unsigned Opc = ResVT == EVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
+ unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
unsigned MemSize = ResVT.getSizeInBits()/8;
int FI = MFI.CreateStackObject(MemSize, MemSize);
addFrameReference(BuildMI(MBB, DL, TII.get(Opc)), FI).addReg(ResultReg);
- DstRC = ResVT == EVT::f32
+ DstRC = ResVT == MVT::f32
? X86::FR32RegisterClass : X86::FR64RegisterClass;
- Opc = ResVT == EVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
+ Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
ResultReg = createResultReg(DstRC);
addFrameReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), FI);
}
@@ -1560,26 +1560,26 @@
// Get opcode and regclass of the output for the given load instruction.
unsigned Opc = 0;
const TargetRegisterClass *RC = NULL;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: return false;
- case EVT::i8:
+ case MVT::i8:
Opc = X86::MOV8rm;
RC = X86::GR8RegisterClass;
break;
- case EVT::i16:
+ case MVT::i16:
Opc = X86::MOV16rm;
RC = X86::GR16RegisterClass;
break;
- case EVT::i32:
+ case MVT::i32:
Opc = X86::MOV32rm;
RC = X86::GR32RegisterClass;
break;
- case EVT::i64:
+ case MVT::i64:
// Must be in x86-64 mode.
Opc = X86::MOV64rm;
RC = X86::GR64RegisterClass;
break;
- case EVT::f32:
+ case MVT::f32:
if (Subtarget->hasSSE1()) {
Opc = X86::MOVSSrm;
RC = X86::FR32RegisterClass;
@@ -1588,7 +1588,7 @@
RC = X86::RFP32RegisterClass;
}
break;
- case EVT::f64:
+ case MVT::f64:
if (Subtarget->hasSSE2()) {
Opc = X86::MOVSDrm;
RC = X86::FR64RegisterClass;
@@ -1597,7 +1597,7 @@
RC = X86::RFP64RegisterClass;
}
break;
- case EVT::f80:
+ case MVT::f80:
// No f80 support yet.
return false;
}
@@ -1606,7 +1606,7 @@
if (isa<GlobalValue>(C)) {
X86AddressMode AM;
if (X86SelectAddress(C, AM)) {
- if (TLI.getPointerTy() == EVT::i32)
+ if (TLI.getPointerTy() == MVT::i32)
Opc = X86::LEA32r;
else
Opc = X86::LEA64r;
Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=78713&r1=78712&r2=78713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Aug 11 15:47:22 2009
@@ -233,40 +233,40 @@
// These are 32-bit even in 64-bit mode since RIP relative offset
// is 32-bit.
if (AM.GV)
- Disp = CurDAG->getTargetGlobalAddress(AM.GV, EVT::i32, AM.Disp,
+ Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp,
AM.SymbolFlags);
else if (AM.CP)
- Disp = CurDAG->getTargetConstantPool(AM.CP, EVT::i32,
+ Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
AM.Align, AM.Disp, AM.SymbolFlags);
else if (AM.ES)
- Disp = CurDAG->getTargetExternalSymbol(AM.ES, EVT::i32, AM.SymbolFlags);
+ Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
else if (AM.JT != -1)
- Disp = CurDAG->getTargetJumpTable(AM.JT, EVT::i32, AM.SymbolFlags);
+ Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
else
- Disp = CurDAG->getTargetConstant(AM.Disp, EVT::i32);
+ Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
if (AM.Segment.getNode())
Segment = AM.Segment;
else
- Segment = CurDAG->getRegister(0, EVT::i32);
+ Segment = CurDAG->getRegister(0, MVT::i32);
}
/// getI8Imm - Return a target constant with the specified value, of type
/// i8.
inline SDValue getI8Imm(unsigned Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i8);
+ return CurDAG->getTargetConstant(Imm, MVT::i8);
}
/// getI16Imm - Return a target constant with the specified value, of type
/// i16.
inline SDValue getI16Imm(unsigned Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i16);
+ return CurDAG->getTargetConstant(Imm, MVT::i16);
}
/// getI32Imm - Return a target constant with the specified value, of type
/// i32.
inline SDValue getI32Imm(unsigned Imm) {
- return CurDAG->getTargetConstant(Imm, EVT::i32);
+ return CurDAG->getTargetConstant(Imm, MVT::i32);
}
/// getGlobalBaseReg - Return an SDNode that returns the value of
@@ -408,7 +408,7 @@
Ops.push_back(Chain.getOperand(i));
SDValue NewChain =
CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc(),
- EVT::Other, &Ops[0], Ops.size());
+ MVT::Other, &Ops[0], Ops.size());
Ops.clear();
Ops.push_back(NewChain);
}
@@ -764,7 +764,7 @@
}
if (N.getOpcode() == X86ISD::WrapperRIP)
- AM.setBaseReg(CurDAG->getRegister(X86::RIP, EVT::i64));
+ AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
return false;
}
@@ -1001,7 +1001,7 @@
RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
(RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
- RHS.getNode()->getOperand(0).getValueType() == EVT::i32))
+ RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
++Cost;
// If the base is a register with multiple uses, this
// transformation may save a mov.
@@ -1111,13 +1111,13 @@
unsigned ScaleLog = 8 - C1->getZExtValue();
if (ScaleLog > 0 && ScaleLog < 4 &&
C2->getZExtValue() == (UINT64_C(0xff) << ScaleLog)) {
- SDValue Eight = CurDAG->getConstant(8, EVT::i8);
+ SDValue Eight = CurDAG->getConstant(8, MVT::i8);
SDValue Mask = CurDAG->getConstant(0xff, N.getValueType());
SDValue Srl = CurDAG->getNode(ISD::SRL, dl, N.getValueType(),
X, Eight);
SDValue And = CurDAG->getNode(ISD::AND, dl, N.getValueType(),
Srl, Mask);
- SDValue ShlCount = CurDAG->getConstant(ScaleLog, EVT::i8);
+ SDValue ShlCount = CurDAG->getConstant(ScaleLog, MVT::i8);
SDValue Shl = CurDAG->getNode(ISD::SHL, dl, N.getValueType(),
And, ShlCount);
@@ -1333,7 +1333,7 @@
// Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
// segments.
SDValue Copy = AM.Segment;
- SDValue T = CurDAG->getRegister(0, EVT::i32);
+ SDValue T = CurDAG->getRegister(0, MVT::i32);
AM.Segment = T;
if (MatchAddress(N, AM))
return false;
@@ -1400,11 +1400,11 @@
AM.Base.Reg = CurDAG->getRegister(0, N.getValueType());
AM.SymbolFlags = GA->getTargetFlags();
- if (N.getValueType() == EVT::i32) {
+ if (N.getValueType() == MVT::i32) {
AM.Scale = 1;
- AM.IndexReg = CurDAG->getRegister(X86::EBX, EVT::i32);
+ AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
} else {
- AM.IndexReg = CurDAG->getRegister(0, EVT::i64);
+ AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
}
SDValue Segment;
@@ -1435,7 +1435,7 @@
static SDNode *FindCallStartFromCall(SDNode *Node) {
if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
- assert(Node->getOperand(0).getValueType() == EVT::Other &&
+ assert(Node->getOperand(0).getValueType() == MVT::Other &&
"Node doesn't have a token chain argument!");
return FindCallStartFromCall(Node->getOperand(0).getNode());
}
@@ -1451,7 +1451,7 @@
SDValue LSI = Node->getOperand(4); // MemOperand
const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, LSI, Chain};
return CurDAG->getTargetNode(Opc, Node->getDebugLoc(),
- EVT::i32, EVT::i32, EVT::Other, Ops,
+ MVT::i32, MVT::i32, MVT::Other, Ops,
array_lengthof(Ops));
}
@@ -1495,9 +1495,9 @@
}
unsigned Opc = 0;
- switch (NVT.getSimpleVT()) {
+ switch (NVT.getSimpleVT().SimpleTy) {
default: return 0;
- case EVT::i8:
+ case MVT::i8:
if (isInc)
Opc = X86::LOCK_INC8m;
else if (isDec)
@@ -1514,7 +1514,7 @@
Opc = X86::LOCK_ADD8mr;
}
break;
- case EVT::i16:
+ case MVT::i16:
if (isInc)
Opc = X86::LOCK_INC16m;
else if (isDec)
@@ -1537,7 +1537,7 @@
Opc = X86::LOCK_ADD16mr;
}
break;
- case EVT::i32:
+ case MVT::i32:
if (isInc)
Opc = X86::LOCK_INC32m;
else if (isDec)
@@ -1560,7 +1560,7 @@
Opc = X86::LOCK_ADD32mr;
}
break;
- case EVT::i64:
+ case MVT::i64:
if (isInc)
Opc = X86::LOCK_INC64m;
else if (isDec)
@@ -1591,12 +1591,12 @@
SDValue MemOp = CurDAG->getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
if (isInc || isDec) {
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, MemOp, Chain };
- SDValue Ret = SDValue(CurDAG->getTargetNode(Opc, dl, EVT::Other, Ops, 7), 0);
+ SDValue Ret = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7), 0);
SDValue RetVals[] = { Undef, Ret };
return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
} else {
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, MemOp, Chain };
- SDValue Ret = SDValue(CurDAG->getTargetNode(Opc, dl, EVT::Other, Ops, 8), 0);
+ SDValue Ret = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 8), 0);
SDValue RetVals[] = { Undef, Ret };
return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
}
@@ -1664,30 +1664,30 @@
bool isSigned = Opcode == ISD::SMUL_LOHI;
if (!isSigned) {
- switch (NVT.getSimpleVT()) {
+ switch (NVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unsupported VT!");
- case EVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
- case EVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
- case EVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
- case EVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
+ case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
+ case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
+ case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
+ case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
}
} else {
- switch (NVT.getSimpleVT()) {
+ switch (NVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unsupported VT!");
- case EVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
- case EVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
- case EVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
- case EVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
+ case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
+ case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
+ case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
+ case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
}
}
unsigned LoReg, HiReg;
- switch (NVT.getSimpleVT()) {
+ switch (NVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unsupported VT!");
- case EVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
- case EVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
- case EVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
- case EVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
+ case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
+ case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
+ case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
+ case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
}
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
@@ -1706,14 +1706,14 @@
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
InFlag };
SDNode *CNode =
- CurDAG->getTargetNode(MOpc, dl, EVT::Other, EVT::Flag, Ops,
+ CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
array_lengthof(Ops));
InFlag = SDValue(CNode, 1);
// Update the chain.
ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
} else {
InFlag =
- SDValue(CurDAG->getTargetNode(Opc, dl, EVT::Flag, N1, InFlag), 0);
+ SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
}
// Copy the low half of the result, if it is needed.
@@ -1737,15 +1737,15 @@
// Prevent use of AH in a REX instruction by referencing AX instead.
// Shift it down 8 bits.
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
- X86::AX, EVT::i16, InFlag);
+ X86::AX, MVT::i16, InFlag);
InFlag = Result.getValue(2);
- Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, EVT::i16,
+ Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16,
Result,
- CurDAG->getTargetConstant(8, EVT::i8)), 0);
+ CurDAG->getTargetConstant(8, MVT::i8)), 0);
// Then truncate it down to i8.
- SDValue SRIdx = CurDAG->getTargetConstant(X86::SUBREG_8BIT, EVT::i32);
+ SDValue SRIdx = CurDAG->getTargetConstant(X86::SUBREG_8BIT, MVT::i32);
Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl,
- EVT::i8, Result, SRIdx), 0);
+ MVT::i8, Result, SRIdx), 0);
} else {
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
HiReg, NVT, InFlag);
@@ -1775,43 +1775,43 @@
bool isSigned = Opcode == ISD::SDIVREM;
if (!isSigned) {
- switch (NVT.getSimpleVT()) {
+ switch (NVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unsupported VT!");
- case EVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
- case EVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
- case EVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
- case EVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
+ case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
+ case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
+ case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
+ case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
}
} else {
- switch (NVT.getSimpleVT()) {
+ switch (NVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unsupported VT!");
- case EVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
- case EVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
- case EVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
- case EVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
+ case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
+ case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
+ case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
+ case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
}
}
unsigned LoReg, HiReg;
unsigned ClrOpcode, SExtOpcode;
- switch (NVT.getSimpleVT()) {
+ switch (NVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unsupported VT!");
- case EVT::i8:
+ case MVT::i8:
LoReg = X86::AL; HiReg = X86::AH;
ClrOpcode = 0;
SExtOpcode = X86::CBW;
break;
- case EVT::i16:
+ case MVT::i16:
LoReg = X86::AX; HiReg = X86::DX;
ClrOpcode = X86::MOV16r0;
SExtOpcode = X86::CWD;
break;
- case EVT::i32:
+ case MVT::i32:
LoReg = X86::EAX; HiReg = X86::EDX;
ClrOpcode = X86::MOV32r0;
SExtOpcode = X86::CDQ;
break;
- case EVT::i64:
+ case MVT::i64:
LoReg = X86::RAX; HiReg = X86::RDX;
ClrOpcode = ~0U; // NOT USED.
SExtOpcode = X86::CQO;
@@ -1823,21 +1823,21 @@
bool signBitIsZero = CurDAG->SignBitIsZero(N0);
SDValue InFlag;
- if (NVT == EVT::i8 && (!isSigned || signBitIsZero)) {
+ if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
// Special case for div8, just use a move with zero extension to AX to
// clear the upper 8 bits (AH).
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
Move =
- SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, dl, EVT::i16,
- EVT::Other, Ops,
+ SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, dl, MVT::i16,
+ MVT::Other, Ops,
array_lengthof(Ops)), 0);
Chain = Move.getValue(1);
ReplaceUses(N0.getValue(1), Chain);
} else {
Move =
- SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, dl, EVT::i16, N0),0);
+ SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, dl, MVT::i16, N0),0);
Chain = CurDAG->getEntryNode();
}
Chain = CurDAG->getCopyToReg(Chain, dl, X86::AX, Move, SDValue());
@@ -1849,24 +1849,24 @@
if (isSigned && !signBitIsZero) {
// Sign extend the low part into the high part.
InFlag =
- SDValue(CurDAG->getTargetNode(SExtOpcode, dl, EVT::Flag, InFlag),0);
+ SDValue(CurDAG->getTargetNode(SExtOpcode, dl, MVT::Flag, InFlag),0);
} else {
// Zero out the high part, effectively zero extending the input.
SDValue ClrNode;
- if (NVT.getSimpleVT() == EVT::i64) {
- ClrNode = SDValue(CurDAG->getTargetNode(X86::MOV32r0, dl, EVT::i32),
+ if (NVT.getSimpleVT() == MVT::i64) {
+ ClrNode = SDValue(CurDAG->getTargetNode(X86::MOV32r0, dl, MVT::i32),
0);
// We just did a 32-bit clear, insert it into a 64-bit register to
// clear the whole 64-bit reg.
SDValue Undef =
SDValue(CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF,
- dl, EVT::i64), 0);
+ dl, MVT::i64), 0);
SDValue SubRegNo =
- CurDAG->getTargetConstant(X86::SUBREG_32BIT, EVT::i32);
+ CurDAG->getTargetConstant(X86::SUBREG_32BIT, MVT::i32);
ClrNode =
SDValue(CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl,
- EVT::i64, Undef, ClrNode, SubRegNo),
+ MVT::i64, Undef, ClrNode, SubRegNo),
0);
} else {
ClrNode = SDValue(CurDAG->getTargetNode(ClrOpcode, dl, NVT), 0);
@@ -1881,14 +1881,14 @@
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
InFlag };
SDNode *CNode =
- CurDAG->getTargetNode(MOpc, dl, EVT::Other, EVT::Flag, Ops,
+ CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
array_lengthof(Ops));
InFlag = SDValue(CNode, 1);
// Update the chain.
ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
} else {
InFlag =
- SDValue(CurDAG->getTargetNode(Opc, dl, EVT::Flag, N1, InFlag), 0);
+ SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
}
// Copy the division (low) result, if it is needed.
@@ -1912,16 +1912,16 @@
// Prevent use of AH in a REX instruction by referencing AX instead.
// Shift it down 8 bits.
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
- X86::AX, EVT::i16, InFlag);
+ X86::AX, MVT::i16, InFlag);
InFlag = Result.getValue(2);
- Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, EVT::i16,
+ Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16,
Result,
- CurDAG->getTargetConstant(8, EVT::i8)),
+ CurDAG->getTargetConstant(8, MVT::i8)),
0);
// Then truncate it down to i8.
- SDValue SRIdx = CurDAG->getTargetConstant(X86::SUBREG_8BIT, EVT::i32);
+ SDValue SRIdx = CurDAG->getTargetConstant(X86::SUBREG_8BIT, MVT::i32);
Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl,
- EVT::i8, Result, SRIdx), 0);
+ MVT::i8, Result, SRIdx), 0);
} else {
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
HiReg, NVT, InFlag);
@@ -1981,7 +1981,7 @@
TLI.getPointerTy());
SDValue Ops[] = { Tmp1, Tmp2, Chain };
return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl,
- EVT::Other, Ops,
+ MVT::Other, Ops,
array_lengthof(Ops));
}
}
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