[llvm-commits] [llvm] r78563 - in /llvm/trunk: include/llvm/CodeGen/ScheduleHazardRecognizer.h include/llvm/Target/TargetInstrItineraries.h lib/CodeGen/CMakeLists.txt lib/CodeGen/ExactHazardRecognizer.cpp lib/CodeGen/ExactHazardRecognizer.h lib/CodeGen/PostRASchedulerList.cpp lib/CodeGen/ScheduleDAGInstrs.cpp lib/CodeGen/SimpleHazardRecognizer.h

Dan Gohman gohman at apple.com
Tue Aug 11 11:59:51 PDT 2009


On Aug 10, 2009, at 4:38 PM, David Goodwin wrote:

> Issuing two+ instructions in the same cycle that write the same
> register is defined as producing an undefined result by all
> architectures I am familiar with. For a super-scalar style issue, the
> processor will just prevent these from dual issuing, issuing the first
> in one cycle and the next in a later cycle. In a VLIW processor you
> will likely get an undefined value. In either case we can correctly
> model by leaving the Output dependence latency at 1.

With register renaming, a super-scalar processor could issue
two instructions that write to the same architectural register in the  
same
cycle. It's the same as anti-dependencies.

>
> BTW, I left the TODO there even though I don't understand it. Are
> there really processor implementations that have a cost for reusing a
> register?

I don't have any examples in mind; it was more a hypothetical comment.

To make this code fully general, I guess there should be no hard-coded
non-zero latency for either anti dependence or output dependence, and
it ought to be the responsibility of the hazard recognizer to assign
penalties for output dependencies and so on. However, until we have a
target where this matters, I think just having comments that explain
the situation are fine.

Dan




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