[llvm-commits] [llvm] r78604 - in /llvm/trunk: lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/ARMInstrVFP.td test/CodeGen/ARM/fsitos.ll test/CodeGen/ARM/ftosizs.ll test/CodeGen/ARM/ftouizs.ll test/CodeGen/ARM/fuitos.ll
Evan Cheng
evan.cheng at apple.com
Mon Aug 10 15:28:30 PDT 2009
Thanks David. Can you convert the tests to FileCheck ones? I am
converting a lot of existing ones to FileCheck as I intend to turn on
32-bit to 16-bit shrinkage pass?
Evan
On Aug 10, 2009, at 3:17 PM, David Goodwin wrote:
> Author: david_goodwin
> Date: Mon Aug 10 17:17:39 2009
> New Revision: 78604
>
> URL: http://llvm.org/viewvc/llvm-project?rev=78604&view=rev
> Log:
> Use NEON for single-precision int<->FP conversions.
>
> Added:
> llvm/trunk/test/CodeGen/ARM/fsitos.ll
> llvm/trunk/test/CodeGen/ARM/ftosizs.ll
> llvm/trunk/test/CodeGen/ARM/ftouizs.ll
> llvm/trunk/test/CodeGen/ARM/fuitos.ll
> Modified:
> llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
> llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=78604&r1=78603&r2=78604&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Aug 10 17:17:39
> 2009
> @@ -1118,7 +1118,7 @@
> let Inst{7-4} = opcod3;
> }
>
> -// Single precision, unary if no NEON
> +// Single precision unary, if no NEON
> // Same as ASuI except not available if NEON is enabled
> class ASuIn<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag
> oops, dag iops,
> InstrItinClass itin, string opc, string asm,
> list<dag> pattern>
> @@ -1135,7 +1135,7 @@
> let Inst{11-8} = 0b1010;
> }
>
> -// Single precision, binary if no NEON
> +// Single precision binary, if no NEON
> // Same as ASbI except not available if NEON is enabled
> class ASbIn<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
> string opc, string asm, list<dag> pattern>
> @@ -1154,6 +1154,14 @@
> let Inst{6} = 1;
> }
>
> +// VFP conversion instructions, if no NEON
> +class AVConv1In<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3,
> + dag oops, dag iops, InstrItinClass itin,
> + string opc, string asm, list<dag> pattern>
> + : AVConv1I<opcod1, opcod2, opcod3, oops, iops, itin, opc, asm,
> pattern> {
> + list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
> +}
> +
> class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
> Format f,
> InstrItinClass itin,
> string opc, string asm, list<dag> pattern>
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=78604&r1=78603&r2=78604&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Aug 10 17:17:39 2009
> @@ -324,6 +324,20 @@
> (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst,
> $src"), "",
> [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
>
> +// Basic 2-register operations, scalar single-precision.
> +class N2VDs<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
> + bits<2> op17_16, bits<5> op11_7, bit op4, string
> OpcodeStr,
> + ValueType ResTy, ValueType OpTy, SDNode OpNode>
> + : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
> + (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
> + NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
> +
> +class N2VDsPat<SDNode OpNode, ValueType ResTy, ValueType OpTy,
> NeonI Inst>
> + : NEONFPPat<(ResTy (OpNode SPR:$a)),
> + (EXTRACT_SUBREG
> + (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)), SPR:$a,
> arm_ssubreg_0)),
> + arm_ssubreg_0)>;
> +
> // Basic 2-register intrinsics, both double- and quad-register.
> class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
> bits<2> op17_16, bits<5> op11_7, bit op4, string
> OpcodeStr,
> @@ -338,7 +352,7 @@
> (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst,
> $src"), "",
> [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
>
> -// Basic 2-register operations, scalar single-precision
> +// Basic 2-register intrinsics, scalar single-precision
> class N2VDInts<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
> bits<2> op17_16, bits<5> op11_7, bit op4, string
> OpcodeStr,
> ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
> @@ -1981,6 +1995,11 @@
> def VADDfd_sfp : N3VDs<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32,
> v2f32, fadd,1>;
> def : N3VDsPat<fadd, VADDfd_sfp>;
>
> +// Vector Sub Operations used for single-precision FP
> +let neverHasSideEffects = 1 in
> +def VSUBfd_sfp : N3VDs<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32,
> v2f32, fsub,0>;
> +def : N3VDsPat<fsub, VSUBfd_sfp>;
> +
> // Vector Multiply Operations used for single-precision FP
> let neverHasSideEffects = 1 in
> def VMULfd_sfp : N3VDs<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32,
> v2f32, fmul,1>;
> @@ -1989,31 +2008,46 @@
> // Vector Multiply-Accumulate/Subtract used for single-precision FP
> let neverHasSideEffects = 1 in
> def VMLAfd_sfp : N3VDMulOps<0, 0, 0b00, 0b1101, 1, "vmla.f32",
> v2f32,fmul,fadd>;
> -def : N3VDMulOpsPat<fmul, fadd, VMLAfd>;
> +def : N3VDMulOpsPat<fmul, fadd, VMLAfd_sfp>;
>
> let neverHasSideEffects = 1 in
> def VMLSfd_sfp : N3VDMulOps<0, 0, 0b10, 0b1101, 1, "vmls.f32",
> v2f32,fmul,fsub>;
> -def : N3VDMulOpsPat<fmul, fsub, VMLSfd>;
> -
> -// Vector Sub Operations used for single-precision FP
> -let neverHasSideEffects = 1 in
> -def VSUBfd_sfp : N3VDs<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32,
> v2f32, fsub,0>;
> -def : N3VDsPat<fsub, VSUBfd_sfp>;
> +def : N3VDMulOpsPat<fmul, fsub, VMLSfd_sfp>;
>
> -// Vector Absolute for single-precision FP
> +// Vector Absolute used for single-precision FP
> let neverHasSideEffects = 1 in
> def VABSfd_sfp : N2VDInts<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
> "vabs.f32",
> v2f32, v2f32, int_arm_neon_vabsf>;
> def : N2VDIntsPat<fabs, VABSfd_sfp>;
>
> -// Vector Negate for single-precision FP
> -
> +// Vector Negate used for single-precision FP
> let neverHasSideEffects = 1 in
> def VNEGf32d_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
> - (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
> NoItinerary,
> - "vneg.f32\t$dst, $src", "", []>;
> + (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
> NoItinerary,
> + "vneg.f32\t$dst, $src", "", []>;
> def : N2VDIntsPat<fneg, VNEGf32d_sfp>;
>
> +// Vector Convert between single-precision FP and integer
> +let neverHasSideEffects = 1 in
> +def VCVTf2sd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01110, 0,
> "vcvt.s32.f32",
> + v2i32, v2f32, fp_to_sint>;
> +def : N2VDsPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
> +
> +let neverHasSideEffects = 1 in
> +def VCVTf2ud_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01111, 0,
> "vcvt.u32.f32",
> + v2i32, v2f32, fp_to_uint>;
> +def : N2VDsPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
> +
> +let neverHasSideEffects = 1 in
> +def VCVTs2fd_sfp : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0,
> "vcvt.f32.s32",
> + v2f32, v2i32, sint_to_fp>;
> +def : N2VDsPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
> +
> +let neverHasSideEffects = 1 in
> +def VCVTu2fd_sfp : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0,
> "vcvt.f32.u32",
> + v2f32, v2i32, uint_to_fp>;
> +def : N2VDsPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
> +
> //
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
> // Non-Instruction Patterns
> //
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=78604&r1=78603&r2=78604&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Mon Aug 10 17:17:39 2009
> @@ -263,7 +263,7 @@
> let Inst{7} = 1;
> }
>
> -def FSITOS : AVConv1I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst),
> (ins SPR:$a),
> +def FSITOS : AVConv1In<0b11101011, 0b1000, 0b1010, (outs SPR:$dst),
> (ins SPR:$a),
> IIC_fpALU, "fsitos", " $dst, $a",
> [(set SPR:$dst, (arm_sitof SPR:$a))]> {
> let Inst{7} = 1;
> @@ -273,7 +273,7 @@
> IIC_fpALU, "fuitod", " $dst, $a",
> [(set DPR:$dst, (arm_uitof SPR:$a))]>;
>
> -def FUITOS : AVConv1I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst),
> (ins SPR:$a),
> +def FUITOS : AVConv1In<0b11101011, 0b1000, 0b1010, (outs SPR:$dst),
> (ins SPR:$a),
> IIC_fpALU, "fuitos", " $dst, $a",
> [(set SPR:$dst, (arm_uitof SPR:$a))]>;
>
> @@ -287,8 +287,8 @@
> let Inst{7} = 1; // Z bit
> }
>
> -def FTOSIZS : AVConv1I<0b11101011, 0b1101, 0b1010,
> - (outs SPR:$dst), (ins SPR:$a),
> +def FTOSIZS : AVConv1In<0b11101011, 0b1101, 0b1010,
> + (outs SPR:$dst), (ins SPR:$a),
> IIC_fpALU, "ftosizs", " $dst, $a",
> [(set SPR:$dst, (arm_ftosi SPR:$a))]> {
> let Inst{7} = 1; // Z bit
> @@ -301,8 +301,8 @@
> let Inst{7} = 1; // Z bit
> }
>
> -def FTOUIZS : AVConv1I<0b11101011, 0b1100, 0b1010,
> - (outs SPR:$dst), (ins SPR:$a),
> +def FTOUIZS : AVConv1In<0b11101011, 0b1100, 0b1010,
> + (outs SPR:$dst), (ins SPR:$a),
> IIC_fpALU, "ftouizs", " $dst, $a",
> [(set SPR:$dst, (arm_ftoui SPR:$a))]> {
> let Inst{7} = 1; // Z bit
>
> Added: llvm/trunk/test/CodeGen/ARM/fsitos.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fsitos.ll?rev=78604&view=auto
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/test/CodeGen/ARM/fsitos.ll (added)
> +++ llvm/trunk/test/CodeGen/ARM/fsitos.ll Mon Aug 10 17:17:39 2009
> @@ -0,0 +1,12 @@
> +; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | grep -E {fsitos\
> \W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
> +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,+neonfp | grep -E
> {vcvt.f32.s32\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
> +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,-neonfp | grep -E
> {fsitos\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
> +; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a8 | grep -E
> {vcvt.f32.s32\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
> +; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a9 | grep -E
> {fsitos\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
> +
> +define float @test(i32 %a, i32 %b) {
> +entry:
> + %0 = add i32 %a, %b
> + %1 = sitofp i32 %0 to float
> + ret float %1
> +}
>
> Added: llvm/trunk/test/CodeGen/ARM/ftosizs.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ftosizs.ll?rev=78604&view=auto
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/test/CodeGen/ARM/ftosizs.ll (added)
> +++ llvm/trunk/test/CodeGen/ARM/ftosizs.ll Mon Aug 10 17:17:39 2009
> @@ -0,0 +1,12 @@
> +; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | grep -E {ftosizs
> \\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
> +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,+neonfp | grep -E
> {vcvt.s32.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
> +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,-neonfp | grep -E
> {ftosizs\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
> +; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a8 | grep -E
> {vcvt.s32.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
> +; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a9 | grep -E
> {ftosizs\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
> +
> +define i32 @test(float %a, float %b) {
> +entry:
> + %0 = fadd float %a, %b
> + %1 = fptosi float %0 to i32
> + ret i32 %1
> +}
>
> Added: llvm/trunk/test/CodeGen/ARM/ftouizs.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ftouizs.ll?rev=78604&view=auto
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/test/CodeGen/ARM/ftouizs.ll (added)
> +++ llvm/trunk/test/CodeGen/ARM/ftouizs.ll Mon Aug 10 17:17:39 2009
> @@ -0,0 +1,12 @@
> +; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | grep -E {ftouizs
> \\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
> +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,+neonfp | grep -E
> {vcvt.u32.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
> +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,-neonfp | grep -E
> {ftouizs\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
> +; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a8 | grep -E
> {vcvt.u32.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
> +; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a9 | grep -E
> {ftouizs\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
> +
> +define i32 @test(float %a, float %b) {
> +entry:
> + %0 = fadd float %a, %b
> + %1 = fptoui float %0 to i32
> + ret i32 %1
> +}
>
> Added: llvm/trunk/test/CodeGen/ARM/fuitos.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fuitos.ll?rev=78604&view=auto
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/test/CodeGen/ARM/fuitos.ll (added)
> +++ llvm/trunk/test/CodeGen/ARM/fuitos.ll Mon Aug 10 17:17:39 2009
> @@ -0,0 +1,12 @@
> +; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2 | grep -E {fuitos\
> \W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
> +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,+neonfp | grep -E
> {vcvt.f32.u32\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
> +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon,-neonfp | grep -E
> {fuitos\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
> +; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a8 | grep -E
> {vcvt.f32.u32\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
> +; RUN: llvm-as < %s | llc -march=arm -mcpu=cortex-a9 | grep -E
> {fuitos\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
> +
> +define float @test(i32 %a, i32 %b) {
> +entry:
> + %0 = add i32 %a, %b
> + %1 = uitofp i32 %0 to float
> + ret float %1
> +}
>
>
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