[llvm-commits] [llvm] r78419 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp test/CodeGen/ARM/vdup.ll

[Evan Cheng]

Right. Please use def : pat to match to the same instructions whenever  
possible.

Evan

On Aug 7, 2009, at 3:50 PM, Bob Wilson wrote:

> I don't understand why you can't do this with the existing splat_lane
> pattern.  It would be good to match the (scalar_to_vector SPR)
> independently as a subreg access.  Once you've got that, it seems like
> it ought to be possible to legalize it to use the splat_lane shuffle.
> Am I missing something here?
>
> On Aug 7, 2009, at 3:36 PM, Anton Korobeynikov wrote:
>
>> Author: asl
>> Date: Fri Aug  7 17:36:50 2009
>> New Revision: 78419
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=78419&view=rev
>> Log:
>> 2 more vdup.32 cases
>>
>> Modified:
>>   llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>   llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
>>   llvm/trunk/test/CodeGen/ARM/vdup.ll
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=78419&r1=78418&r2=78419&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Aug  7 17:36:50  
>> 2009
>> @@ -1769,6 +1769,20 @@
>> def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>;
>> def VDUPLNfq  : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>;
>>
>> +def VDUPfdf   : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 0, 0,
>> +                    (outs DPR:$dst), (ins SPR:$src),
>> +                    "vdup.32\t$dst, ${src:lane}", "",
>> +                    [(set DPR:$dst, (v2f32 (splat_lo
>> +                                            (scalar_to_vector SPR:
>> $src),
>> +                                            undef)))]>;
>> +
>> +def VDUPfqf   : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 1, 0,
>> +                    (outs QPR:$dst), (ins SPR:$src),
>> +                    "vdup.32\t$dst, ${src:lane}", "",
>> +                    [(set QPR:$dst, (v4f32 (splat_lo
>> +                                            (scalar_to_vector SPR:
>> $src),
>> +                                            undef)))]>;
>> +
>> //   VMOVN    : Vector Narrowing Move
>> defm VMOVN    : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i",
>>                            int_arm_neon_vmovn>;
>>
>> Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=78419&r1=78418&r2=78419&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Fri Aug
>> 7 17:36:50 2009
>> @@ -345,6 +345,11 @@
>>        O << '{'
>>          << TRI->getAsmName(DRegLo) << ',' << TRI->getAsmName(DRegHi)
>>          << '}';
>> +      } else if (Modifier && strcmp(Modifier, "lane") == 0) {
>> +        unsigned RegNum = ARMRegisterInfo::getRegisterNumbering 
>> (Reg);
>> +        unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ?
>> 0 : 1,
>> +                                                 &ARM::DPRRegClass);
>> +        O << TRI->getAsmName(DReg) << '[' << (RegNum & 1) << ']';
>>      } else {
>>        O << TRI->getAsmName(Reg);
>>      }
>>
>> Modified: llvm/trunk/test/CodeGen/ARM/vdup.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vdup.ll?rev=78419&r1=78418&r2=78419&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/test/CodeGen/ARM/vdup.ll (original)
>> +++ llvm/trunk/test/CodeGen/ARM/vdup.ll Fri Aug  7 17:36:50 2009
>> @@ -1,7 +1,7 @@
>> ; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
>> ; RUN: grep vdup.8 %t | count 4
>> ; RUN: grep vdup.16 %t | count 4
>> -; RUN: grep vdup.32 %t | count 8
>> +; RUN: grep vdup.32 %t | count 10
>>
>> define <8 x i8> @v_dup8(i8 %A) nounwind {
>> 	%tmp1 = insertelement <8 x i8> zeroinitializer, i8 %A, i32 0
>> @@ -132,3 +132,17 @@
>> 	%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x
>> i32> zeroinitializer
>> 	ret <4 x float> %tmp2
>> }
>> +
>> +define <2 x float> @v_shuffledupfloat2(float* %A) nounwind {
>> +	%tmp0 = load float* %A
>> +        %tmp1 = insertelement <2 x float> undef, float %tmp0, i32 0
>> +        %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef,
>> <2 x i32> zeroinitializer
>> +        ret <2 x float> %tmp2
>> +}
>> +
>> +define <4 x float> @v_shuffledupQfloat2(float* %A) nounwind {
>> +        %tmp0 = load float* %A
>> +        %tmp1 = insertelement <4 x float> undef, float %tmp0, i32 0
>> +        %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef,
>> <4 x i32> zeroinitializer
>> +        ret <4 x float> %tmp2
>> +}
>>
>>
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