[llvm-commits] [llvm] r78237 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

[Anton Korobeynikov]

Author: asl
Date: Wed Aug  5 15:15:19 2009
New Revision: 78237

URL: http://llvm.org/viewvc/llvm-project?rev=78237&view=rev
Log:
Remove redundand checks: the only way to have, e.g. f32 RegVT is exactly
hardfloat case.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=78237&r1=78236&r2=78237&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Aug  5 15:15:19 2009
@@ -1461,21 +1461,17 @@
       } else {
         TargetRegisterClass *RC;
 
-        if (FloatABIType == FloatABI::Hard && RegVT == MVT::f32)
+        if (RegVT == MVT::f32)
           RC = ARM::SPRRegisterClass;
-        else if (FloatABIType == FloatABI::Hard && RegVT == MVT::f64)
+        else if (RegVT == MVT::f64)
           RC = ARM::DPRRegisterClass;
-        else if (FloatABIType == FloatABI::Hard && RegVT == MVT::v2f64)
+        else if (RegVT == MVT::v2f64)
           RC = ARM::QPRRegisterClass;
-        else if (AFI->isThumb1OnlyFunction())
-          RC = ARM::tGPRRegisterClass;
+        else if (RegVT == MVT::i32)
+          RC = (AFI->isThumb1OnlyFunction() ?
+                ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
         else
-          RC = ARM::GPRRegisterClass;
-
-        assert((RegVT == MVT::i32 || RegVT == MVT::f32 ||
-                (FloatABIType == FloatABI::Hard &&
-                 ((RegVT == MVT::f64) || (RegVT == MVT::v2f64)))) &&
-               "RegVT not supported by FORMAL_ARGUMENTS Lowering");
+          llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
 
         // Transform the arguments in physical registers into virtual ones.
         unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);