[llvm-commits] [llvm] r78086 - in /llvm/trunk: lib/Target/ARM/ARMRegisterInfo.td test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll
Evan Cheng
evan.cheng at apple.com
Tue Aug 4 11:46:22 PDT 2009
Author: evancheng
Date: Tue Aug 4 13:46:17 2009
New Revision: 78086
URL: http://llvm.org/viewvc/llvm-project?rev=78086&view=rev
Log:
In thumb mode, r7 is used as frame register. This fixes pr4681.
Added:
llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll
Modified:
llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=78086&r1=78085&r2=78086&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Tue Aug 4 13:46:17 2009
@@ -160,6 +160,13 @@
ARM::R4, ARM::R5, ARM::R6,
ARM::R8, ARM::R10,ARM::R11,
ARM::R7 };
+ // FP is R7, R9 is available as callee-saved register.
+ // This is used by non-Darwin platform in Thumb mode.
+ static const unsigned ARM_GPR_AO_5[] = {
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+ ARM::R12,ARM::LR,
+ ARM::R4, ARM::R5, ARM::R6,
+ ARM::R8, ARM::R9, ARM::R10,ARM::R11,ARM::R7 };
GPRClass::iterator
GPRClass::allocation_order_begin(const MachineFunction &MF) const {
@@ -173,6 +180,8 @@
} else {
if (Subtarget.isR9Reserved())
return ARM_GPR_AO_2;
+ else if (Subtarget.isThumb())
+ return ARM_GPR_AO_5;
else
return ARM_GPR_AO_1;
}
@@ -193,6 +202,8 @@
} else {
if (Subtarget.isR9Reserved())
I = ARM_GPR_AO_2 + (sizeof(ARM_GPR_AO_2)/sizeof(unsigned));
+ else if (Subtarget.isThumb())
+ I = ARM_GPR_AO_5 + (sizeof(ARM_GPR_AO_5)/sizeof(unsigned));
else
I = ARM_GPR_AO_1 + (sizeof(ARM_GPR_AO_1)/sizeof(unsigned));
}
Added: llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll?rev=78086&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll (added)
+++ llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll Tue Aug 4 13:46:17 2009
@@ -0,0 +1,29 @@
+; RUN: llvm-as < %s | llc -mtriple=thumbv7-none-linux-gnueabi
+; PR4681
+
+ %struct.FILE = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %struct._IO_marker*, %struct.FILE*, i32, i32, i32, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i8*, i8*, i32, i32, [40 x i8] }
+ %struct._IO_marker = type { %struct._IO_marker*, %struct.FILE*, i32 }
+ at .str2 = external constant [30 x i8], align 1 ; <[30 x i8]*> [#uses=1]
+
+define arm_aapcscc i32 @__mf_heuristic_check(i32 %ptr, i32 %ptr_high) nounwind {
+entry:
+ br i1 undef, label %bb1, label %bb
+
+bb: ; preds = %entry
+ unreachable
+
+bb1: ; preds = %entry
+ br i1 undef, label %bb9, label %bb2
+
+bb2: ; preds = %bb1
+ %0 = call i8* @llvm.frameaddress(i32 0) ; <i8*> [#uses=1]
+ %1 = call arm_aapcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* noalias undef, i8* noalias getelementptr ([30 x i8]* @.str2, i32 0, i32 0), i8* %0, i8* null) nounwind ; <i32> [#uses=0]
+ unreachable
+
+bb9: ; preds = %bb1
+ ret i32 undef
+}
+
+declare i8* @llvm.frameaddress(i32) nounwind readnone
+
+declare arm_aapcscc i32 @fprintf(%struct.FILE* noalias nocapture, i8* noalias nocapture, ...) nounwind
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