[llvm-commits] [llvm] r77740 - in /llvm/trunk: include/llvm/CodeGen/AsmPrinter.h lib/CodeGen/AsmPrinter/AsmPrinter.cpp test/CodeGen/X86/2009-04-17-tls-fast.ll test/CodeGen/X86/tls1-pic.ll test/CodeGen/X86/tls2-pic.ll test/CodeGen/X86/tls3-pic.ll test/CodeGen/X86/tls4-pic.ll utils/TableGen/AsmWriterEmitter.cpp

[Jakob Stoklund Olesen]

On 01/08/2009, at 07.43, Chris Lattner wrote:
> Wow, this is awesome!
>
> I'm not seeing this kick in.  On X86, I'm seeing stuff like:
>
> _get_results:
> LBB2_0: ## entry
>         pushl   %ebx
>         pushl   %edi
>         pushl   %esi
>         subl    $48, %esp
>         testl   %edx, %edx
>         movl    %ecx, %esi
>         je      LBB2_4  ## bb
>
>
> Shouldn't the esp/edx/esi be lined up?  What am I missing here?

As I am reading David's patch, there must be a tab in the instruction  
definition before a tab is emitted. From X86InstrInfo.td:

def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
                 "mov{l}\t{$src, $dst|$dst, $src}", []>;

There is only one tab. It should be changed to:

def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
                 "mov{l}\t{$src,\t$dst|$dst,\t$src}", []>;

Let me just point out that not all assembler syntax fits the mnemonic 
+operands syntax. These are some random blackfin assembler instructions:

p3 = (p3+p2)<<2 ;
r3.h = ashift r0.l by r7.l ;
prefetch [ p0 ++ ] ;
(r1, r0) = search r2 (LT) || r2 = [p0++];
a1=r7.h*r4.h (m), a0+=r7.l*r4.l (fu) ;
r1=pack(r1.h,r0.h) || [i0++]=r0 || r2.l=w[i2++] ;

Yes, that is one instruction per line. As you can see, it would be bad  
to insert any tabs in that syntax. It is important that targets can  
"opt out" of any imposed formatting.