[llvm-commits] [PATCH] Analog Devices Blackfin back-end

[Evan Cheng]

Hi Jakob,

Sorry I haven't found the time to look at the patch. Things have been  
crazy.

I'll try to get to it soon. If not, please ping me again in a few  
days. :-)

Evan

On Jul 23, 2009, at 11:48 PM, Jakob Stoklund Olesen wrote:

> Hi,
>
> Finally my blackfin back-end is ready to be included in the main  
> tree. It is still experimental. I have compiled most of CodeGen/ 
> Generic as well as my own test cases. The blackfin assembler (bfin- 
> elf-as) is happy with the output, but I have not yet tested it on  
> real hardware. I have access to blackfin hardware, so I can do that  
> later. There is a GNU tool-chain at http://blackfin.uclinux.org/
>
> I have some XFAIL test cases. They are:
>
> - RegisterScavenger asserts caused by the heavy use if sub-registers.
> - Readcyclecounter failing because it wants to return an illegal i64.
> - Illegal i16 logic operations introduced after LegalizeOps.
>
> These issues will be easier to fix after the back-end goes in. Then  
> I can make test cases at the same time.
>
> The Blackfin DSP has some features that have stressed the code  
> generator quite a bit:
>
> - It has more register classes that any other target. Fortunately  
> register class support has improved a lot since 2.5.
> - Some register class constraints are not yet supported. For  
> instance there are two ADD variants: D=D+D and P=P+P.
> - The legal types are i16 and i32, but i16 is quite limited in the  
> number of supported operations. This has caused a lot of fun with  
> the DAG combiner.
> - Sub-register operations are used a lot more than on X86.
>
> Some things are simply not implemented yet, like hardware loops and  
> circular buffer addressing.
>
> I hope you will consider this for inclusion in the tree.
>
> Best regards,
> /jakob
>
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