[llvm-commits] [llvm] r77227 - in /llvm/trunk/lib/Target/ARM: ARMBaseInstrInfo.h ARMBaseRegisterInfo.cpp ARMInstrInfo.cpp Thumb1InstrInfo.cpp Thumb2InstrInfo.cpp

[Evan Cheng]

Author: evancheng
Date: Mon Jul 27 13:38:54 2009
New Revision: 77227

URL: http://llvm.org/viewvc/llvm-project?rev=77227&view=rev
Log:
Get rid of more dead code.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
    llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
    llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=77227&r1=77226&r2=77227&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Mon Jul 27 13:38:54 2009
@@ -165,9 +165,7 @@
     ADDri,
     ADDrs,
     ADDrr,
-    LDRri,
     MOVr,
-    STRri,
     SUBri,
     SUBrs,
     SUBrr

Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=77227&r1=77226&r2=77227&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Mon Jul 27 13:38:54 2009
@@ -1368,7 +1368,7 @@
 
 void ARMBaseRegisterInfo::
 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
-  assert(!STI.isThumb1Only &&
+  assert(!STI.isThumb1Only() &&
          "This emitEpilogue should not be executed for Thumb1!");
 
   MachineBasicBlock::iterator MBBI = prior(MBB.end());

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=77227&r1=77226&r2=77227&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Mon Jul 27 13:38:54 2009
@@ -68,9 +68,7 @@
   case ARMII::ADDri: return ARM::ADDri;
   case ARMII::ADDrs: return ARM::ADDrs;
   case ARMII::ADDrr: return ARM::ADDrr;
-  case ARMII::LDRri: return 0;
   case ARMII::MOVr: return ARM::MOVr;
-  case ARMII::STRri: return 0;
   case ARMII::SUBri: return ARM::SUBri;
   case ARMII::SUBrs: return ARM::SUBrs;
   case ARMII::SUBrr: return ARM::SUBrr;

Modified: llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp?rev=77227&r1=77226&r2=77227&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp Mon Jul 27 13:38:54 2009
@@ -35,9 +35,7 @@
   case ARMII::ADDri: return ARM::tADDi8;
   case ARMII::ADDrs: return 0;
   case ARMII::ADDrr: return ARM::tADDrr;
-  case ARMII::LDRri: return 0;
   case ARMII::MOVr: return ARM::tMOVr;
-  case ARMII::STRri: return 0;
   case ARMII::SUBri: return ARM::tSUBi8;
   case ARMII::SUBrs: return 0;
   case ARMII::SUBrr: return ARM::tSUBrr;

Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=77227&r1=77226&r2=77227&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Mon Jul 27 13:38:54 2009
@@ -36,9 +36,7 @@
   case ARMII::ADDri: return ARM::t2ADDri;
   case ARMII::ADDrs: return ARM::t2ADDrs;
   case ARMII::ADDrr: return ARM::t2ADDrr;
-  case ARMII::LDRri: return ARM::t2LDRi12;
   case ARMII::MOVr: return ARM::t2MOVr;
-  case ARMII::STRri: return ARM::t2STRi12;
   case ARMII::SUBri: return ARM::t2SUBri;
   case ARMII::SUBrs: return ARM::t2SUBrs;
   case ARMII::SUBrr: return ARM::t2SUBrr;