[llvm-commits] [llvm] r77164 - in /llvm/trunk/lib/Target/ARM: ARMBaseRegisterInfo.cpp ARMBaseRegisterInfo.h Thumb1RegisterInfo.cpp Thumb1RegisterInfo.h Thumb2RegisterInfo.cpp Thumb2RegisterInfo.h
Evan Cheng
evan.cheng at apple.com
Sun Jul 26 11:55:24 PDT 2009
Author: evancheng
Date: Sun Jul 26 13:55:14 2009
New Revision: 77164
URL: http://llvm.org/viewvc/llvm-project?rev=77164&view=rev
Log:
Refactor. Get rid of a few more getOpcode() calls.
Modified:
llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.h
llvm/trunk/lib/Target/ARM/Thumb2RegisterInfo.cpp
llvm/trunk/lib/Target/ARM/Thumb2RegisterInfo.h
Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=77164&r1=77163&r2=77164&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Sun Jul 26 13:55:14 2009
@@ -1028,6 +1028,7 @@
int ARMBaseRegisterInfo::
rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
+ unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc,
unsigned FrameReg, int Offset) const
{
unsigned Opcode = MI.getOpcode();
@@ -1039,18 +1040,18 @@
if (Opcode == ARM::INLINEASM)
AddrMode = ARMII::AddrMode2;
- if (Opcode == getOpcode(ARMII::ADDri)) {
+ if (Opcode == ADDriOpc) {
Offset += MI.getOperand(FrameRegIdx+1).getImm();
if (Offset == 0) {
// Turn it into a move.
- MI.setDesc(TII.get(getOpcode(ARMII::MOVr)));
+ MI.setDesc(TII.get(MOVOpc));
MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
MI.RemoveOperand(FrameRegIdx+1);
return 0;
} else if (Offset < 0) {
Offset = -Offset;
isSub = true;
- MI.setDesc(TII.get(getOpcode(ARMII::SUBri)));
+ MI.setDesc(TII.get(SUBriOpc));
}
// Common case: small offset, fits into instruction.
@@ -1144,7 +1145,8 @@
}
void ARMBaseRegisterInfo::
-eliminateFrameIndex(MachineBasicBlock::iterator II,
+eliminateFrameIndexImpl(MachineBasicBlock::iterator II,
+ unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc,
int SPAdj, RegScavenger *RS) const {
unsigned i = 0;
MachineInstr &MI = *II;
@@ -1178,7 +1180,7 @@
}
// modify MI as necessary to handle as much of 'Offset' as possible
- Offset = rewriteFrameIndex(MI, i, FrameReg, Offset);
+ Offset = rewriteFrameIndex(MI, i, MOVOpc,ADDriOpc,SUBriOpc, FrameReg, Offset);
if (Offset == 0)
return;
Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=77164&r1=77163&r2=77164&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Sun Jul 26 13:55:14 2009
@@ -128,14 +128,26 @@
// rewrite MI to access 'Offset' bytes from the FP. Return the offset that
// could not be handled directly in MI.
- virtual int rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
- unsigned FrameReg, int Offset) const;
- virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
- int SPAdj, RegScavenger *RS = NULL) const;
+ virtual int
+ rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
+ unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc,
+ unsigned FrameReg, int Offset) const;
+
+ virtual void
+ eliminateFrameIndex(MachineBasicBlock::iterator II,
+ int SPAdj, RegScavenger *RS = NULL) const {
+ eliminateFrameIndexImpl(II, ARM::MOVr, ARM::ADDri, ARM::SUBri, SPAdj, RS);
+ }
virtual void emitPrologue(MachineFunction &MF) const;
virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
+protected:
+ void
+ eliminateFrameIndexImpl(MachineBasicBlock::iterator II,
+ unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc,
+ int SPAdj, RegScavenger *RS = NULL) const;
+
private:
unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;
Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=77164&r1=77163&r2=77164&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Sun Jul 26 13:55:14 2009
@@ -388,6 +388,7 @@
int Thumb1RegisterInfo::
rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
+ unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc,
unsigned FrameReg, int Offset) const
{
// if/when eliminateFrameIndex() conforms with ARMBaseRegisterInfo
Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.h?rev=77164&r1=77163&r2=77164&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.h Sun Jul 26 13:55:14 2009
@@ -51,7 +51,9 @@
// rewrite MI to access 'Offset' bytes from the FP. Return the offset that
// could not be handled directly in MI.
int rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
+ unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc,
unsigned FrameReg, int Offset) const;
+
void eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, RegScavenger *RS = NULL) const;
Modified: llvm/trunk/lib/Target/ARM/Thumb2RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2RegisterInfo.cpp?rev=77164&r1=77163&r2=77164&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2RegisterInfo.cpp Sun Jul 26 13:55:14 2009
@@ -165,6 +165,7 @@
int Thumb2RegisterInfo::
rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
+ unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc,
unsigned FrameReg, int Offset) const
{
unsigned Opcode = MI.getOpcode();
@@ -176,18 +177,18 @@
if (Opcode == ARM::INLINEASM)
AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
- if (Opcode == getOpcode(ARMII::ADDri)) {
+ if (Opcode == ADDriOpc) {
Offset += MI.getOperand(FrameRegIdx+1).getImm();
if (Offset == 0) {
// Turn it into a move.
- MI.setDesc(TII.get(ARM::t2MOVr));
+ MI.setDesc(TII.get(MOVOpc));
MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
MI.RemoveOperand(FrameRegIdx+1);
return 0;
} else if (Offset < 0) {
Offset = -Offset;
isSub = true;
- MI.setDesc(TII.get(getOpcode(ARMII::SUBri)));
+ MI.setDesc(TII.get(SUBriOpc));
}
// Common case: small offset, fits into instruction.
@@ -231,7 +232,7 @@
if ((AddrMode != ARMII::AddrModeT2_i8) &&
(AddrMode != ARMII::AddrModeT2_i12)) {
return ARMBaseRegisterInfo::rewriteFrameIndex(MI, FrameRegIdx,
- FrameReg, Offset);
+ ARM::t2MOVr, ARM::t2ADDri, ARM::t2SUBri, FrameReg, Offset);
}
unsigned NumBits = 0;
Modified: llvm/trunk/lib/Target/ARM/Thumb2RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2RegisterInfo.h?rev=77164&r1=77163&r2=77164&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2RegisterInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2RegisterInfo.h Sun Jul 26 13:55:14 2009
@@ -27,11 +27,6 @@
public:
Thumb2RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
- // rewrite MI to access 'Offset' bytes from the FP. Return the offset that
- // could not be handled directly in MI.
- int rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
- unsigned FrameReg, int Offset) const;
-
/// emitLoadConstPool - Emits a load from constpool to materialize the
/// specified immediate.
void emitLoadConstPool(MachineBasicBlock &MBB,
@@ -42,6 +37,19 @@
unsigned PredReg = 0) const;
bool requiresRegisterScavenging(const MachineFunction &MF) const;
+
+ // rewrite MI to access 'Offset' bytes from the FP. Return the offset that
+ // could not be handled directly in MI.
+ virtual int
+ rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
+ unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc,
+ unsigned FrameReg, int Offset) const;
+
+ void eliminateFrameIndex(MachineBasicBlock::iterator II,
+ int SPAdj, RegScavenger *RS = NULL) const {
+ ARMBaseRegisterInfo::eliminateFrameIndexImpl(II, ARM::t2MOVr, ARM::t2ADDri,
+ ARM::t2SUBri, SPAdj, RS);
+ }
};
}
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