[llvm-commits] [llvm] r76986 - in /llvm/trunk/lib/Target/ARM: ARMBaseInstrInfo.cpp ARMConstantIslandPass.cpp ARMInstrThumb2.td
Evan Cheng
evan.cheng at apple.com
Fri Jul 24 11:20:44 PDT 2009
Author: evancheng
Date: Fri Jul 24 13:20:44 2009
New Revision: 76986
URL: http://llvm.org/viewvc/llvm-project?rev=76986&view=rev
Log:
Make sure thumb2 jumptable entries are aligned.
Modified:
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=76986&r1=76985&r2=76986&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Fri Jul 24 13:20:44 2009
@@ -433,23 +433,27 @@
}
break;
}
- case ARMII::Size8Bytes: return 8; // Arm instruction x 2.
- case ARMII::Size4Bytes: return 4; // Arm instruction.
- case ARMII::Size2Bytes: return 2; // Thumb instruction.
+ case ARMII::Size8Bytes: return 8; // ARM instruction x 2.
+ case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction.
+ case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
case ARMII::SizeSpecial: {
+ bool IsThumb1JT = false;
switch (MI->getOpcode()) {
case ARM::CONSTPOOL_ENTRY:
// If this machine instr is a constant pool entry, its size is recorded as
// operand #2.
return MI->getOperand(2).getImm();
- case ARM::Int_eh_sjlj_setjmp: return 12;
+ case ARM::Int_eh_sjlj_setjmp:
+ return 12;
+ case ARM::tBR_JTr:
+ IsThumb1JT = true;
+ // Fallthrough
case ARM::BR_JTr:
case ARM::BR_JTm:
case ARM::BR_JTadd:
case ARM::t2BR_JTr:
case ARM::t2BR_JTm:
- case ARM::t2BR_JTadd:
- case ARM::tBR_JTr: {
+ case ARM::t2BR_JTadd: {
// These are jumptable branches, i.e. a branch followed by an inlined
// jumptable. The size is 4 + 4 * number of entries.
unsigned NumOps = TID.getNumOperands();
@@ -466,8 +470,7 @@
// FIXME: If we know the size of the function is less than (1 << 16) *2
// bytes, we can use 16-bit entries instead. Then there won't be an
// alignment issue.
- return getNumJTEntries(JT, JTI) * 4 +
- ((MI->getOpcode()==ARM::tBR_JTr) ? 2 : 4);
+ return getNumJTEntries(JT, JTI) * 4 + (IsThumb1JT ? 2 : 4);
}
default:
// Otherwise, pseudo-instruction sizes are zero.
Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=76986&r1=76985&r2=76986&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Fri Jul 24 13:20:44 2009
@@ -788,10 +788,11 @@
}
// Thumb1 jump tables require padding. They should be at the end;
// following unconditional branches are removed by AnalyzeBranch.
- MachineInstr *ThumbJTMI = NULL;
- if (prior(MBB->end())->getOpcode() == ARM::tBR_JTr)
- ThumbJTMI = prior(MBB->end());
- if (ThumbJTMI) {
+ MachineInstr *ThumbJTMI = prior(MBB->end());
+ if (ThumbJTMI->getOpcode() == ARM::tBR_JTr ||
+ ThumbJTMI->getOpcode() == ARM::t2BR_JTr ||
+ ThumbJTMI->getOpcode() == ARM::t2BR_JTm ||
+ ThumbJTMI->getOpcode() == ARM::t2BR_JTadd) {
unsigned newMIOffset = GetOffsetOf(ThumbJTMI);
unsigned oldMIOffset = newMIOffset - delta;
if (oldMIOffset%4 == 0 && newMIOffset%4 != 0) {
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=76986&r1=76985&r2=76986&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Jul 24 13:20:44 2009
@@ -1082,20 +1082,20 @@
let isNotDuplicable = 1, isIndirectBranch = 1 in {
def t2BR_JTr : T2JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
- "mov pc, $target \n$jt",
+ "mov pc, $target \n\t.align\t2\n$jt",
[(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
def t2BR_JTm :
T2JTI<(outs),
(ins t2addrmode_so_reg:$target, jtblock_operand:$jt, i32imm:$id),
- "ldr pc, $target \n$jt",
+ "ldr pc, $target \n\t.align\t2\n$jt",
[(ARMbrjt (i32 (load t2addrmode_so_reg:$target)), tjumptable:$jt,
imm:$id)]>;
def t2BR_JTadd :
T2JTI<(outs),
(ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
- "add pc, $target, $idx \n$jt",
+ "add pc, $target, $idx \n\t.align\t2\n$jt",
[(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, imm:$id)]>;
} // isNotDuplicate, isIndirectBranch
} // isBranch, isTerminator, isBarrier
More information about the llvm-commits
mailing list