[llvm-commits] [llvm] r76883 - in /llvm/trunk/lib/Target/ARM: ARMBaseInstrInfo.h ARMBaseRegisterInfo.cpp ARMBaseRegisterInfo.h ARMInstrInfo.cpp ARMInstrInfo.h ARMInstrThumb2.td Thumb1InstrInfo.cpp Thumb1InstrInfo.h Thumb2InstrInfo.cpp Thumb2InstrInfo.h

[David Goodwin]

Arg! What a horrible architecture! So, the base + imm8 form is  
interpreted as a LDRT which is probably OK for user code but would  
cause problems in kernel code.
Having two different opcodes for the two base + imm (8/12) forms makes  
it awkward to adjust the immediate... but I will fix it.

David

On Jul 23, 2009, at 11:35 AM, Evan Cheng wrote:

>
> On Jul 23, 2009, at 10:06 AM, David Goodwin wrote:
>
>>
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Thu Jul 23 12:06:46
>> 2009
>> @@ -109,7 +109,7 @@
>>  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
>> }
>>
>> -// t2addrmode_imm8  := reg - imm8
>> +// t2addrmode_imm8  := reg +/- imm8
>> def t2addrmode_imm8 : Operand<i32>,
>>                      ComplexPattern<i32, 2, "SelectT2AddrModeImm8",
>> []> {
>>  let PrintMethod = "printT2AddrModeImm8Operand";
>
> Hi David,
>
> This looks wrong (SelectT2AddrModeImm8 looks wrong too). According to
> the manual:
>
> LDR (immediate, Thumb) encoding T4 is
> LDR<c> <Rt>, [<Rn>,#-<imm8>]
> LDR<c> <Rt>, [<Rn>,#+/-<imm8>]
> LDR<c> <Rd>, [<Rn>,#+/-<imm8>]!
>
> That is, it only allows + offset when it's a pre- / post- index LDR
> (ditto for STR). This means sense since T3 allows for positive 12-bit
> immediate offset.
>
> Evan
>
>>
>> Modified: llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp?rev=76883&r1=76882&r2=76883&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp Thu Jul 23
>> 12:06:46 2009
>> @@ -30,6 +30,12 @@
>>  return 0;
>> }
>>
>> +unsigned
>> +Thumb1InstrInfo::unsignedOffsetOpcodeToSigned(unsigned opcode,
>> +                                              unsigned *NumBits)
>> const {
>> +  return 0;
>> +}
>> +
>> unsigned Thumb1InstrInfo::getOpcode(ARMII::Op Op) const {
>>  switch (Op) {
>>  case ARMII::ADDri: return ARM::tADDi8;
>>
>> Modified: llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.h?rev=76883&r1=76882&r2=76883&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.h (original)
>> +++ llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.h Thu Jul 23 12:06:46
>> 2009
>> @@ -34,6 +34,13 @@
>>  // Return the opcode that implements 'Op', or 0 if no opcode
>>  unsigned getOpcode(ARMII::Op Op) const;
>>
>> +  // If 'opcode' is an instruction with an unsigned offset that also
>> +  // has a version with a signed offset, return the opcode for the
>> +  // version with the signed offset. In 'NumBits' return the number
>> of
>> +  // bits for the signed offset.
>> +  unsigned unsignedOffsetOpcodeToSigned(unsigned opcode,
>> +                                        unsigned *NumBits) const;
>> +
>>  // Return true if the block does not fall through.
>>  bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
>>
>>
>> Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=76883&r1=76882&r2=76883&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Thu Jul 23
>> 12:06:46 2009
>> @@ -88,6 +88,29 @@
>>  return false;
>> }
>>
>> +unsigned
>> +Thumb2InstrInfo::unsignedOffsetOpcodeToSigned(unsigned opcode,
>> +                                              unsigned *NumBits)
>> const
>> +{
>> +  if (NumBits != NULL)
>> +    *NumBits = 8;
>> +
>> +  switch (opcode) {
>> +  case ARM::t2LDRi12:   return ARM::t2LDRi8;
>> +  case ARM::t2LDRHi12:  return ARM::t2LDRHi8;
>> +  case ARM::t2LDRBi12:  return ARM::t2LDRBi8;
>> +  case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
>> +  case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
>> +  case ARM::t2STRi12:   return ARM::t2STRi8;
>> +  case ARM::t2STRBi12:  return ARM::t2STRBi8;
>> +  case ARM::t2STRHi12:  return ARM::t2STRHi8;
>> +  default:
>> +    break;
>> +  }
>> +
>> +  return 0;
>> +}
>> +
>> bool
>> Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
>>                              MachineBasicBlock::iterator I,
>>
>> Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.h?rev=76883&r1=76882&r2=76883&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.h (original)
>> +++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.h Thu Jul 23 12:06:46
>> 2009
>> @@ -34,6 +34,13 @@
>>  // Return the opcode that implements 'Op', or 0 if no opcode
>>  unsigned getOpcode(ARMII::Op Op) const;
>>
>> +  // If 'opcode' is an instruction with an unsigned offset that also
>> +  // has a version with a signed offset, return the opcode for the
>> +  // version with the signed offset. In 'NumBits' return the number
>> of
>> +  // bits for the signed offset.
>> +  unsigned unsignedOffsetOpcodeToSigned(unsigned opcode,
>> +                                        unsigned *NumBits) const;
>> +
>>  // Return true if the block does not fall through.
>>  bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
>>
>>
>>
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