[llvm-commits] [llvm-gcc-4.2] r76781 [5/5] - in /llvm-gcc-4.2/trunk: ./ gcc/ gcc/config/ gcc/config/arm/ gcc/config/rs6000/ gcc/cp/ gcc/doc/ gcc/testsuite/g++.apple/ gcc/testsuite/g++.dg/abi/ gcc/testsuite/gcc.apple/ gcc/testsuite/gcc.target/arm/ gcc/testsuite/gcc.target/arm/neon/ gcc/testsuite/obj-c++.dg/ gcc/testsuite/objc.dg/

Wed Jul 22 13:36:46 PDT 2009

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c?rev=76781&view=auto

==============================================================================

--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets8_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_s64 (void)
+{
+  int8x8_t out_int8x8_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int8x8_t = vreinterpret_s8_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets8_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_u16 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_int8x8_t = vreinterpret_s8_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets8_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_u32 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_int8x8_t = vreinterpret_s8_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets8_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_u64 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_int8x8_t = vreinterpret_s8_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets8_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_u8 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_int8x8_t = vreinterpret_s8_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_f32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint16x4_t = vreinterpret_u16_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu16_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_p16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_uint16x4_t = vreinterpret_u16_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu16_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_p8 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_uint16x4_t = vreinterpret_u16_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu16_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_s16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_uint16x4_t = vreinterpret_u16_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu16_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_s32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_uint16x4_t = vreinterpret_u16_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu16_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_s64 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_uint16x4_t = vreinterpret_u16_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu16_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_s8 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_uint16x4_t = vreinterpret_u16_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu16_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_u32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint16x4_t = vreinterpret_u16_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu16_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_u64 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint16x4_t = vreinterpret_u16_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu16_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_u8 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint16x4_t = vreinterpret_u16_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_f32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint32x2_t = vreinterpret_u32_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu32_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_p16 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_uint32x2_t = vreinterpret_u32_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu32_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_p8 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_uint32x2_t = vreinterpret_u32_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu32_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_s16 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_uint32x2_t = vreinterpret_u32_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_s32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_uint32x2_t = vreinterpret_u32_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu32_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_s64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_uint32x2_t = vreinterpret_u32_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu32_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_s8 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_uint32x2_t = vreinterpret_u32_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu32_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_u16 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint32x2_t = vreinterpret_u32_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu32_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_u64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint32x2_t = vreinterpret_u32_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu32_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_u8 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint32x2_t = vreinterpret_u32_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu64_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_f32 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint64x1_t = vreinterpret_u64_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu64_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_p16 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_uint64x1_t = vreinterpret_u64_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu64_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_p8 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_uint64x1_t = vreinterpret_u64_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu64_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_s16 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_uint64x1_t = vreinterpret_u64_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu64_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_s32 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_uint64x1_t = vreinterpret_u64_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu64_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_s64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_uint64x1_t = vreinterpret_u64_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu64_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_s8 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_uint64x1_t = vreinterpret_u64_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu64_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_u16 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint64x1_t = vreinterpret_u64_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu64_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_u32 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint64x1_t = vreinterpret_u64_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu64_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_u8 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint64x1_t = vreinterpret_u64_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu8_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_f32 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint8x8_t = vreinterpret_u8_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu8_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_p16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_uint8x8_t = vreinterpret_u8_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu8_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_p8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_uint8x8_t = vreinterpret_u8_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu8_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_s16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_uint8x8_t = vreinterpret_u8_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu8_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_s32 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_uint8x8_t = vreinterpret_u8_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu8_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_s64 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_uint8x8_t = vreinterpret_u8_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu8_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_s8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_uint8x8_t = vreinterpret_u8_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu8_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_u16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint8x8_t = vreinterpret_u8_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu8_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_u32 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint8x8_t = vreinterpret_u8_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretu8_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_u64 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint8x8_t = vreinterpret_u8_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev16Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev16Qp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x16_t = vrev16q_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev16Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev16Qs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vrev16q_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev16Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev16Qu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vrev16q_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev16p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev16p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vrev16_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev16s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev16s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vrev16_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev16u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev16u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vrev16_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev32Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qp16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly16x8_t = vrev32q_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev32Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x16_t = vrev32q_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev32Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vrev32q_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev32Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vrev32q_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev32Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vrev32q_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev32Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vrev32q_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev32p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32p16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly16x4_t = vrev32_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev32p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vrev32_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev32s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32s16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vrev32_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev32s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vrev32_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev32u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32u16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vrev32_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev32u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vrev32_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev64Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vrev64q_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev64Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qp16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly16x8_t = vrev64q_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev64Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x16_t = vrev64q_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev64Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vrev64q_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev64Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vrev64q_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev64Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vrev64q_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev64Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vrev64q_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev64Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vrev64q_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev64Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vrev64q_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev64f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64f32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vrev64_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev64p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64p16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly16x4_t = vrev64_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev64p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vrev64_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev64s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64s16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vrev64_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev64s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64s32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vrev64_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev64s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vrev64_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev64u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64u16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vrev64_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev64u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64u32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vrev64_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrev64u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vrev64_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrsqrteQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrsqrteQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vrsqrteq_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrte\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrsqrteQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrsqrteQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vrsqrteq_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrte\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrsqrtef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrsqrtef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vrsqrte_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrte\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrsqrteu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrsqrteu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vrsqrte_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrte\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrsqrtsQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrsqrtsQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vrsqrtsq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrts\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrsqrtsf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrsqrtsf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vrsqrts_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrts\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsetQ_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32_t arg0_float32_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vsetq_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsetQ_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanep16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16_t arg0_poly16_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8_t = vsetq_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsetQ_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanep8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8_t arg0_poly8_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vsetq_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsetQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16_t arg0_int16_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vsetq_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsetQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32_t arg0_int32_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vsetq_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsetQ_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanes64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64_t arg0_int64_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vsetq_lane_s64 (arg0_int64_t, arg1_int64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsetQ_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanes8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8_t arg0_int8_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vsetq_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsetQ_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_laneu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16_t arg0_uint16_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vsetq_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsetQ_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_laneu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32_t arg0_uint32_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vsetq_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsetQ_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_laneu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64_t arg0_uint64_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vsetq_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsetQ_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_laneu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8_t arg0_uint8_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vsetq_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vset_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_lanef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32_t arg0_float32_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vset_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vset_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_lanep16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16_t arg0_poly16_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4_t = vset_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vset_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_lanep8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8_t arg0_poly8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vset_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vset_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16_t arg0_int16_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vset_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vset_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32_t arg0_int32_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vset_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vset_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_lanes64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64_t arg0_int64_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vset_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vset_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_lanes8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8_t arg0_int8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vset_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vset_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_laneu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16_t arg0_uint16_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vset_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vset_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_laneu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32_t arg0_uint32_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vset_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vset_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_laneu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64_t arg0_uint64_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vset_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vset_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_laneu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8_t arg0_uint8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vset_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshlQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vshlq_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshlQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vshlq_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshlQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x2_t = vshlq_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshlQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vshlq_n_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshlQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vshlq_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshlQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vshlq_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshlQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x2_t = vshlq_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshlQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vshlq_n_u8 (arg0_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshlQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshlQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshlQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshlQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshlQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshlQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshlQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_uint64x2_t = vshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshlQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshl_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshl_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vshl_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshl_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshl_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vshl_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshl_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshl_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x1_t = vshl_n_s64 (arg0_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshl_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshl_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vshl_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshl_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshl_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vshl_n_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshl_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshl_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vshl_n_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshl_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshl_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x1_t = vshl_n_u64 (arg0_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshl_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshl_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vshl_n_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshll_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshll_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int32x4_t = vshll_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshll_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshll_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int64x2_t = vshll_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshll_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshll_ns8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int16x8_t = vshll_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshll_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshll_nu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint32x4_t = vshll_n_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshll_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshll_nu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint64x2_t = vshll_n_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshll_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshll_nu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint16x8_t = vshll_n_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshls16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshls16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshls16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshls16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshls16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshls32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshls32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshls32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshls32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshls32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshls64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshls64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshls64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshls64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshls64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshls64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshls8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshls8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshls8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshls8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshls8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlu64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshlu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_uint64x1_t = vshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshlu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshrQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vshrq_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshrQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vshrq_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshrQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x2_t = vshrq_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshrQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vshrq_n_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshrQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vshrq_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshrQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vshrq_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshrQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x2_t = vshrq_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshrQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vshrq_n_u8 (arg0_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshr_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshr_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vshr_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshr_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshr_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vshr_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshr_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshr_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x1_t = vshr_n_s64 (arg0_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshr_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshr_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vshr_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshr_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshr_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vshr_n_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshr_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshr_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vshr_n_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshr_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshr_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x1_t = vshr_n_u64 (arg0_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshr_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshr_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vshr_n_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshrn_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrn_ns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x8_t = vshrn_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshrn_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrn_ns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x4_t = vshrn_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshrn_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrn_ns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x2_t = vshrn_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshrn_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrn_nu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x8_t = vshrn_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshrn_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrn_nu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x4_t = vshrn_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vshrn_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrn_nu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x2_t = vshrn_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsliQ_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_np16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8_t = vsliq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsliQ_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_np8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vsliq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsliQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vsliq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsliQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vsliq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsliQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vsliq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsliQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vsliq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsliQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vsliq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsliQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vsliq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsliQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vsliq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsliQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vsliq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsli_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_np16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4_t = vsli_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsli_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_np8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vsli_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsli_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vsli_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsli_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vsli_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsli_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vsli_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsli_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vsli_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsli_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vsli_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsli_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vsli_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsli_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vsli_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsli_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vsli_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsraQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsraQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsraQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsraQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsraQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsraQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsraQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsraQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsra_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsra_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsra_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsra_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsra_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsra_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsra_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsra_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsra_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsra_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsra_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsra_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsra_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsra_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsra_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsra_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsriQ_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_np16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8_t = vsriq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsriQ_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_np8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vsriq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsriQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vsriq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsriQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vsriq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsriQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vsriq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsriQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vsriq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsriQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vsriq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsriQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vsriq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsriQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vsriq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsriQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vsriq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsri_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_np16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4_t = vsri_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsri_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_np8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vsri_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsri_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vsri_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsri_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vsri_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsri_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vsri_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsri_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vsri_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsri_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vsri_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsri_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vsri_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsri_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vsri_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsri_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vsri_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4_t arg1_float32x4_t;
+
+  vst1q_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  vst1q_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1Q_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanep8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  vst1q_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8_t arg1_int16x8_t;
+
+  vst1q_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4_t arg1_int32x4_t;
+
+  vst1q_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1Q_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanes64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x2_t arg1_int64x2_t;
+
+  vst1q_lane_s64 (arg0_int64_t, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1Q_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanes8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x16_t arg1_int8x16_t;
+
+  vst1q_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  vst1q_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  vst1q_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1Q_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_laneu64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  vst1q_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1Q_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_laneu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  vst1q_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qf32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4_t arg1_float32x4_t;
+
+  vst1q_f32 (arg0_float32_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qp16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  vst1q_p16 (arg0_poly16_t, arg1_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qp8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  vst1q_p8 (arg0_poly8_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qs16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8_t arg1_int16x8_t;
+
+  vst1q_s16 (arg0_int16_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qs32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4_t arg1_int32x4_t;
+
+  vst1q_s32 (arg0_int32_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1Qs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qs64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x2_t arg1_int64x2_t;
+
+  vst1q_s64 (arg0_int64_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qs8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x16_t arg1_int8x16_t;
+
+  vst1q_s8 (arg0_int8_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  vst1q_u16 (arg0_uint16_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  vst1q_u32 (arg0_uint32_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1Qu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qu64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  vst1q_u64 (arg0_uint64_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  vst1q_u8 (arg0_uint8_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2_t arg1_float32x2_t;
+
+  vst1_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  vst1_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanep8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  vst1_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4_t arg1_int16x4_t;
+
+  vst1_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2_t arg1_int32x2_t;
+
+  vst1_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanes64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x1_t arg1_int64x1_t;
+
+  vst1_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanes8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8_t arg1_int8x8_t;
+
+  vst1_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  vst1_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  vst1_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_laneu64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  vst1_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_laneu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  vst1_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1f32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1f32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2_t arg1_float32x2_t;
+
+  vst1_f32 (arg0_float32_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1p16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1p16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  vst1_p16 (arg0_poly16_t, arg1_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1p8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1p8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  vst1_p8 (arg0_poly8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1s16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1s16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4_t arg1_int16x4_t;
+
+  vst1_s16 (arg0_int16_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1s32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1s32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2_t arg1_int32x2_t;
+
+  vst1_s32 (arg0_int32_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1s64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1s64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x1_t arg1_int64x1_t;
+
+  vst1_s64 (arg0_int64_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1s8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1s8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8_t arg1_int8x8_t;
+
+  vst1_s8 (arg0_int8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1u16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1u16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  vst1_u16 (arg0_uint16_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1u32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1u32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  vst1_u32 (arg0_uint32_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1u64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1u64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  vst1_u64 (arg0_uint64_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1u8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst1u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst1u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1u8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  vst1_u8 (arg0_uint8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x2_t arg1_float32x4x2_t;
+
+  vst2q_lane_f32 (arg0_float32_t, arg1_float32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x2_t arg1_poly16x8x2_t;
+
+  vst2q_lane_p16 (arg0_poly16_t, arg1_poly16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x2_t arg1_int16x8x2_t;
+
+  vst2q_lane_s16 (arg0_int16_t, arg1_int16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x2_t arg1_int32x4x2_t;
+
+  vst2q_lane_s32 (arg0_int32_t, arg1_int32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x2_t arg1_uint16x8x2_t;
+
+  vst2q_lane_u16 (arg0_uint16_t, arg1_uint16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x2_t arg1_uint32x4x2_t;
+
+  vst2q_lane_u32 (arg0_uint32_t, arg1_uint32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qf32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x2_t arg1_float32x4x2_t;
+
+  vst2q_f32 (arg0_float32_t, arg1_float32x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qp16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x2_t arg1_poly16x8x2_t;
+
+  vst2q_p16 (arg0_poly16_t, arg1_poly16x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qp8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x16x2_t arg1_poly8x16x2_t;
+
+  vst2q_p8 (arg0_poly8_t, arg1_poly8x16x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qs16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x2_t arg1_int16x8x2_t;
+
+  vst2q_s16 (arg0_int16_t, arg1_int16x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qs32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x2_t arg1_int32x4x2_t;
+
+  vst2q_s32 (arg0_int32_t, arg1_int32x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qs8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x16x2_t arg1_int8x16x2_t;
+
+  vst2q_s8 (arg0_int8_t, arg1_int8x16x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x2_t arg1_uint16x8x2_t;
+
+  vst2q_u16 (arg0_uint16_t, arg1_uint16x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x2_t arg1_uint32x4x2_t;
+
+  vst2q_u32 (arg0_uint32_t, arg1_uint32x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x16x2_t arg1_uint8x16x2_t;
+
+  vst2q_u8 (arg0_uint8_t, arg1_uint8x16x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x2_t arg1_float32x2x2_t;
+
+  vst2_lane_f32 (arg0_float32_t, arg1_float32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x2_t arg1_poly16x4x2_t;
+
+  vst2_lane_p16 (arg0_poly16_t, arg1_poly16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanep8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x2_t arg1_poly8x8x2_t;
+
+  vst2_lane_p8 (arg0_poly8_t, arg1_poly8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x2_t arg1_int16x4x2_t;
+
+  vst2_lane_s16 (arg0_int16_t, arg1_int16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x2_t arg1_int32x2x2_t;
+
+  vst2_lane_s32 (arg0_int32_t, arg1_int32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanes8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x2_t arg1_int8x8x2_t;
+
+  vst2_lane_s8 (arg0_int8_t, arg1_int8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x2_t arg1_uint16x4x2_t;
+
+  vst2_lane_u16 (arg0_uint16_t, arg1_uint16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x2_t arg1_uint32x2x2_t;
+
+  vst2_lane_u32 (arg0_uint32_t, arg1_uint32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_laneu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x2_t arg1_uint8x8x2_t;
+
+  vst2_lane_u8 (arg0_uint8_t, arg1_uint8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2f32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2f32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x2_t arg1_float32x2x2_t;
+
+  vst2_f32 (arg0_float32_t, arg1_float32x2x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2p16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2p16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x2_t arg1_poly16x4x2_t;
+
+  vst2_p16 (arg0_poly16_t, arg1_poly16x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2p8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2p8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x2_t arg1_poly8x8x2_t;
+
+  vst2_p8 (arg0_poly8_t, arg1_poly8x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2s16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2s16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x2_t arg1_int16x4x2_t;
+
+  vst2_s16 (arg0_int16_t, arg1_int16x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2s32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2s32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x2_t arg1_int32x2x2_t;
+
+  vst2_s32 (arg0_int32_t, arg1_int32x2x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2s64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2s64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x1x2_t arg1_int64x1x2_t;
+
+  vst2_s64 (arg0_int64_t, arg1_int64x1x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2s8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2s8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x2_t arg1_int8x8x2_t;
+
+  vst2_s8 (arg0_int8_t, arg1_int8x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2u16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2u16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x2_t arg1_uint16x4x2_t;
+
+  vst2_u16 (arg0_uint16_t, arg1_uint16x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2u32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2u32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x2_t arg1_uint32x2x2_t;
+
+  vst2_u32 (arg0_uint32_t, arg1_uint32x2x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2u64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2u64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x1x2_t arg1_uint64x1x2_t;
+
+  vst2_u64 (arg0_uint64_t, arg1_uint64x1x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2u8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst2u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst2u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2u8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x2_t arg1_uint8x8x2_t;
+
+  vst2_u8 (arg0_uint8_t, arg1_uint8x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x3_t arg1_float32x4x3_t;
+
+  vst3q_lane_f32 (arg0_float32_t, arg1_float32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x3_t arg1_poly16x8x3_t;
+
+  vst3q_lane_p16 (arg0_poly16_t, arg1_poly16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x3_t arg1_int16x8x3_t;
+
+  vst3q_lane_s16 (arg0_int16_t, arg1_int16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x3_t arg1_int32x4x3_t;
+
+  vst3q_lane_s32 (arg0_int32_t, arg1_int32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x3_t arg1_uint16x8x3_t;
+
+  vst3q_lane_u16 (arg0_uint16_t, arg1_uint16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x3_t arg1_uint32x4x3_t;
+
+  vst3q_lane_u32 (arg0_uint32_t, arg1_uint32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qf32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x3_t arg1_float32x4x3_t;
+
+  vst3q_f32 (arg0_float32_t, arg1_float32x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qp16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x3_t arg1_poly16x8x3_t;
+
+  vst3q_p16 (arg0_poly16_t, arg1_poly16x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qp8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x16x3_t arg1_poly8x16x3_t;
+
+  vst3q_p8 (arg0_poly8_t, arg1_poly8x16x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qs16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x3_t arg1_int16x8x3_t;
+
+  vst3q_s16 (arg0_int16_t, arg1_int16x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qs32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x3_t arg1_int32x4x3_t;
+
+  vst3q_s32 (arg0_int32_t, arg1_int32x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qs8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x16x3_t arg1_int8x16x3_t;
+
+  vst3q_s8 (arg0_int8_t, arg1_int8x16x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x3_t arg1_uint16x8x3_t;
+
+  vst3q_u16 (arg0_uint16_t, arg1_uint16x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x3_t arg1_uint32x4x3_t;
+
+  vst3q_u32 (arg0_uint32_t, arg1_uint32x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x16x3_t arg1_uint8x16x3_t;
+
+  vst3q_u8 (arg0_uint8_t, arg1_uint8x16x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x3_t arg1_float32x2x3_t;
+
+  vst3_lane_f32 (arg0_float32_t, arg1_float32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x3_t arg1_poly16x4x3_t;
+
+  vst3_lane_p16 (arg0_poly16_t, arg1_poly16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanep8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x3_t arg1_poly8x8x3_t;
+
+  vst3_lane_p8 (arg0_poly8_t, arg1_poly8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x3_t arg1_int16x4x3_t;
+
+  vst3_lane_s16 (arg0_int16_t, arg1_int16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x3_t arg1_int32x2x3_t;
+
+  vst3_lane_s32 (arg0_int32_t, arg1_int32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanes8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x3_t arg1_int8x8x3_t;
+
+  vst3_lane_s8 (arg0_int8_t, arg1_int8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x3_t arg1_uint16x4x3_t;
+
+  vst3_lane_u16 (arg0_uint16_t, arg1_uint16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x3_t arg1_uint32x2x3_t;
+
+  vst3_lane_u32 (arg0_uint32_t, arg1_uint32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_laneu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x3_t arg1_uint8x8x3_t;
+
+  vst3_lane_u8 (arg0_uint8_t, arg1_uint8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3f32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3f32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x3_t arg1_float32x2x3_t;
+
+  vst3_f32 (arg0_float32_t, arg1_float32x2x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3p16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3p16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x3_t arg1_poly16x4x3_t;
+
+  vst3_p16 (arg0_poly16_t, arg1_poly16x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3p8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3p8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x3_t arg1_poly8x8x3_t;
+
+  vst3_p8 (arg0_poly8_t, arg1_poly8x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3s16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3s16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x3_t arg1_int16x4x3_t;
+
+  vst3_s16 (arg0_int16_t, arg1_int16x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3s32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3s32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x3_t arg1_int32x2x3_t;
+
+  vst3_s32 (arg0_int32_t, arg1_int32x2x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3s64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3s64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x1x3_t arg1_int64x1x3_t;
+
+  vst3_s64 (arg0_int64_t, arg1_int64x1x3_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3s8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3s8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x3_t arg1_int8x8x3_t;
+
+  vst3_s8 (arg0_int8_t, arg1_int8x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3u16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3u16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x3_t arg1_uint16x4x3_t;
+
+  vst3_u16 (arg0_uint16_t, arg1_uint16x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3u32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3u32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x3_t arg1_uint32x2x3_t;
+
+  vst3_u32 (arg0_uint32_t, arg1_uint32x2x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3u64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3u64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x1x3_t arg1_uint64x1x3_t;
+
+  vst3_u64 (arg0_uint64_t, arg1_uint64x1x3_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3u8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst3u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst3u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3u8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x3_t arg1_uint8x8x3_t;
+
+  vst3_u8 (arg0_uint8_t, arg1_uint8x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x4_t arg1_float32x4x4_t;
+
+  vst4q_lane_f32 (arg0_float32_t, arg1_float32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x4_t arg1_poly16x8x4_t;
+
+  vst4q_lane_p16 (arg0_poly16_t, arg1_poly16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x4_t arg1_int16x8x4_t;
+
+  vst4q_lane_s16 (arg0_int16_t, arg1_int16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x4_t arg1_int32x4x4_t;
+
+  vst4q_lane_s32 (arg0_int32_t, arg1_int32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x4_t arg1_uint16x8x4_t;
+
+  vst4q_lane_u16 (arg0_uint16_t, arg1_uint16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x4_t arg1_uint32x4x4_t;
+
+  vst4q_lane_u32 (arg0_uint32_t, arg1_uint32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qf32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x4_t arg1_float32x4x4_t;
+
+  vst4q_f32 (arg0_float32_t, arg1_float32x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qp16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x4_t arg1_poly16x8x4_t;
+
+  vst4q_p16 (arg0_poly16_t, arg1_poly16x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qp8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x16x4_t arg1_poly8x16x4_t;
+
+  vst4q_p8 (arg0_poly8_t, arg1_poly8x16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qs16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x4_t arg1_int16x8x4_t;
+
+  vst4q_s16 (arg0_int16_t, arg1_int16x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qs32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x4_t arg1_int32x4x4_t;
+
+  vst4q_s32 (arg0_int32_t, arg1_int32x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qs8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x16x4_t arg1_int8x16x4_t;
+
+  vst4q_s8 (arg0_int8_t, arg1_int8x16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x4_t arg1_uint16x8x4_t;
+
+  vst4q_u16 (arg0_uint16_t, arg1_uint16x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x4_t arg1_uint32x4x4_t;
+
+  vst4q_u32 (arg0_uint32_t, arg1_uint32x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x16x4_t arg1_uint8x16x4_t;
+
+  vst4q_u8 (arg0_uint8_t, arg1_uint8x16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x4_t arg1_float32x2x4_t;
+
+  vst4_lane_f32 (arg0_float32_t, arg1_float32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x4_t arg1_poly16x4x4_t;
+
+  vst4_lane_p16 (arg0_poly16_t, arg1_poly16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanep8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x4_t arg1_poly8x8x4_t;
+
+  vst4_lane_p8 (arg0_poly8_t, arg1_poly8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x4_t arg1_int16x4x4_t;
+
+  vst4_lane_s16 (arg0_int16_t, arg1_int16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x4_t arg1_int32x2x4_t;
+
+  vst4_lane_s32 (arg0_int32_t, arg1_int32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanes8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x4_t arg1_int8x8x4_t;
+
+  vst4_lane_s8 (arg0_int8_t, arg1_int8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x4_t arg1_uint16x4x4_t;
+
+  vst4_lane_u16 (arg0_uint16_t, arg1_uint16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x4_t arg1_uint32x2x4_t;
+
+  vst4_lane_u32 (arg0_uint32_t, arg1_uint32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_laneu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x4_t arg1_uint8x8x4_t;
+
+  vst4_lane_u8 (arg0_uint8_t, arg1_uint8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4f32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4f32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x4_t arg1_float32x2x4_t;
+
+  vst4_f32 (arg0_float32_t, arg1_float32x2x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4p16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4p16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x4_t arg1_poly16x4x4_t;
+
+  vst4_p16 (arg0_poly16_t, arg1_poly16x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4p8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4p8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x4_t arg1_poly8x8x4_t;
+
+  vst4_p8 (arg0_poly8_t, arg1_poly8x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4s16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4s16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x4_t arg1_int16x4x4_t;
+
+  vst4_s16 (arg0_int16_t, arg1_int16x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4s32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4s32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x4_t arg1_int32x2x4_t;
+
+  vst4_s32 (arg0_int32_t, arg1_int32x2x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4s64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4s64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x1x4_t arg1_int64x1x4_t;
+
+  vst4_s64 (arg0_int64_t, arg1_int64x1x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4s8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4s8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x4_t arg1_int8x8x4_t;
+
+  vst4_s8 (arg0_int8_t, arg1_int8x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4u16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4u16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x4_t arg1_uint16x4x4_t;
+
+  vst4_u16 (arg0_uint16_t, arg1_uint16x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4u32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4u32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x4_t arg1_uint32x2x4_t;
+
+  vst4_u32 (arg0_uint32_t, arg1_uint32x2x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4u64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4u64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x1x4_t arg1_uint64x1x4_t;
+
+  vst4_u64 (arg0_uint64_t, arg1_uint64x1x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4u8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vst4u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vst4u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4u8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x4_t arg1_uint8x8x4_t;
+
+  vst4_u8 (arg0_uint8_t, arg1_uint8x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vsubq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vsubq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vsubq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vsubq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vsubq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubf32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vsub_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubhns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubhns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int8x8_t = vsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubhns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubhns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int16x4_t = vsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubhns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubhns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int32x2_t = vsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubhnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubhnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint8x8_t = vsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubhnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubhnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint16x4_t = vsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubhnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubhnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint32x2_t = vsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubls16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubls16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubls16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubls16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vsubl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubls32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubls32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubls32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubls32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vsubl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubls8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubls8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubls8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubls8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubls8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x8_t = vsubl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsublu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsublu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsublu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsublu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsublu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsublu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vsubl_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsublu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsublu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsublu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsublu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsublu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsublu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vsubl_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsublu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsublu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsublu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsublu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsublu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsublu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x8_t = vsubl_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubs16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vsub_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubs32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vsub_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubs64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubs64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubs64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubs64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubs64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vsub_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubs8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vsub_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubu64.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubws16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubws16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubws16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubws16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubws16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubws16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vsubw_s16 (arg0_int32x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubws32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubws32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubws32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubws32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubws32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubws32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vsubw_s32 (arg0_int64x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubws8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubws8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubws8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubws8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubws8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubws8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x8_t = vsubw_s8 (arg0_int16x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubwu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubwu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vsubw_u16 (arg0_uint32x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubwu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubwu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vsubw_u32 (arg0_uint64x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vsubwu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubwu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x8_t = vsubw_u8 (arg0_uint16x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtbl1p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl1p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_poly8x8_t = vtbl1_p8 (arg0_poly8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtbl1s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl1s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vtbl1_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtbl1u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl1u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vtbl1_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtbl2p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl2p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8x2_t arg0_poly8x8x2_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_poly8x8_t = vtbl2_p8 (arg0_poly8x8x2_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtbl2s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl2s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8x2_t arg0_int8x8x2_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vtbl2_s8 (arg0_int8x8x2_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtbl2u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl2u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8x2_t arg0_uint8x8x2_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vtbl2_u8 (arg0_uint8x8x2_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtbl3p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl3p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8x3_t arg0_poly8x8x3_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_poly8x8_t = vtbl3_p8 (arg0_poly8x8x3_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtbl3s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl3s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8x3_t arg0_int8x8x3_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vtbl3_s8 (arg0_int8x8x3_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtbl3u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl3u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8x3_t arg0_uint8x8x3_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vtbl3_u8 (arg0_uint8x8x3_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtbl4p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl4p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8x4_t arg0_poly8x8x4_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_poly8x8_t = vtbl4_p8 (arg0_poly8x8x4_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtbl4s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl4s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8x4_t arg0_int8x8x4_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vtbl4_s8 (arg0_int8x8x4_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtbl4u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl4u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8x4_t arg0_uint8x8x4_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vtbl4_u8 (arg0_uint8x8x4_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtbx1p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx1p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_poly8x8_t = vtbx1_p8 (arg0_poly8x8_t, arg1_poly8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtbx1s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx1s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vtbx1_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtbx1u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx1u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vtbx1_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtbx2p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx2p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8x2_t arg1_poly8x8x2_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_poly8x8_t = vtbx2_p8 (arg0_poly8x8_t, arg1_poly8x8x2_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtbx2s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx2s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8x2_t arg1_int8x8x2_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vtbx2_s8 (arg0_int8x8_t, arg1_int8x8x2_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtbx2u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx2u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8x2_t arg1_uint8x8x2_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vtbx2_u8 (arg0_uint8x8_t, arg1_uint8x8x2_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtbx3p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx3p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8x3_t arg1_poly8x8x3_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_poly8x8_t = vtbx3_p8 (arg0_poly8x8_t, arg1_poly8x8x3_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtbx3s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx3s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8x3_t arg1_int8x8x3_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vtbx3_s8 (arg0_int8x8_t, arg1_int8x8x3_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtbx3u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx3u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8x3_t arg1_uint8x8x3_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vtbx3_u8 (arg0_uint8x8_t, arg1_uint8x8x3_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtbx4p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx4p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8x4_t arg1_poly8x8x4_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_poly8x8_t = vtbx4_p8 (arg0_poly8x8_t, arg1_poly8x8x4_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtbx4s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx4s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8x4_t arg1_int8x8x4_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vtbx4_s8 (arg0_int8x8_t, arg1_int8x8x4_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtbx4u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx4u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8x4_t arg1_uint8x8x4_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vtbx4_u8 (arg0_uint8x8_t, arg1_uint8x8x4_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtrnQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQf32 (void)
+{
+  float32x4x2_t out_float32x4x2_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4x2_t = vtrnq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtrnQp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQp16 (void)
+{
+  poly16x8x2_t out_poly16x8x2_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8x2_t = vtrnq_p16 (arg0_poly16x8_t, arg1_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtrnQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQp8 (void)
+{
+  poly8x16x2_t out_poly8x16x2_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16x2_t = vtrnq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtrnQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQs16 (void)
+{
+  int16x8x2_t out_int16x8x2_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8x2_t = vtrnq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtrnQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQs32 (void)
+{
+  int32x4x2_t out_int32x4x2_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4x2_t = vtrnq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtrnQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQs8 (void)
+{
+  int8x16x2_t out_int8x16x2_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16x2_t = vtrnq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtrnQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQu16 (void)
+{
+  uint16x8x2_t out_uint16x8x2_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8x2_t = vtrnq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtrnQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQu32 (void)
+{
+  uint32x4x2_t out_uint32x4x2_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4x2_t = vtrnq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtrnQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQu8 (void)
+{
+  uint8x16x2_t out_uint8x16x2_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16x2_t = vtrnq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtrnf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnf32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2x2_t = vtrn_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtrnp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnp16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4x2_t = vtrn_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtrnp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnp8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8x2_t = vtrn_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrns16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtrns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrns16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4x2_t = vtrn_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrns32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtrns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrns32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2x2_t = vtrn_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrns8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrns8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrns8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrns8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtrns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrns8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8x2_t = vtrn_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtrnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnu16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4x2_t = vtrn_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtrnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnu32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2x2_t = vtrn_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtrnu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnu8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8x2_t = vtrn_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtstQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstQp8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_uint8x16_t = vtstq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtstQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstQs16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vtstq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtstQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstQs32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vtstq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtstQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstQs8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vtstq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtstQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vtstq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtstQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vtstq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtstQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vtstq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstp8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtstp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstp8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_uint8x8_t = vtst_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtsts16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtsts16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtsts16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtsts16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtsts16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtsts16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vtst_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtsts32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtsts32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtsts32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtsts32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtsts32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtsts32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vtst_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtsts8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtsts8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtsts8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtsts8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtsts8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtsts8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vtst_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtstu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vtst_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtstu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vtst_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vtstu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vtstu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vtst_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vuzpQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQf32 (void)
+{
+  float32x4x2_t out_float32x4x2_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4x2_t = vuzpq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vuzpQp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQp16 (void)
+{
+  poly16x8x2_t out_poly16x8x2_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8x2_t = vuzpq_p16 (arg0_poly16x8_t, arg1_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vuzpQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQp8 (void)
+{
+  poly8x16x2_t out_poly8x16x2_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16x2_t = vuzpq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vuzpQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQs16 (void)
+{
+  int16x8x2_t out_int16x8x2_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8x2_t = vuzpq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vuzpQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQs32 (void)
+{
+  int32x4x2_t out_int32x4x2_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4x2_t = vuzpq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vuzpQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQs8 (void)
+{
+  int8x16x2_t out_int8x16x2_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16x2_t = vuzpq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vuzpQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQu16 (void)
+{
+  uint16x8x2_t out_uint16x8x2_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8x2_t = vuzpq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vuzpQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQu32 (void)
+{
+  uint32x4x2_t out_uint32x4x2_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4x2_t = vuzpq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vuzpQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQu8 (void)
+{
+  uint8x16x2_t out_uint8x16x2_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16x2_t = vuzpq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vuzpf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpf32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2x2_t = vuzp_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vuzpp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpp16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4x2_t = vuzp_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vuzpp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpp8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8x2_t = vuzp_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzps16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzps16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzps16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzps16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vuzps16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzps16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4x2_t = vuzp_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzps32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzps32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzps32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzps32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vuzps32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzps32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2x2_t = vuzp_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzps8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzps8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzps8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzps8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vuzps8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzps8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8x2_t = vuzp_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vuzpu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpu16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4x2_t = vuzp_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vuzpu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpu32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2x2_t = vuzp_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vuzpu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpu8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8x2_t = vuzp_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vzipQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQf32 (void)
+{
+  float32x4x2_t out_float32x4x2_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4x2_t = vzipq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vzipQp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQp16 (void)
+{
+  poly16x8x2_t out_poly16x8x2_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8x2_t = vzipq_p16 (arg0_poly16x8_t, arg1_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vzipQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQp8 (void)
+{
+  poly8x16x2_t out_poly8x16x2_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16x2_t = vzipq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vzipQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQs16 (void)
+{
+  int16x8x2_t out_int16x8x2_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8x2_t = vzipq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vzipQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQs32 (void)
+{
+  int32x4x2_t out_int32x4x2_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4x2_t = vzipq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vzipQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQs8 (void)
+{
+  int8x16x2_t out_int8x16x2_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16x2_t = vzipq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vzipQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQu16 (void)
+{
+  uint16x8x2_t out_uint16x8x2_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8x2_t = vzipq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vzipQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQu32 (void)
+{
+  uint32x4x2_t out_uint32x4x2_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4x2_t = vzipq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vzipQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQu8 (void)
+{
+  uint8x16x2_t out_uint8x16x2_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16x2_t = vzipq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipf32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vzipf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipf32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2x2_t = vzip_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipp16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipp16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipp16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipp16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vzipp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipp16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4x2_t = vzip_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipp8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vzipp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipp8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8x2_t = vzip_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzips16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzips16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzips16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzips16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vzips16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzips16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4x2_t = vzip_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzips32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzips32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzips32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzips32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vzips32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzips32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2x2_t = vzip_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzips8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzips8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzips8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzips8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vzips8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzips8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8x2_t = vzip_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipu16.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vzipu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipu16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4x2_t = vzip_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipu32.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vzipu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipu32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2x2_t = vzip_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipu8.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vzipu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vzipu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipu8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8x2_t = vzip_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,16 @@
+/* APPLE LOCAL file v7 merge */
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
+
+extern void bar (double);
+
+void
+foo (double *p, double a, int n)
+{
+  do
+    bar (*--p + a);
+  while (n--);
+}
+
+/* { dg-final { scan-assembler "fldmdbd" } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,16 @@
+/* APPLE LOCAL file v7 merge */
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
+
+extern void baz (float);
+
+void
+foo (float *p, float a, int n)
+{
+  do
+    bar (*--p + a);
+  while (n--);
+}
+
+/* { dg-final { scan-assembler "fldmdbs" } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,16 @@
+/* APPLE LOCAL file v7 merge */
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
+
+extern void bar (double);
+
+void
+foo (double *p, double a, int n)
+{
+  do
+    bar (*p++ + a);
+  while (n--);
+}
+
+/* { dg-final { scan-assembler "fldmiad" } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-ldmias.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-ldmias.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-ldmias.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-ldmias.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,16 @@
+/* APPLE LOCAL file v7 merge */
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
+
+extern void baz (float);
+
+void
+foo (float *p, float a, int n)
+{
+  do
+    bar (*p++ + a);
+  while (n--);
+}
+
+/* { dg-final { scan-assembler "fldmias" } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,15 @@
+/* APPLE LOCAL file v7 merge */
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
+
+void
+foo (double *p, double a, double b, int n)
+{
+  double c = a + b;
+  do
+    *--p = c;
+  while (n--);
+}
+
+/* { dg-final { scan-assembler "fstmdbd" } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,15 @@
+/* APPLE LOCAL file v7 merge */
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
+
+void
+foo (float *p, float a, float b, int n)
+{
+  float c = a + b;
+  do
+    *--p = c;
+  while (n--);
+}
+
+/* { dg-final { scan-assembler "fstmdbs" } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-stmiad.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-stmiad.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-stmiad.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-stmiad.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,15 @@
+/* APPLE LOCAL file v7 merge */
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
+
+void
+foo (double *p, double a, double b, int n)
+{
+  double c = a + b;
+  do
+    *p++ = c;
+  while (n--);
+}
+
+/* { dg-final { scan-assembler "fstmiad" } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-stmias.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-stmias.c?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-stmias.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/vfp-stmias.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,15 @@
+/* APPLE LOCAL file v7 merge */
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
+
+void
+foo (float *p, float a, float b, int n)
+{
+  float c = a + b;
+  do
+    *p++ = c;
+  while (n--);
+}
+
+/* { dg-final { scan-assembler "fstmias" } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/obj-c++.dg/objc2-protocol-3.mm
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/obj-c%2B%2B.dg/objc2-protocol-3.mm?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/obj-c++.dg/objc2-protocol-3.mm (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/obj-c++.dg/objc2-protocol-3.mm Wed Jul 22 15:36:27 2009
@@ -0,0 +1,26 @@
+/* APPLE LOCAL file radar 6351990 */
+/* { dg-options "-mmacosx-version-min=10.6 -m32 -fobjc-abi-version=2" { target powerpc*-*-darwin* i?86*-*-darwin* } } */
+/* { dg-options "-fobjc-abi-version=2" { target arm*-*-darwin* } } */
+/* { dg-do compile { target *-*-darwin* } } */
+
+ at protocol PROTO
+ at end
+ at protocol PROTO1
+ at end
+ at protocol PROTO2
+ at end
+
+ at interface INTF <PROTO, PROTO1, PROTO2> @end
+
+ at implementation INTF @end
+
+int main()
+{
+	return (long) @protocol(PROTO); + (long) @protocol(PROTO1);
+}
+/* { dg-final { if [istarget i?86-*-darwin* ] { scan-assembler "L_ZL23_OBJC_PROTOCOL_\\\$_PROTO1:" } } } */
+/* { dg-final { if [istarget powerpc*-*-darwin* ] { scan-assembler "L_ZL23_OBJC_PROTOCOL_\\\$_PROTO1:" } } } */
+/* { dg-final { if [istarget arm*-*-darwin* ] { scan-assembler "l_OBJC_PROTOCOL_\\\$_PROTO1:" } } } */
+/* { dg-final { if [istarget i?86-*-darwin* ] { scan-assembler "L_ZL23_OBJC_PROTOCOL_\\\$_PROTO2:" } } } */
+/* { dg-final { if [istarget powerpc*-*-darwin* ] { scan-assembler "L_ZL23_OBJC_PROTOCOL_\\\$_PROTO2:" } } } */
+/* { dg-final { if [istarget arm*-*-darwin* ] { scan-assembler "l_OBJC_PROTOCOL_\\\$_PROTO2:" } } } */

Added: llvm-gcc-4.2/trunk/gcc/testsuite/obj-c++.dg/property-as-initializer.mm
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/obj-c%2B%2B.dg/property-as-initializer.mm?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/obj-c++.dg/property-as-initializer.mm (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/obj-c++.dg/property-as-initializer.mm Wed Jul 22 15:36:27 2009
@@ -0,0 +1,41 @@
+/* APPLE LOCAL file radar 6936421 */
+/* Test that no seg. fault is generated due to initializer being a property
+   getter of a class with copy constructor. */
+/* { dg-options "-mmacosx-version-min=10.5" { target *-*-darwin* } } */
+/* { dg-do compile { target *-*-darwin* } } */
+
+struct vector {
+  vector();
+  vector(const vector &);
+};
+
+typedef vector operations_t;
+
+
+ at interface GridManager 
+{
+ operations_t operations;
+}
+
+ at property (readonly) operations_t operations;
+ at end
+
+ at interface MainView {
+ GridManager *gmgr;
+}
+- (void)placeOperations;
+ at end
+
+void cvt(operations_t);
+
+ at implementation MainView
+-(void)placeOperations
+{
+  operations_t operations = gmgr.operations;
+  operations = gmgr.operations;
+
+  (operations_t)gmgr.operations;
+  cvt(gmgr.operations);
+}
+
+ at end

Added: llvm-gcc-4.2/trunk/gcc/testsuite/objc.dg/objc2-protocol-3.m
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/objc.dg/objc2-protocol-3.m?rev=76781&view=auto

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/objc.dg/objc2-protocol-3.m (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/objc.dg/objc2-protocol-3.m Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file radar 6351990 */
+/* { dg-options "-mmacosx-version-min=10.6 -m32 -fobjc-abi-version=2" { target powerpc*-*-darwin* i?86*-*-darwin* } } */
+/* { dg-options "-fobjc-abi-version=2" { target arm*-*-darwin* } } */
+/* { dg-do compile { target *-*-darwin* } } */
+
+ at protocol PROTO
+ at end
+ at protocol PROTO1
+ at end
+ at protocol PROTO2
+ at end
+
+ at interface INTF <PROTO, PROTO1, PROTO2> @end
+
+ at implementation INTF @end
+
+int main()
+{
+	return (long) @protocol(PROTO); + (long) @protocol(PROTO1);
+}
+/* { dg-final { scan-assembler "l_OBJC_PROTOCOL_\\\$_PROTO1:" } } */
+/* { dg-final { scan-assembler "l_OBJC_PROTOCOL_\\\$_PROTO2:" } } */

Modified: llvm-gcc-4.2/trunk/gcc/varasm.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/varasm.c?rev=76781&r1=76780&r2=76781&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/varasm.c (original)
+++ llvm-gcc-4.2/trunk/gcc/varasm.c Wed Jul 22 15:36:27 2009
@@ -4758,6 +4758,7 @@
       && GET_CODE (XEXP (DECL_RTL (decl), 0)) == SYMBOL_REF)
     SYMBOL_REF_WEAK (XEXP (DECL_RTL (decl), 0)) = 1;
 #endif
+  /* LLVM LOCAL end */
 }
 
 /* Merge weak status between NEWDECL and OLDDECL.  */

Modified: llvm-gcc-4.2/trunk/gcc/version.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/version.c?rev=76781&r1=76780&r2=76781&view=diff

==============================================================================
--- llvm-gcc-4.2/trunk/gcc/version.c (original)
+++ llvm-gcc-4.2/trunk/gcc/version.c Wed Jul 22 15:36:27 2009
@@ -11,12 +11,12 @@
 /* APPLE LOCAL begin Apple version */
 #ifdef ENABLE_LLVM
 #ifdef LLVM_VERSION_INFO
-#define VERSUFFIX " (Based on Apple Inc. build 5646) (LLVM build " LLVM_VERSION_INFO ")"
+#define VERSUFFIX " (Based on Apple Inc. build 5647) (LLVM build " LLVM_VERSION_INFO ")"
 #else
-#define VERSUFFIX " (Based on Apple Inc. build 5646) (LLVM build)"
+#define VERSUFFIX " (Based on Apple Inc. build 5647) (LLVM build)"
 #endif
 #else
-#define VERSUFFIX " (Based on Apple Inc. build 5646)"
+#define VERSUFFIX " (Based on Apple Inc. build 5647)"
 #endif
 /* APPLE LOCAL end Apple version */
 



