[llvm-commits] [llvm] r76725 - in /llvm/trunk/lib/Target/ARM: ARMBaseRegisterInfo.cpp ARMBaseRegisterInfo.h ARMCodeEmitter.cpp
Evan Cheng
evan.cheng at apple.com
Tue Jul 21 22:55:19 PDT 2009
Author: evancheng
Date: Wed Jul 22 00:55:18 2009
New Revision: 76725
URL: http://llvm.org/viewvc/llvm-project?rev=76725&view=rev
Log:
Get rid one of the getRegisterNumbering. Also add D16 - D31.
Modified:
llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=76725&r1=76724&r2=76725&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Wed Jul 22 00:55:18 2009
@@ -38,70 +38,48 @@
#include "llvm/ADT/SmallVector.h"
using namespace llvm;
-unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
- using namespace ARM;
- switch (RegEnum) {
- case R0: case S0: case D0: return 0;
- case R1: case S1: case D1: return 1;
- case R2: case S2: case D2: return 2;
- case R3: case S3: case D3: return 3;
- case R4: case S4: case D4: return 4;
- case R5: case S5: case D5: return 5;
- case R6: case S6: case D6: return 6;
- case R7: case S7: case D7: return 7;
- case R8: case S8: case D8: return 8;
- case R9: case S9: case D9: return 9;
- case R10: case S10: case D10: return 10;
- case R11: case S11: case D11: return 11;
- case R12: case S12: case D12: return 12;
- case SP: case S13: case D13: return 13;
- case LR: case S14: case D14: return 14;
- case PC: case S15: case D15: return 15;
- case S16: return 16;
- case S17: return 17;
- case S18: return 18;
- case S19: return 19;
- case S20: return 20;
- case S21: return 21;
- case S22: return 22;
- case S23: return 23;
- case S24: return 24;
- case S25: return 25;
- case S26: return 26;
- case S27: return 27;
- case S28: return 28;
- case S29: return 29;
- case S30: return 30;
- case S31: return 31;
- default:
- llvm_unreachable("Unknown ARM register!");
- }
-}
-
unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
- bool &isSPVFP) {
- isSPVFP = false;
+ bool *isSPVFP) {
+ if (isSPVFP)
+ *isSPVFP = false;
using namespace ARM;
switch (RegEnum) {
default:
llvm_unreachable("Unknown ARM register!");
- case R0: case D0: return 0;
- case R1: case D1: return 1;
- case R2: case D2: return 2;
- case R3: case D3: return 3;
- case R4: case D4: return 4;
- case R5: case D5: return 5;
- case R6: case D6: return 6;
- case R7: case D7: return 7;
- case R8: case D8: return 8;
- case R9: case D9: return 9;
- case R10: case D10: return 10;
- case R11: case D11: return 11;
- case R12: case D12: return 12;
- case SP: case D13: return 13;
- case LR: case D14: return 14;
- case PC: case D15: return 15;
+ case R0: case D0: case Q0: return 0;
+ case R1: case D1: case Q1: return 1;
+ case R2: case D2: case Q2: return 2;
+ case R3: case D3: case Q3: return 3;
+ case R4: case D4: case Q4: return 4;
+ case R5: case D5: case Q5: return 5;
+ case R6: case D6: case Q6: return 6;
+ case R7: case D7: case Q7: return 7;
+ case R8: case D8: case Q8: return 8;
+ case R9: case D9: case Q9: return 9;
+ case R10: case D10: case Q10: return 10;
+ case R11: case D11: case Q11: return 11;
+ case R12: case D12: case Q12: return 12;
+ case SP: case D13: case Q13: return 13;
+ case LR: case D14: case Q14: return 14;
+ case PC: case D15: case Q15: return 15;
+
+ case D16: return 16;
+ case D17: return 17;
+ case D18: return 18;
+ case D19: return 19;
+ case D20: return 20;
+ case D21: return 21;
+ case D22: return 22;
+ case D23: return 23;
+ case D24: return 24;
+ case D25: return 25;
+ case D26: return 27;
+ case D27: return 27;
+ case D28: return 28;
+ case D29: return 29;
+ case D30: return 30;
+ case D31: return 31;
case S0: case S1: case S2: case S3:
case S4: case S5: case S6: case S7:
@@ -110,8 +88,9 @@
case S16: case S17: case S18: case S19:
case S20: case S21: case S22: case S23:
case S24: case S25: case S26: case S27:
- case S28: case S29: case S30: case S31: {
- isSPVFP = true;
+ case S28: case S29: case S30: case S31: {
+ if (isSPVFP)
+ *isSPVFP = true;
switch (RegEnum) {
default: return 0; // Avoid compile time warning.
case S0: return 0;
@@ -791,6 +770,22 @@
return ARM::D12;
case ARM::D15:
return ARM::D14;
+ case ARM::D17:
+ return ARM::D16;
+ case ARM::D19:
+ return ARM::D18;
+ case ARM::D21:
+ return ARM::D20;
+ case ARM::D23:
+ return ARM::D22;
+ case ARM::D25:
+ return ARM::D24;
+ case ARM::D27:
+ return ARM::D26;
+ case ARM::D29:
+ return ARM::D28;
+ case ARM::D31:
+ return ARM::D30;
}
return 0;
@@ -865,6 +860,22 @@
return ARM::D13;
case ARM::D14:
return ARM::D15;
+ case ARM::D16:
+ return ARM::D17;
+ case ARM::D18:
+ return ARM::D19;
+ case ARM::D20:
+ return ARM::D21;
+ case ARM::D22:
+ return ARM::D23;
+ case ARM::D24:
+ return ARM::D25;
+ case ARM::D26:
+ return ARM::D27;
+ case ARM::D28:
+ return ARM::D29;
+ case ARM::D30:
+ return ARM::D31;
}
return 0;
Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=76725&r1=76724&r2=76725&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Wed Jul 22 00:55:18 2009
@@ -61,12 +61,10 @@
public:
/// getRegisterNumbering - Given the enum value for some register, e.g.
- /// ARM::LR, return the number that it corresponds to (e.g. 14).
- static unsigned getRegisterNumbering(unsigned RegEnum);
-
- /// Same as previous getRegisterNumbering except it returns true in isSPVFP
- /// if the register is a single precision VFP register.
- static unsigned getRegisterNumbering(unsigned RegEnum, bool &isSPVFP);
+ /// ARM::LR, return the number that it corresponds to (e.g. 14). It
+ /// also returns true in isSPVFP if the register is a single precision
+ /// VFP register.
+ static unsigned getRegisterNumbering(unsigned RegEnum, bool *isSPVFP = 0);
/// Code Generation virtual methods...
const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=76725&r1=76724&r2=76725&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Wed Jul 22 00:55:18 2009
@@ -1205,7 +1205,7 @@
unsigned RegD = MI.getOperand(OpIdx).getReg();
unsigned Binary = 0;
bool isSPVFP = false;
- RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP);
+ RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP);
if (!isSPVFP)
Binary |= RegD << ARMII::RegRdShift;
else {
@@ -1219,7 +1219,7 @@
unsigned RegN = MI.getOperand(OpIdx).getReg();
unsigned Binary = 0;
bool isSPVFP = false;
- RegN = ARMRegisterInfo::getRegisterNumbering(RegN, isSPVFP);
+ RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP);
if (!isSPVFP)
Binary |= RegN << ARMII::RegRnShift;
else {
@@ -1233,7 +1233,7 @@
unsigned RegM = MI.getOperand(OpIdx).getReg();
unsigned Binary = 0;
bool isSPVFP = false;
- RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP);
+ RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP);
if (!isSPVFP)
Binary |= RegM;
else {
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