[llvm-commits] [llvm] r76401 - in /llvm/trunk/lib/Target/ARM: README-Thumb.txt Thumb1RegisterInfo.cpp

[Evan Cheng]

Author: evancheng
Date: Mon Jul 20 01:59:32 2009
New Revision: 76401

URL: http://llvm.org/viewvc/llvm-project?rev=76401&view=rev
Log:
Fix PR4567. Thumb1 target was using the wrong instruction to handle sp = sub fp, #c.

Modified:
    llvm/trunk/lib/Target/ARM/README-Thumb.txt
    llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/README-Thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/README-Thumb.txt?rev=76401&r1=76400&r2=76401&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/README-Thumb.txt (original)
+++ llvm/trunk/lib/Target/ARM/README-Thumb.txt Mon Jul 20 01:59:32 2009
@@ -244,3 +244,7 @@
 Make use of hi register variants of cmp: tCMPhir / tCMPZhir.
 
 //===---------------------------------------------------------------------===//
+
+Thumb1 immediate field sometimes keep pre-scaled values. See
+Thumb1RegisterInfo::eliminateFrameIndex. This is inconsistent from ARM and
+Thumb2.

Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=76401&r1=76400&r2=76401&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Mon Jul 20 01:59:32 2009
@@ -231,8 +231,16 @@
     if (DestReg != BaseReg)
       DstNotEqBase = true;
     NumBits = 8;
-    Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
-    NeedPred = NeedCC = true;
+    if (DestReg == ARM::SP) {
+      Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
+      assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
+      NumBits = 7;
+      Scale = 4;
+    } else {
+      Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
+      NumBits = 8;
+      NeedPred = NeedCC = true;
+    }
     isTwoAddr = true;
   }
 
@@ -447,7 +455,7 @@
         removeOperands(MI, i);
         MachineInstrBuilder MIB(&MI);
         AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
-                       .addImm(Offset/Scale));
+                       .addImm(Offset / Scale));
       } else {
         MI.getOperand(i).ChangeToRegister(FrameReg, false);
         MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);