[llvm-commits] [llvm] r76105 - /llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
Jakob Stoklund Olesen
stoklund at 2pi.dk
Thu Jul 16 14:24:13 PDT 2009
Author: stoklund
Date: Thu Jul 16 16:24:13 2009
New Revision: 76105
URL: http://llvm.org/viewvc/llvm-project?rev=76105&view=rev
Log:
Silence warning in Linux builds:
X86InstrInfo.cpp:2272: warning: suggest explicit braces to avoid ambiguous 'else'
Modified:
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=76105&r1=76104&r2=76105&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu Jul 16 16:24:13 2009
@@ -2269,15 +2269,16 @@
// x86-32 PIC requires a PIC base register for constant pools.
unsigned PICBase = 0;
- if (TM.getRelocationModel() == Reloc::PIC_)
+ if (TM.getRelocationModel() == Reloc::PIC_) {
if (TM.getSubtarget<X86Subtarget>().is64Bit())
PICBase = X86::RIP;
- else
+ else
// FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF);
// This doesn't work for several reasons.
// 1. GlobalBaseReg may have been spilled.
// 2. It may not be live at MI.
return false;
+ }
// Create a v4i32 constant-pool entry.
MachineConstantPool &MCP = *MF.getConstantPool();
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