[llvm-commits] [llvm] r76101 - in /llvm/trunk: lib/CodeGen/MachineInstr.cpp test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll

[Jakob Stoklund Olesen]

Author: stoklund
Date: Thu Jul 16 15:58:34 2009
New Revision: 76101

URL: http://llvm.org/viewvc/llvm-project?rev=76101&view=rev
Log:
Teach MachineInstr::isRegTiedToDefOperand() to correctly parse inline asm operands.

The inline asm operands must be parsed from the first flag, you cannot assume
that an immediate operand preceeding a register use operand is the flag.
PowerPC "m" operands are represented as (flag, imm, reg) triples.
isRegTiedToDefOperand() would incorrectly interpret the imm as the flag.

Added:
    llvm/trunk/test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll
Modified:
    llvm/trunk/lib/CodeGen/MachineInstr.cpp

Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=76101&r1=76100&r2=76101&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Thu Jul 16 15:58:34 2009
@@ -783,16 +783,20 @@
     const MachineOperand &MO = getOperand(UseOpIdx);
     if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
       return false;
-    int FlagIdx = UseOpIdx - 1;
-    if (FlagIdx < 1)
-      return false;
-    while (!getOperand(FlagIdx).isImm()) {
-      if (--FlagIdx == 0)
-        return false;
+
+    // Find the flag operand corresponding to UseOpIdx
+    unsigned FlagIdx, NumOps=0;
+    for (FlagIdx = 1; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
+      const MachineOperand &UFMO = getOperand(FlagIdx);
+      assert(UFMO.isImm() && "Expecting flag operand on inline asm");
+      NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm());
+      assert(NumOps < getNumOperands() && "Invalid inline asm flag");
+      if (UseOpIdx < FlagIdx+NumOps+1)
+        break;
     }
-    const MachineOperand &UFMO = getOperand(FlagIdx);
-    if (FlagIdx + InlineAsm::getNumOperandRegisters(UFMO.getImm()) < UseOpIdx)
+    if (FlagIdx >= UseOpIdx)
       return false;
+    const MachineOperand &UFMO = getOperand(FlagIdx);
     unsigned DefNo;
     if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
       if (!DefOpIdx)

Added: llvm/trunk/test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll?rev=76101&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll Thu Jul 16 15:58:34 2009
@@ -0,0 +1,16 @@
+; RUN: llvm-as < %s | llc -march=ppc32 -verify-machineinstrs
+
+; Machine code verifier will call isRegTiedToDefOperand() on /all/ register use
+; operands.  We must make sure that the operand flag is found correctly.
+
+; This test case is actually not specific to PowerPC, but the (imm, reg) format
+; of PowerPC "m" operands trigger this bug.
+
+define void @memory_asm_operand(i32 %a) {
+  ; "m" operand will be represented as:
+  ; INLINEASM <es:fake $0>, 10, %R2, 20, -4, %R1
+  ; It is difficult to find the flag operand (20) when starting from %R1
+  call i32 asm "lbzx $0, $1", "=r,m" (i32 %a)
+  ret void
+}
+