[llvm-commits] [llvm] r76027 - in /llvm/trunk/lib/Target/SystemZ: SystemZISelLowering.cpp SystemZInstrFP.td
Anton Korobeynikov
asl at math.spbu.ru
Thu Jul 16 07:22:30 PDT 2009
Author: asl
Date: Thu Jul 16 09:22:30 2009
New Revision: 76027
URL: http://llvm.org/viewvc/llvm-project?rev=76027&view=rev
Log:
Add proper PWS impdef's
Modified:
llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/trunk/lib/Target/SystemZ/SystemZInstrFP.td
Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=76027&r1=76026&r2=76027&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp Thu Jul 16 09:22:30 2009
@@ -68,6 +68,7 @@
setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Promote);
setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Promote);
setLoadExtAction(ISD::EXTLOAD, MVT::f32, Promote);
+
setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Promote);
setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Promote);
setLoadExtAction(ISD::EXTLOAD, MVT::f64, Promote);
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrFP.td?rev=76027&r1=76026&r2=76027&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrFP.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrFP.td Thu Jul 16 09:22:30 2009
@@ -69,53 +69,67 @@
// Arithmetic Instructions
-
let isTwoAddress = 1 in {
+let Defs = [PSW] in {
+
def FNEG32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
"lcebr\t{$dst}",
- [(set FP32:$dst, (fneg FP32:$src))]>;
+ [(set FP32:$dst, (fneg FP32:$src)),
+ (implicit PSW)]>;
def FNEG64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
"lcdbr\t{$dst}",
- [(set FP64:$dst, (fneg FP64:$src))]>;
+ [(set FP64:$dst, (fneg FP64:$src)),
+ (implicit PSW)]>;
// FIXME: Add peephole for fneg(fabs) => load negative
def FABS32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
"lpebr\t{$dst}",
- [(set FP32:$dst, (fabs FP32:$src))]>;
+ [(set FP32:$dst, (fabs FP32:$src)),
+ (implicit PSW)]>;
def FABS64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
"lpdbr\t{$dst}",
- [(set FP64:$dst, (fabs FP64:$src))]>;
+ [(set FP64:$dst, (fabs FP64:$src)),
+ (implicit PSW)]>;
let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
def FADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
"aebr\t{$dst, $src2}",
- [(set FP32:$dst, (fadd FP32:$src1, FP32:$src2))]>;
+ [(set FP32:$dst, (fadd FP32:$src1, FP32:$src2)),
+ (implicit PSW)]>;
def FADD64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
"adbr\t{$dst, $src2}",
- [(set FP64:$dst, (fadd FP64:$src1, FP64:$src2))]>;
+ [(set FP64:$dst, (fadd FP64:$src1, FP64:$src2)),
+ (implicit PSW)]>;
}
def FADD32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
"aeb\t{$dst, $src2}",
- [(set FP32:$dst, (fadd FP32:$src1, (load rriaddr:$src2)))]>;
+ [(set FP32:$dst, (fadd FP32:$src1, (load rriaddr:$src2))),
+ (implicit PSW)]>;
def FADD64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
"adb\t{$dst, $src2}",
- [(set FP64:$dst, (fadd FP64:$src1, (load rriaddr:$src2)))]>;
+ [(set FP64:$dst, (fadd FP64:$src1, (load rriaddr:$src2))),
+ (implicit PSW)]>;
def FSUB32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
"sebr\t{$dst, $src2}",
- [(set FP32:$dst, (fsub FP32:$src1, FP32:$src2))]>;
+ [(set FP32:$dst, (fsub FP32:$src1, FP32:$src2)),
+ (implicit PSW)]>;
def FSUB64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
"sdbr\t{$dst, $src2}",
- [(set FP64:$dst, (fsub FP64:$src1, FP64:$src2))]>;
+ [(set FP64:$dst, (fsub FP64:$src1, FP64:$src2)),
+ (implicit PSW)]>;
def FSUB32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
"seb\t{$dst, $src2}",
- [(set FP32:$dst, (fsub FP32:$src1, (load rriaddr:$src2)))]>;
+ [(set FP32:$dst, (fsub FP32:$src1, (load rriaddr:$src2))),
+ (implicit PSW)]>;
def FSUB64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
"sdb\t{$dst, $src2}",
- [(set FP64:$dst, (fsub FP64:$src1, (load rriaddr:$src2)))]>;
+ [(set FP64:$dst, (fsub FP64:$src1, (load rriaddr:$src2))),
+ (implicit PSW)]>;
+} // Defs = [PSW]
let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y
def FMUL32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
@@ -153,33 +167,48 @@
"ledbr\t{$dst, $src}",
[(set FP32:$dst, (fround FP64:$src))]>;
+// FIXME: memory variant
+def FEXT32r64 : Pseudo<(outs FP64:$dst), (ins FP32:$src),
+ "ldebr\t{$dst, $src}",
+ [(set FP64:$dst, (fextend FP32:$src))]>;
+
+let Defs = [PSW] in {
def FCONVFP32 : Pseudo<(outs FP32:$dst), (ins GR32:$src),
"cefbr\t{$dst, $src}",
- [(set FP32:$dst, (sint_to_fp GR32:$src))]>;
+ [(set FP32:$dst, (sint_to_fp GR32:$src)),
+ (implicit PSW)]>;
def FCONVFP32r64: Pseudo<(outs FP32:$dst), (ins GR64:$src),
"cegbr\t{$dst, $src}",
- [(set FP32:$dst, (sint_to_fp GR64:$src))]>;
+ [(set FP32:$dst, (sint_to_fp GR64:$src)),
+ (implicit PSW)]>;
def FCONVFP64r32: Pseudo<(outs FP64:$dst), (ins GR32:$src),
"cdfbr\t{$dst, $src}",
- [(set FP64:$dst, (sint_to_fp GR32:$src))]>;
+ [(set FP64:$dst, (sint_to_fp GR32:$src)),
+ (implicit PSW)]>;
def FCONVFP64 : Pseudo<(outs FP64:$dst), (ins GR64:$src),
"cdgbr\t{$dst, $src}",
- [(set FP64:$dst, (sint_to_fp GR64:$src))]>;
+ [(set FP64:$dst, (sint_to_fp GR64:$src)),
+ (implicit PSW)]>;
def FCONVGR32 : Pseudo<(outs GR32:$dst), (ins FP32:$src),
"cfebr\t{$dst, $src}",
- [(set GR32:$dst, (fp_to_sint FP32:$src))]>;
+ [(set GR32:$dst, (fp_to_sint FP32:$src)),
+ (implicit PSW)]>;
def FCONVGR32r64: Pseudo<(outs GR32:$dst), (ins FP64:$src),
"cgebr\t{$dst, $src}",
- [(set GR32:$dst, (fp_to_sint FP64:$src))]>;
+ [(set GR32:$dst, (fp_to_sint FP64:$src)),
+ (implicit PSW)]>;
def FCONVGR64r32: Pseudo<(outs GR64:$dst), (ins FP32:$src),
"cfdbr\t{$dst, $src}",
- [(set GR64:$dst, (fp_to_sint FP32:$src))]>;
+ [(set GR64:$dst, (fp_to_sint FP32:$src)),
+ (implicit PSW)]>;
def FCONVGR64 : Pseudo<(outs GR64:$dst), (ins FP64:$src),
"cgdbr\t{$dst, $src}",
- [(set GR64:$dst, (fp_to_sint FP64:$src))]>;
+ [(set GR64:$dst, (fp_to_sint FP64:$src)),
+ (implicit PSW)]>;
+} // Defs = [PSW]
//===----------------------------------------------------------------------===//
// Test instructions (like AND but do not produce any result)
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