[llvm-commits] [llvm] r76004 - in /llvm/trunk/lib/Target/SystemZ: SystemZISelDAGToDAG.cpp SystemZInstrInfo.td
Anton Korobeynikov
asl at math.spbu.ru
Thu Jul 16 07:14:56 PDT 2009
Author: asl
Date: Thu Jul 16 09:14:54 2009
New Revision: 76004
URL: http://llvm.org/viewvc/llvm-project?rev=76004&view=rev
Log:
Remove redundand register move
Modified:
llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp?rev=76004&r1=76003&r2=76004&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp Thu Jul 16 09:14:54 2009
@@ -645,7 +645,7 @@
default: assert(0 && "Unsupported VT!");
case MVT::i32:
Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m;
- ClrOpc = SystemZ::MOV32ri16;
+ ClrOpc = SystemZ::MOV64Pr0_even;
ResVT = MVT::v2i32;
break;
case MVT::i64:
@@ -669,15 +669,8 @@
CurDAG->getTargetConstant(subreg_odd, MVT::i32));
// Zero out even subreg, if needed
- if (ClrOpc) {
- SDNode * ZeroHi = CurDAG->getTargetNode(SystemZ::MOV32ri16, dl, NVT,
- CurDAG->getTargetConstant(0, MVT::i32));
- Dividend =
- CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
- SDValue(Dividend, 0),
- SDValue(ZeroHi, 0),
- CurDAG->getTargetConstant(subreg_even, MVT::i32));
- }
+ if (ClrOpc)
+ Dividend = CurDAG->getTargetNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0));
SDNode *Result;
SDValue DivVal = SDValue(Dividend, 0);
@@ -736,12 +729,12 @@
default: assert(0 && "Unsupported VT!");
case MVT::i32:
Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m;
- ClrOpc = SystemZ::MOV32ri16;
+ ClrOpc = SystemZ::MOV64Pr0_even;
ResVT = MVT::v2i32;
break;
case MVT::i64:
Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m;
- ClrOpc = SystemZ::MOV64ri16;
+ ClrOpc = SystemZ::MOV128r0_even;
ResVT = MVT::v2i64;
break;
}
@@ -760,15 +753,8 @@
SDValue(Tmp, 0), SDValue(Dividend, 0),
CurDAG->getTargetConstant(subreg_odd, MVT::i32));
- // Zero out even subreg, if needed
- SDNode * ZeroHi = CurDAG->getTargetNode(ClrOpc, dl, NVT,
- CurDAG->getTargetConstant(0,
- MVT::i32));
- Dividend =
- CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
- SDValue(Dividend, 0),
- SDValue(ZeroHi, 0),
- CurDAG->getTargetConstant(subreg_even, MVT::i32));
+ // Zero out even subreg
+ Dividend = CurDAG->getTargetNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0));
SDValue DivVal = SDValue(Dividend, 0);
SDNode *Result;
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td?rev=76004&r1=76003&r2=76004&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td Thu Jul 16 09:14:54 2009
@@ -370,6 +370,14 @@
"lmg\t{$from, $to, $dst}",
[]>;
+let isReMaterializable = 1, isAsCheapAsAMove = 1, isTwoAddress = 1 in {
+def MOV64Pr0_even : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
+ "lhi\t${dst:subreg_even}, 0",
+ []>;
+def MOV128r0_even : Pseudo<(outs GR128:$dst), (ins GR128:$src),
+ "lghi\t${dst:subreg_even}, 0",
+ []>;
+}
//===----------------------------------------------------------------------===//
// Arithmetic Instructions
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