[llvm-commits] [llvm] r75931 - in /llvm/trunk: lib/Target/SystemZ/SystemZISelDAGToDAG.cpp lib/Target/SystemZ/SystemZInstrInfo.td test/CodeGen/SystemZ/05-MemRegStores.ll
Anton Korobeynikov
asl at math.spbu.ru
Thu Jul 16 06:45:01 PDT 2009
Author: asl
Date: Thu Jul 16 08:45:00 2009
New Revision: 75931
URL: http://llvm.org/viewvc/llvm-project?rev=75931&view=rev
Log:
Add stores and truncstores
Added:
llvm/trunk/test/CodeGen/SystemZ/05-MemRegStores.ll
Modified:
llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp?rev=75931&r1=75930&r2=75931&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp Thu Jul 16 08:45:00 2009
@@ -52,18 +52,19 @@
}
void dump() {
- cerr << "SystemZRRIAddressMode " << this << "\n";
+ cerr << "SystemZRRIAddressMode " << this << '\n';
if (BaseType == RegBase) {
cerr << "Base.Reg ";
if (Base.Reg.getNode() != 0) Base.Reg.getNode()->dump();
else cerr << "nul";
+ cerr << '\n';
} else {
- cerr << " Base.FrameIndex " << Base.FrameIndex << "\n";
+ cerr << " Base.FrameIndex " << Base.FrameIndex << '\n';
}
cerr << "IndexReg ";
if (IndexReg.getNode() != 0) IndexReg.getNode()->dump();
else cerr << "nul";
- cerr << " Disp " << Disp << "\n";
+ cerr << " Disp " << Disp << '\n';
}
};
}
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td?rev=75931&r1=75930&r2=75931&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td Thu Jul 16 08:45:00 2009
@@ -219,6 +219,11 @@
}
+def MOV64mr : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
+ "stg\t{$src, $dst}",
+ [(store GR64:$src, rriaddr:$dst)]>;
+
+// extloads
def MOVSX64rm8 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
"lgb\t{$dst, $src}",
[(set GR64:$dst, (sextloadi64i8 rriaddr:$src))]>;
@@ -239,6 +244,27 @@
"llgf\t{$dst, $src}",
[(set GR64:$dst, (zextloadi64i32 rriaddr:$src))]>;
+// truncstores
+// FIXME: Implement 12-bit displacement stuff someday
+def MOV32m8r : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
+ "stcy\t{$src, $dst}",
+ [(truncstorei8 GR32:$src, rriaddr:$dst)]>;
+
+def MOV32m16r : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
+ "sthy\t{$src, $dst}",
+ [(truncstorei16 GR32:$src, rriaddr:$dst)]>;
+
+def MOV64m8r : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
+ "stcy\t{$src, $dst}",
+ [(truncstorei8 GR64:$src, rriaddr:$dst)]>;
+
+def MOV64m16r : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
+ "sthy\t{$src, $dst}",
+ [(truncstorei16 GR64:$src, rriaddr:$dst)]>;
+
+def MOV64m32r : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
+ "sty\t{$src, $dst}",
+ [(truncstorei32 GR64:$src, rriaddr:$dst)]>;
//===----------------------------------------------------------------------===//
// Arithmetic Instructions
Added: llvm/trunk/test/CodeGen/SystemZ/05-MemRegStores.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/05-MemRegStores.ll?rev=75931&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/05-MemRegStores.ll (added)
+++ llvm/trunk/test/CodeGen/SystemZ/05-MemRegStores.ll Thu Jul 16 08:45:00 2009
@@ -0,0 +1,67 @@
+; RUN: llvm-as < %s | llc | not grep aghi
+; RUN: llvm-as < %s | llc | grep stg | count 1
+; RUN: llvm-as < %s | llc | grep sty | count 2
+; RUN: llvm-as < %s | llc | grep sthy | count 2
+; RUN: llvm-as < %s | llc | grep stcy | count 2
+
+target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
+target triple = "s390x-unknown-linux-gnu"
+
+define void @foo1(i64* nocapture %a, i64 %idx, i64 %val) nounwind {
+entry:
+ %add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr2 = getelementptr i64* %a, i64 %add.ptr.sum ; <i64*> [#uses=1]
+ store i64 %val, i64* %add.ptr2
+ ret void
+}
+
+define void @foo2(i32* nocapture %a, i64 %idx, i32 %val) nounwind {
+entry:
+ %add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr2 = getelementptr i32* %a, i64 %add.ptr.sum ; <i32*> [#uses=1]
+ store i32 %val, i32* %add.ptr2
+ ret void
+}
+
+define void @foo3(i16* nocapture %a, i64 %idx, i16 zeroext %val) nounwind {
+entry:
+ %add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr2 = getelementptr i16* %a, i64 %add.ptr.sum ; <i16*> [#uses=1]
+ store i16 %val, i16* %add.ptr2
+ ret void
+}
+
+define void @foo4(i8* nocapture %a, i64 %idx, i8 zeroext %val) nounwind {
+entry:
+ %add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr2 = getelementptr i8* %a, i64 %add.ptr.sum ; <i8*> [#uses=1]
+ store i8 %val, i8* %add.ptr2
+ ret void
+}
+
+define void @foo5(i8* nocapture %a, i64 %idx, i64 %val) nounwind {
+entry:
+ %add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr2 = getelementptr i8* %a, i64 %add.ptr.sum ; <i8*> [#uses=1]
+ %conv = trunc i64 %val to i8 ; <i8> [#uses=1]
+ store i8 %conv, i8* %add.ptr2
+ ret void
+}
+
+define void @foo6(i16* nocapture %a, i64 %idx, i64 %val) nounwind {
+entry:
+ %add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr2 = getelementptr i16* %a, i64 %add.ptr.sum ; <i16*> [#uses=1]
+ %conv = trunc i64 %val to i16 ; <i16> [#uses=1]
+ store i16 %conv, i16* %add.ptr2
+ ret void
+}
+
+define void @foo7(i32* nocapture %a, i64 %idx, i64 %val) nounwind {
+entry:
+ %add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr2 = getelementptr i32* %a, i64 %add.ptr.sum ; <i32*> [#uses=1]
+ %conv = trunc i64 %val to i32 ; <i32> [#uses=1]
+ store i32 %conv, i32* %add.ptr2
+ ret void
+}
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