[llvm-commits] [PATCH] MSIL backend: Fix incorrect value after sign extension

[Anton Korobeynikov]

Hi, Artur

> This patch adds extra sign extension to the same bit width before int
> sign extension to another bit width. This is needed to get correct
> singed value.
Applied, thanks!

-- 
With best regards, Anton Korobeynikov.

Faculty of Mathematics & Mechanics, Saint Petersburg State University.