[llvm-commits] [llvm] r75308 - in /llvm/trunk: include/llvm/CodeGen/ValueTypes.h include/llvm/CodeGen/ValueTypes.td lib/VMCore/ValueTypes.cpp utils/TableGen/CodeGenTarget.cpp

[Anton Korobeynikov]

Hi, Chris

> I don't know about much about neon, but if you are using this to model
> load/store with multiple registers, there are probably better ways to
> go.  What set of operations does neon natively support on these
> datatypes?
I also faced with similar problem and it seems it's a deficiency of
current regalloc. There is common situation that some instructions
operate on regpairs. Currently there is no way to say stuff like
"allocate this argument from odd-numbered register" or "keep this two
operands in two consecutive registers".

If the instruction accepts only certain regpair (e.g. x86's div /
idiv) when we can go into hacky way and expand stuff by hands (another
example is ARM argument lowering). Otherwise I don't see any other way
except defining virtual regclass holding register pairs with all
needed reg alias sets, etc. This regclass should be special though
since the type it's holding is not 'native' type legalizer should
expand all operations with such type (We already have special case
during type legalization of ppcf128 - it behaves exactly this way).

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University