[llvm-commits] [llvm] r75408 - in /llvm/trunk/lib/Target/X86: X86ISelDAGToDAG.cpp X86Instr64bit.td X86InstrInfo.cpp
Bill Wendling
isanbard at gmail.com
Sat Jul 11 19:50:23 PDT 2009
Hi Chris,
It appears that this broke the Apple-style builds:
x86_64-apple-darwin10-gcc -c -g -O2 -DIN_GCC -W -Wall -Wwrite-strings -
Wstrict-prototypes -Wmissing-prototypes -pedantic -Wno-long-long -Wno-
variadic-macros -Wno-overlength-strings -Wold-style-definition -
Wmissing-format-attribute -mdynamic-no-pic -DHAVE_CONFIG_H -I. -I. -I/
Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/
build/llvmgcc42.roots/llvmgcc42~obj/src/gcc -I/Volumes/Sandbox/
Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/
llvmgcc42.roots/llvmgcc42~obj/src/gcc/. -I/Volumes/Sandbox/Buildbot/
llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/llvmgcc42.roots/
llvmgcc42~obj/src/gcc/../include -I./../intl -I/Volumes/Sandbox/
Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/
llvmgcc42.roots/llvmgcc42~obj/src/gcc/../libcpp/include -I/Volumes/
Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin10-selfhost/build/
llvmgcc42.roots/llvmgcc42~obj/src/gcc/../libdecnumber -I../
libdecnumber -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-
darwin10-selfhost/build/llvmCore.roots/llvmCore~dst/Developer/usr/
local/include -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-
darwin10-selfhost/build/llvmCore.roots/llvmCore~obj/src/include -
DENABLE_LLVM -I/Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-
darwin10-selfhost/build/llvmCore.roots/llvmCore~dst/Developer/usr/
local/include -D_DEBUG -D_GNU_SOURCE -D__STDC_LIMIT_MACROS -
D__STDC_CONSTANT_MACROS -DLLVM_VERSION_INFO='"9999"' -
DBUILD_LLVM_APPLE_STYLE /Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-
x86_64-darwin10-selfhost/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/
tree-ssa-alias.c -o tree-ssa-alias.o /var/tmp//ccJQ2JBT.s:
4134:Incorrect register `%rcx' used with `l' suffix make[2]: *** [tree-
ssa-live.o] Error 1 make[2]: *** Waiting for unfinished jobs....
http://smooshlab.apple.com:8010/builders/llvm-gcc-x86_64-darwin10-selfhost/builds/611/steps/shell/logs/stdio
I reverted it for now. Could you look into it?
-bw
On Jul 11, 2009, at 5:47 PM, Chris Lattner wrote:
> Author: lattner
> Date: Sat Jul 11 19:47:55 2009
> New Revision: 75408
>
> URL: http://llvm.org/viewvc/llvm-project?rev=75408&view=rev
> Log:
> eliminate MOV64r0 in favor of a Pat<> pattern. This is only
> nontrivial because
> the div lowering code explicitly references it.
>
> Modified:
> llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
> llvm/trunk/lib/Target/X86/X86Instr64bit.td
> llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=75408&r1=75407&r2=75408&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Sat Jul 11
> 19:47:55 2009
> @@ -1604,7 +1604,7 @@
> break;
> case MVT::i64:
> LoReg = X86::RAX; HiReg = X86::RDX;
> - ClrOpcode = X86::MOV64r0;
> + ClrOpcode = ~0U; // NOT USED.
> SExtOpcode = X86::CQO;
> break;
> }
> @@ -1643,8 +1643,26 @@
> SDValue(CurDAG->getTargetNode(SExtOpcode, dl, MVT::Flag,
> InFlag),0);
> } else {
> // Zero out the high part, effectively zero extending the
> input.
> - SDValue ClrNode = SDValue(CurDAG-
> >getTargetNode(ClrOpcode, dl, NVT),
> - 0);
> + SDValue ClrNode;
> +
> + if (NVT.getSimpleVT() == MVT::i64) {
> + ClrNode = SDValue(CurDAG->getTargetNode(X86::MOV32r0,
> dl, MVT::i32),
> + 0);
> + // We just did a 32-bit clear, insert it into a 64-bit
> register to
> + // clear the whole 64-bit reg.
> + SDValue Undef =
> + SDValue(CurDAG-
> >getTargetNode(TargetInstrInfo::IMPLICIT_DEF,
> + dl, MVT::i64), 0);
> + SDValue SubRegNo =
> + CurDAG->getTargetConstant(X86::SUBREG_32BIT, MVT::i32);
> + ClrNode =
> + SDValue(CurDAG-
> >getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl,
> + MVT::i64, Undef,
> ClrNode, SubRegNo),
> + 0);
> + } else {
> + ClrNode = SDValue(CurDAG->getTargetNode(ClrOpcode, dl,
> NVT), 0);
> + }
> +
> InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
> HiReg,
> ClrNode, InFlag).getValue(1);
> }
>
> Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=75408&r1=75407&r2=75408&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
> +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Sat Jul 11 19:47:55
> 2009
> @@ -1305,14 +1305,12 @@
> // Alias instructions that map movr0 to xor. Use xorl instead of
> xorq; it's
> // equivalent due to implicit zero-extending, and it sometimes has a
> smaller
> // encoding.
> -// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
> -// FIXME: AddedComplexity gives MOV64r0 a higher priority than
> MOV64ri32. Remove
> +// FIXME: AddedComplexity gives this a higher priority than
> MOV64ri32. Remove
> // when we have a better way to specify isel priority.
> -let Defs = [EFLAGS], AddedComplexity = 1,
> - isReMaterializable = 1, isAsCheapAsAMove = 1 in
> -def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins),
> - "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
> - [(set GR64:$dst, 0)]>;
> +let AddedComplexity = 1 in
> +def : Pat<(i64 0),
> + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV32r0),
> x86_subreg_32bit)>;
> +
>
> // Materialize i64 constant where top 32-bits are zero.
> let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove =
> 1 in
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=75408&r1=75407&r2=75408&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sat Jul 11 19:47:55
> 2009
> @@ -929,8 +929,7 @@
> default: break;
> case X86::MOV8r0:
> case X86::MOV16r0:
> - case X86::MOV32r0:
> - case X86::MOV64r0: {
> + case X86::MOV32r0: {
> if (!isSafeToClobberEFLAGS(MBB, I)) {
> unsigned Opc = 0;
> switch (Orig->getOpcode()) {
> @@ -938,7 +937,6 @@
> case X86::MOV8r0: Opc = X86::MOV8ri; break;
> case X86::MOV16r0: Opc = X86::MOV16ri; break;
> case X86::MOV32r0: Opc = X86::MOV32ri; break;
> - case X86::MOV64r0: Opc = X86::MOV64ri32; break;
> }
> BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0);
> Emitted = true;
> @@ -2165,8 +2163,6 @@
> NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
> else if (MI->getOpcode() == X86::MOV32r0)
> NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
> - else if (MI->getOpcode() == X86::MOV64r0)
> - NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
> else if (MI->getOpcode() == X86::MOV8r0)
> NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
> if (NewMI)
> @@ -2365,10 +2361,9 @@
> OpcodeTablePtr = &RegOp2MemOpTable2Addr;
> } else if (OpNum == 0) { // If operand 0
> switch (Opc) {
> + case X86::MOV8r0:
> case X86::MOV16r0:
> case X86::MOV32r0:
> - case X86::MOV64r0:
> - case X86::MOV8r0:
> return true;
> default: break;
> }
>
>
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