[llvm-commits] [llvm] r75361 - in /llvm/trunk: lib/Target/ARM/Thumb2ITBlockPass.cpp test/CodeGen/Thumb2/thumb2-bcc.ll

[Evan Cheng]

Author: evancheng
Date: Sat Jul 11 02:26:20 2009
New Revision: 75361

URL: http://llvm.org/viewvc/llvm-project?rev=75361&view=rev
Log:
Don't put IT instruction before conditional branches.

Added:
    llvm/trunk/test/CodeGen/Thumb2/thumb2-bcc.ll
Modified:
    llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp

Modified: llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp?rev=75361&r1=75360&r2=75361&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp Sat Jul 11 02:26:20 2009
@@ -9,8 +9,8 @@
 
 #define DEBUG_TYPE "thumb2-it"
 #include "ARM.h"
-#include "ARMInstrInfo.h"
 #include "ARMMachineFunctionInfo.h"
+#include "Thumb2InstrInfo.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
@@ -25,7 +25,7 @@
     static char ID;
     Thumb2ITBlockPass() : MachineFunctionPass(&ID) {}
 
-    const ARMBaseInstrInfo *TII;
+    const Thumb2InstrInfo *TII;
     ARMFunctionInfo *AFI;
 
     virtual bool runOnMachineFunction(MachineFunction &Fn);
@@ -40,13 +40,21 @@
   char Thumb2ITBlockPass::ID = 0;
 }
 
+ARMCC::CondCodes getPredicate(const MachineInstr *MI,
+                              const Thumb2InstrInfo *TII) {
+  unsigned Opc = MI->getOpcode();
+  if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
+    return ARMCC::AL;
+  return TII->getPredicate(MI);
+}
+
 bool Thumb2ITBlockPass::InsertITBlocks(MachineBasicBlock &MBB) {
   bool Modified = false;
 
   MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
   while (MBBI != E) {
     MachineInstr *MI = &*MBBI;
-    ARMCC::CondCodes CC = TII->getPredicate(MI);
+    ARMCC::CondCodes CC = getPredicate(MI, TII);
     if (CC == ARMCC::AL) {
       ++MBBI;
       continue;
@@ -64,7 +72,7 @@
     ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
     unsigned Mask = 0x8;
     while (MBBI != E || (Mask & 1)) {
-      ARMCC::CondCodes NCC = TII->getPredicate(&*MBBI);
+      ARMCC::CondCodes NCC = getPredicate(&*MBBI, TII);
       if (NCC == CC) {
         Mask >>= 1;
         Mask |= 0x8;
@@ -86,7 +94,7 @@
 bool Thumb2ITBlockPass::runOnMachineFunction(MachineFunction &Fn) {
   const TargetMachine &TM = Fn.getTarget();
   AFI = Fn.getInfo<ARMFunctionInfo>();
-  TII = static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo());
+  TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo());
 
   if (!AFI->isThumbFunction())
     return false;

Added: llvm/trunk/test/CodeGen/Thumb2/thumb2-bcc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-bcc.ll?rev=75361&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/thumb2-bcc.ll (added)
+++ llvm/trunk/test/CodeGen/Thumb2/thumb2-bcc.ll Sat Jul 11 02:26:20 2009
@@ -0,0 +1,19 @@
+; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | not grep it
+
+define i32 @t1(i32 %a, i32 %b, i32 %c) {
+; CHECK: t1
+; CHECK: beq
+	%tmp2 = icmp eq i32 %a, 0
+	br i1 %tmp2, label %cond_false, label %cond_true
+
+cond_true:
+	%tmp5 = add i32 %b, 1
+        %tmp6 = and i32 %tmp5, %c
+	ret i32 %tmp6
+
+cond_false:
+	%tmp7 = add i32 %b, -1
+        %tmp8 = xor i32 %tmp7, %c
+	ret i32 %tmp8
+}