[llvm-commits] [llvm] r74964 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp test/CodeGen/X86/vec_compare.ll
Eli Friedman
eli.friedman at gmail.com
Tue Jul 7 21:10:07 PDT 2009
On Tue, Jul 7, 2009 at 9:09 PM, Eli Friedman<eli.friedman at gmail.com> wrote:
> On Tue, Jul 7, 2009 at 7:38 PM, Eli Friedman<eli.friedman at gmail.com> wrote:
>> On Tue, Jul 7, 2009 at 7:16 PM, Eli Friedman<eli.friedman at gmail.com> wrote:
>>> On Tue, Jul 7, 2009 at 6:29 PM, Dan Gohman<gohman at apple.com> wrote:
>>>> EXTRACT_SUBVECTOR is normally used to extract a legal value from
>>>> an illegal one. The code above does the opposite, extracting a
>>>> potentially illegal value from a legal one.
>>>
>>> As far as I can tell, we support both cases properly in type
>>> legalization; what specific case breaks?
>>
>> Mmm, nevermind, you're talking about something like the following?
>>
>> define void @test2(<2 x i32> %A, <2 x i32> %B, <2 x i32>* %C) nounwind {
>> %D = icmp sgt <2 x i32> %A, %B
>> %E = zext <2 x i1> %D to <2 x i32>
>> store <2 x i32> %E, <2 x i32>* %C
>> ret void
>> }
>>
>> It's really just falling apart because we don't support various
>> related cases correctly; first, it hits the "Unimp" assert in this
>> patch, and if you just comment it out (which seems like the right
>> thing to do), we hit an assertion because we don't support extracting
>> an i1 from a <2 x i1> in PromoteIntRes_EXTRACT_VECTOR_ELT . Still
>> nothing going wrong with EXTRACT_SUBVECTOR.
>
> Attached partially deals with the issues (enough to get the given
> testcase to compile); it might not be the best approach, though,
> because changing the definition of EXTRACT_VECTOR_ELT has side-effects
> all over the place.
Bleh, accidentally attached the wrong thing.
-Eli
-------------- next part --------------
Index: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (revision 74987)
+++ lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (working copy)
@@ -303,52 +303,10 @@
}
SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
- MVT OldVT = N->getValueType(0);
- SDValue OldVec = N->getOperand(0);
- if (getTypeAction(OldVec.getValueType()) == WidenVector)
- OldVec = GetWidenedVector(N->getOperand(0));
- unsigned OldElts = OldVec.getValueType().getVectorNumElements();
DebugLoc dl = N->getDebugLoc();
-
- if (OldElts == 1) {
- assert(!isTypeLegal(OldVec.getValueType()) &&
- "Legal one-element vector of a type needing promotion!");
- // It is tempting to follow GetScalarizedVector by a call to
- // GetPromotedInteger, but this would be wrong because the
- // scalarized value may not yet have been processed.
- return DAG.getNode(ISD::ANY_EXTEND, dl, TLI.getTypeToTransformTo(OldVT),
- GetScalarizedVector(OldVec));
- }
-
- // Convert to a vector half as long with an element type of twice the width,
- // for example <4 x i16> -> <2 x i32>.
- assert(!(OldElts & 1) && "Odd length vectors not supported!");
- MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
- assert(OldVT.isSimple() && NewVT.isSimple());
-
- SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::getVectorVT(NewVT, OldElts / 2),
- OldVec);
-
- // Extract the element at OldIdx / 2 from the new vector.
- SDValue OldIdx = N->getOperand(1);
- SDValue NewIdx = DAG.getNode(ISD::SRL, dl, OldIdx.getValueType(), OldIdx,
- DAG.getConstant(1, TLI.getPointerTy()));
- SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, NewIdx);
-
- // Select the appropriate half of the element: Lo if OldIdx was even,
- // Hi if it was odd.
- SDValue Lo = Elt;
- SDValue Hi = DAG.getNode(ISD::SRL, dl, NewVT, Elt,
- DAG.getConstant(OldVT.getSizeInBits(),
- TLI.getPointerTy()));
- if (TLI.isBigEndian())
- std::swap(Lo, Hi);
-
- // Extend to the promoted type.
- SDValue Odd = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, OldIdx);
- SDValue Res = DAG.getNode(ISD::SELECT, dl, NewVT, Odd, Hi, Lo);
- return DAG.getNode(ISD::ANY_EXTEND, dl, TLI.getTypeToTransformTo(OldVT), Res);
+ MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
+ N->getOperand(1));
}
SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
Index: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (revision 74987)
+++ lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (working copy)
@@ -330,7 +330,11 @@
/// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
/// index.
SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
- return GetScalarizedVector(N->getOperand(0));
+ SDValue Res = GetScalarizedVector(N->getOperand(0));
+ if (Res.getValueType() != N->getValueType(0))
+ Res = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0),
+ Res);
+ return Res;
}
/// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
@@ -899,7 +903,7 @@
SDValue LL, LH, RL, RH;
switch (getTypeAction(InVT)) {
default: assert(0 && "Unexpected type action!");
- case WidenVector: assert(0 && "Unimp");
+ case WidenVector:
case Legal: {
assert(LoVT == HiVT && "Legal non-power-of-two vector type?");
MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
@@ -1073,7 +1077,8 @@
// Load back the required element.
StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
- return DAG.getLoad(EltVT, dl, Store, StackPtr, SV, 0);
+ return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
+ SV, 0, EltVT);
}
SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
@@ -1925,9 +1930,8 @@
SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
SDValue InOp = GetWidenedVector(N->getOperand(0));
- MVT EltVT = InOp.getValueType().getVectorElementType();
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
- EltVT, InOp, N->getOperand(1));
+ N->getValueType(0), InOp, N->getOperand(1));
}
SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
Index: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (revision 74987)
+++ lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (working copy)
@@ -1522,7 +1522,11 @@
StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
- return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0);
+ if (Op.getValueType().isVector())
+ return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0);
+ else
+ return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
+ NULL, 0, Vec.getValueType().getVectorElementType());
}
SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
Index: include/llvm/CodeGen/SelectionDAGNodes.h
===================================================================
--- include/llvm/CodeGen/SelectionDAGNodes.h (revision 74987)
+++ include/llvm/CodeGen/SelectionDAGNodes.h (working copy)
@@ -303,7 +303,9 @@
INSERT_VECTOR_ELT,
/// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR
- /// identified by the (potentially variable) element number IDX.
+ /// identified by the (potentially variable) element number IDX. If the
+ /// return type is an integer type larger than the element type of the
+ /// vector, the result is extended to the width of the return type.
EXTRACT_VECTOR_ELT,
/// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of
Index: test/CodeGen/X86/2009-07-07-UnrollICmp.ll
===================================================================
--- test/CodeGen/X86/2009-07-07-UnrollICmp.ll (revision 0)
+++ test/CodeGen/X86/2009-07-07-UnrollICmp.ll (revision 0)
@@ -0,0 +1,8 @@
+; RUN: llvm-as < %s | llc -march=x86 -disable-mmx
+
+define void @test2(<2 x i32> %A, <2 x i32> %B, <2 x i32>* %C) nounwind {
+ %D = icmp sgt <2 x i32> %A, %B
+ %E = zext <2 x i1> %D to <2 x i32>
+ store <2 x i32> %E, <2 x i32>* %C
+ ret void
+}
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