[llvm-commits] [llvm] r74641 - /llvm/trunk/lib/Target/ARM/ARMAddressingModes.h

[Bob Wilson]

Author: bwilson
Date: Wed Jul  1 16:22:45 2009
New Revision: 74641

URL: http://llvm.org/viewvc/llvm-project?rev=74641&view=rev
Log:
Fix up a comment: besides the >80col lines, the operation for this
addressing mode is encoded in the second operand, not the third.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAddressingModes.h

Modified: llvm/trunk/lib/Target/ARM/ARMAddressingModes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAddressingModes.h?rev=74641&r1=74640&r2=74641&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAddressingModes.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMAddressingModes.h Wed Jul  1 16:22:45 2009
@@ -459,13 +459,13 @@
   //
   // addrmode5 := reg +/- imm8*4
   //
-  // The first operand is always a Reg.  The third field encodes the operation
-  // in bit 8, the immediate in bits 0-7.
+  // The first operand is always a Reg.  The second operand encodes the
+  // operation in bit 8 and the immediate in bits 0-7.
   //
-  // This can also be used for FP load/store multiple ops. The third field encodes
-  // writeback mode in bit 8, the number of registers (or 2 times the number of
-  // registers for DPR ops) in bits 0-7. In addition, bit 9-11 encodes one of the
-  // following two sub-modes:
+  // This is also used for FP load/store multiple ops. The second operand
+  // encodes the writeback mode in bit 8 and the number of registers (or 2
+  // times the number of registers for DPR ops) in bits 0-7. In addition,
+  // bits 9-11 encode one of the following two sub-modes:
   //
   //    IA - Increment after
   //    DB - Decrement before