[llvm-commits] CVS: llvm-www/pubs/2009-01-ASP-DAC-MemorySimulation.html 2009-01-ASP-DAC-MemorySimulation.pdf pubs.js

Sat Jun 27 01:03:10 PDT 2009

Changes in directory llvm-www/pubs:

2009-01-ASP-DAC-MemorySimulation.html added (r1.1)
2009-01-ASP-DAC-MemorySimulation.pdf added (r1.1)
pubs.js updated: 1.24 -> 1.25
---
Log message:

add "Memory subsystem simulation in software TLM/T models" a second paper
at ASP-DAC'09


---
Diffs of the changes:  (+70 -0)

 2009-01-ASP-DAC-MemorySimulation.html |   62 ++++++++++++++++++++++++++++++++++
 2009-01-ASP-DAC-MemorySimulation.pdf  |    0 
 pubs.js                               |    8 ++++
 3 files changed, 70 insertions(+)


Index: llvm-www/pubs/2009-01-ASP-DAC-MemorySimulation.html
diff -c /dev/null llvm-www/pubs/2009-01-ASP-DAC-MemorySimulation.html:1.1
*** /dev/null	Sat Jun 27 03:01:13 2009

--- llvm-www/pubs/2009-01-ASP-DAC-MemorySimulation.html	Sat Jun 27 03:01:01 2009
***************
*** 0 ****
--- 1,62 ----
+ <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+ <html>
+ <head>
+   <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+   <link rel="stylesheet" href="../llvm.css" type="text/css" media="screen">
+   <title>Memory subsystem simulation in software TLM/T models</title>
+ </head>
+ <body>
+ 
+ 
+ <div class="pub_title">
+   Memory subsystem simulation in software TLM/T models
+ </div>
+ <div class="pub_author">
+   Eric Cheung, Harry Hsieh, and Felice Balarin
+ </div>
+ 
+ <h2>Abstract:</h2>
+ <blockquote>
+ Design of Multiprocessor System-on-a-Chips requires efficient and accurate simulation of every component. Since the memory subsystem accounts for up to 50% of the performance and energy expenditures, it has to be considered in system-level design space exploration. In this paper, we present a novel technique to simulate memory accesses in software TLM/T models. We use a compiler to automatically expose all memory accesses in software and annotate them onto efficient TLM/T models. A reverse address map provides target memory addresses for accurate cache and memory simulation. Simulating at more than 10MHz, our models allow realistic architectural design space explorations on memory subsystems. We demonstrate our approach with a design exploration case study of an industrial-strength MPEG-2 decoder.
+ </blockquote>
+ 
+ <h2>Published:</h2>
+ <blockquote>
+   "Memory subsystem simulation in software TLM/T models"<br>
+   Eric Cheung, Harry Hsieh, and Felice Balarin<br>
+   <i>Proceedings of the 14th <a href="http://www.aspdac.com">Asia South Pacific Design Automation Conference (ASP-DAC'09)</a></i>, Yokohama, Japan, January 09
+ </blockquote>
+ 
+ <h2>Bibtex:</h2>
+ <pre>
+ @inproceedings{1509814,
+  author = {Cheung, Eric and Hsieh, Harry and Balarin, Felice},
+  title = {Memory subsystem simulation in software TLM/T models},
+  booktitle = {ASP-DAC '09: Proceedings of the 2009 Conference on Asia and South Pacific Design Automation},
+  year = {2009},
+  isbn = {978-1-4244-2748-2},
+  pages = {811--816},
+  location = {Yokohama, Japan},
+  publisher = {IEEE Press},
+  address = {Piscataway, NJ, USA},
+  }
+ </pre>
+ 
+ 
+ <h2>Download:</h2>
+ <h3>Paper:</h3>
+ <ul>
+   <li><a href="2009-01-ASP-DAC-MemorySimulation.pdf">
+     Memory subsystem simulation in software TLM/T models
+   </a> (PDF)</li>
+ </ul>
+ 
+ <!-- *********************************************************************** -->
+ <hr>
+   <a href="http://jigsaw.w3.org/css-validator/check/referer"><img
+   src="http://jigsaw.w3.org/css-validator/images/vcss" alt="Valid CSS!"></a>
+   <a href="http://validator.w3.org/check/referer"><img
+   src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!" /></a>
+ 
+ </body>
+ </html>


Index: llvm-www/pubs/2009-01-ASP-DAC-MemorySimulation.pdf


Index: llvm-www/pubs/pubs.js
diff -u llvm-www/pubs/pubs.js:1.24 llvm-www/pubs/pubs.js:1.25
--- llvm-www/pubs/pubs.js:1.24	Sat Jun 27 02:51:15 2009
+++ llvm-www/pubs/pubs.js	Sat Jun 27 03:01:01 2009
@@ -125,6 +125,14 @@
     month: 1,
     year: 2009}, 
 
+  {url: '2009-01-ASP-DAC-MemorySimulation.html',
+   title: "Memory subsystem simulation in software TLM/T models",
+   author: "Eric Cheung, Harry Hsieh, and Felice Balarin",
+   published: "Proc. of the 14th Asia South Pacific Design Automation Conference (ASP-DAC'09)",
+    location: 'Yokohama, Japan',
+    month: 1,
+    year: 2009},
+
   {url: '2008-12-OSDI-KLEE.html',
    title: 'KLEE: Unassisted and Automatic Generation of High-Coverage Tests for Complex Systems Programs',
    author: 'Cristian Cadar, Daniel Dunbar, Dawson Engler',




