[llvm-commits] [llvm] r73622 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp test/CodeGen/ARM/thumb2-add.ll test/CodeGen/ARM/thumb2-mov.ll test/CodeGen/ARM/thumb2-mov2.ll test/CodeGen/ARM/thumb2-shifter.ll
Evan Cheng
evan.cheng at apple.com
Mon Jun 22 23:26:46 PDT 2009
On Jun 17, 2009, at 11:13 AM, Anton Korobeynikov wrote:
>
> +//
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
> +// Move Instructions.
> +//
> +def tMOVi16 : PseudoInst<(outs GPR:$dst), (ins i32imm:$src),
> + "mov $dst, $src",
> + [(set GPR:$dst, imm0_65535:$src)]>,
> + Requires<[HasThumb2]>;
> +
> +let isTwoAddress = 1 in
> +def tMOVTi16 : PseudoInst<(outs GPR:$dst), (ins GPR:$src, i32imm:
> $imm),
> + "movt $dst, $imm",
> + [(set GPR:$dst, (or (and GPR:$src, 0xffff),
> + imm16high:$imm))]>,
> + Requires<[HasThumb2]>;
> +
> +def : Pat<(and (or GPR:$src, imm16high:$imm1), imm16high0xffff:
> $imm2),
> + (tMOVTi16 GPR:$src, (HI16 imm16high:$imm1))>,
> + Requires<[HasThumb2]>;
I don't get this pattern. Can you explain?
Evan
> +
> +def : Pat<(i32 imm:$imm),
> + (tMOVTi16 (tMOVi16 (LO16 imm:$imm)),(HI16 imm:$imm))>,
> + Requires<[HasThumb2]>;
> +
> +//
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
> +// Arithmetic Instructions.
> +//
> +defm t2ADD : T2I_bin_irs <"add", BinOpFrag<(add node:$LHS, node:
> $RHS)>>;
> +defm t2SUB : T2I_bin_irs <"sub", BinOpFrag<(sub node:$LHS, node:
> $RHS)>>;
> +
> +def tADDri12 : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:
> $rhs),
> + "add $dst, $lhs, $rhs",
> + [(set GPR:$dst, (add GPR:$lhs,
> imm0_4095:$rhs))]>,
> + Requires<[HasThumb2]>;
> +def tSUBri12 : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:
> $rhs),
> + "sub $dst, $lhs, $rhs",
> + [(set GPR:$dst, (add GPR:$lhs,
> imm0_4095_neg:$rhs))]>,
> + Requires<[HasThumb2]>;
> +
> +defm t2ADDS : T2I_bin_s_irs<"add", BinOpFrag<(addc node:$LHS, node:
> $RHS)>>;
> +defm t2SUBS : T2I_bin_s_irs<"sub", BinOpFrag<(subc node:$LHS, node:
> $RHS)>>;
> +
> +defm t2ADC : T2I_bin_c_irs<"adc", BinOpFrag<(adde node:$LHS, node:
> $RHS)>>;
> +defm t2SBC : T2I_bin_c_irs<"sbc", BinOpFrag<(sube node:$LHS, node:
> $RHS)>>;
> +
> +
> +def tMLS : PseudoInst<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
> + "mls $dst, $a, $b, $c",
> + [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:
> $b)))]>,
> + Requires<[HasThumb2]>;
> +
> +def tORNrs : PseudoInst<(outs GPR:$dst), (ins GPR:$src1, t2_so_reg:
> $src2),
> + "orn $dst, $src1, $src2",
> + [(set GPR:$dst, (or GPR:$src1, (not
> t2_so_reg: $src2)))]>,
> + Requires<[HasThumb2]>;
>
> Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=73622&r1=73621&r2=73622&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Wed Jun
> 17 13:13:58 2009
> @@ -97,6 +97,7 @@
> const char *Modifier = 0);
> void printSOImmOperand(const MachineInstr *MI, int opNum);
> void printSOImm2PartOperand(const MachineInstr *MI, int opNum);
> + void printSOOperand(const MachineInstr *MI, int OpNum);
> void printSORegOperand(const MachineInstr *MI, int opNum);
> void printAddrMode2Operand(const MachineInstr *MI, int OpNo);
> void printAddrMode2OffsetOperand(const MachineInstr *MI, int
> OpNo);
> @@ -396,6 +397,28 @@
> printSOImm(O, ARM_AM::getSOImmVal(V2), VerboseAsm, TAI);
> }
>
> +// Constant shifts so_reg is a 3-operand unit corresponding to
> register forms of
> +// the A5.1 "Addressing Mode 1 - Data-processing operands" forms.
> This
> +// includes:
> +// REG 0 - e.g. R5
> +// REG IMM, SH_OPC - e.g. R5, LSL #3
> +void ARMAsmPrinter::printSOOperand(const MachineInstr *MI, int
> OpNum) {
> + const MachineOperand &MO1 = MI->getOperand(OpNum);
> + const MachineOperand &MO2 = MI->getOperand(OpNum+1);
> +
> + unsigned Reg = MO1.getReg();
> + assert(TargetRegisterInfo::isPhysicalRegister(Reg));
> + O << TM.getRegisterInfo()->getAsmName(Reg);
> +
> + // Print the shift opc.
> + O << ", "
> + << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
> + << " ";
> +
> + assert(MO2.isImm() && "Not a valid t2_so_reg value!");
> + O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
> +}
> +
> // so_reg is a 4-operand unit corresponding to register forms of the
> A5.1
> // "Addressing Mode 1 - Data-processing operands" forms. This
> includes:
> // REG 0 0 - e.g. R5
>
> Added: llvm/trunk/test/CodeGen/ARM/thumb2-add.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/thumb2-add.ll?rev=73622&view=auto
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/test/CodeGen/ARM/thumb2-add.ll (added)
> +++ llvm/trunk/test/CodeGen/ARM/thumb2-add.ll Wed Jun 17 13:13:58 2009
> @@ -0,0 +1,50 @@
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add |
> grep #255
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add |
> grep #256
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add |
> grep #257
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add |
> grep #4094
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add |
> grep #4095
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add |
> grep #4096
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep add |
> grep lsl | grep #8
> +
> +define i32 @t2ADDrc_255(i32 %lhs) {
> + %Rd = add i32 %lhs, 255;
> + ret i32 %Rd
> +}
> +
> +define i32 @t2ADDrc_256(i32 %lhs) {
> + %Rd = add i32 %lhs, 256;
> + ret i32 %Rd
> +}
> +
> +define i32 @t2ADDrc_257(i32 %lhs) {
> + %Rd = add i32 %lhs, 257;
> + ret i32 %Rd
> +}
> +
> +define i32 @t2ADDrc_4094(i32 %lhs) {
> + %Rd = add i32 %lhs, 4094;
> + ret i32 %Rd
> +}
> +
> +define i32 @t2ADDrc_4095(i32 %lhs) {
> + %Rd = add i32 %lhs, 4095;
> + ret i32 %Rd
> +}
> +
> +define i32 @t2ADDrc_4096(i32 %lhs) {
> + %Rd = add i32 %lhs, 4096;
> + ret i32 %Rd
> +}
> +
> +define i32 @t2ADDrr(i32 %lhs, i32 %rhs) {
> + %Rd = add i32 %lhs, %rhs;
> + ret i32 %Rd
> +}
> +
> +define i32 @t2ADDrs(i32 %lhs, i32 %rhs) {
> + %tmp = shl i32 %rhs, 8
> + %Rd = add i32 %lhs, %tmp;
> + ret i32 %Rd
> +}
> +
>
> Added: llvm/trunk/test/CodeGen/ARM/thumb2-mov.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/thumb2-mov.ll?rev=73622&view=auto
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/test/CodeGen/ARM/thumb2-mov.ll (added)
> +++ llvm/trunk/test/CodeGen/ARM/thumb2-mov.ll Wed Jun 17 13:13:58 2009
> @@ -0,0 +1,127 @@
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep
> #11206827
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov |
> grep movt
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov |
> grep movt
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov |
> grep movt
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov |
> grep movt
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep
> #2868947712
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov |
> grep movt
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov |
> grep movt
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov |
> grep movt
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov |
> grep movt
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep
> #2880154539
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov |
> grep movt
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov |
> grep movt
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov |
> grep movt
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov |
> grep movt
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep
> #251658240
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep #3948544
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov |
> grep movt
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep #258
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep
> #4026531840
> +
> +; Test #<const>
> +
> +; var 2.1 - 0x00ab00ab
> +define i32 @t2_const_var2_1_ok_1(i32 %lhs) {
> + %ret = add i32 %lhs, 11206827 ; 0x00ab00ab
> + ret i32 %ret
> +}
> +
> +define i32 @t2_const_var2_1_fail_1(i32 %lhs) {
> + %ret = add i32 %lhs, 11206843 ; 0x00ab00bb
> + ret i32 %ret
> +}
> +
> +define i32 @t2_const_var2_1_fail_2(i32 %lhs) {
> + %ret = add i32 %lhs, 27984043 ; 0x01ab00ab
> + ret i32 %ret
> +}
> +
> +define i32 @t2_const_var2_1_fail_3(i32 %lhs) {
> + %ret = add i32 %lhs, 27984299 ; 0x01ab01ab
> + ret i32 %ret
> +}
> +
> +define i32 @t2_const_var2_1_fail_4(i32 %lhs) {
> + %ret = add i32 %lhs, 28027649 ; 0x01abab01
> + ret i32 %ret
> +}
> +
> +; var 2.2 - 0xab00ab00
> +define i32 @t2_const_var2_2_ok_1(i32 %lhs) {
> + %ret = add i32 %lhs, 2868947712 ; 0xab00ab00
> + ret i32 %ret
> +}
> +
> +define i32 @t2_const_var2_2_fail_1(i32 %lhs) {
> + %ret = add i32 %lhs, 2868951552 ; 0xab00ba00
> + ret i32 %ret
> +}
> +
> +define i32 @t2_const_var2_2_fail_2(i32 %lhs) {
> + %ret = add i32 %lhs, 2868947728 ; 0xab00ab10
> + ret i32 %ret
> +}
> +
> +define i32 @t2_const_var2_2_fail_3(i32 %lhs) {
> + %ret = add i32 %lhs, 2869996304 ; 0xab10ab10
> + ret i32 %ret
> +}
> +
> +define i32 @t2_const_var2_2_fail_4(i32 %lhs) {
> + %ret = add i32 %lhs, 279685904 ; 0x10abab10
> + ret i32 %ret
> +}
> +
> +; var 2.3 - 0xabababab
> +define i32 @t2_const_var2_3_ok_1(i32 %lhs) {
> + %ret = add i32 %lhs, 2880154539 ; 0xabababab
> + ret i32 %ret
> +}
> +
> +define i32 @t2_const_var2_3_fail_1(i32 %lhs) {
> + %ret = add i32 %lhs, 2880154554 ; 0xabababba
> + ret i32 %ret
> +}
> +
> +define i32 @t2_const_var2_3_fail_2(i32 %lhs) {
> + %ret = add i32 %lhs, 2880158379 ; 0xababbaab
> + ret i32 %ret
> +}
> +
> +define i32 @t2_const_var2_3_fail_3(i32 %lhs) {
> + %ret = add i32 %lhs, 2881137579 ; 0xabbaabab
> + ret i32 %ret
> +}
> +
> +define i32 @t2_const_var2_3_fail_4(i32 %lhs) {
> + %ret = add i32 %lhs, 3131812779 ; 0xbaababab
> + ret i32 %ret
> +}
> +
> +; var 3 - 0x0F000000
> +define i32 @t2_const_var3_1_ok_1(i32 %lhs) {
> + %ret = add i32 %lhs, 251658240 ; 0x0F000000
> + ret i32 %ret
> +}
> +
> +define i32 @t2_const_var3_2_ok_1(i32 %lhs) {
> + %ret = add i32 %lhs, 3948544 ; 0b00000000001111000100000000000000
> + ret i32 %ret
> +}
> +
> +define i32 @t2_const_var3_2_fail_1(i32 %lhs) {
> + %ret = add i32 %lhs, 3940352 ; 0b00000000001111000010000000000000
> + ret i32 %ret
> +}
> +
> +define i32 @t2_const_var3_3_ok_1(i32 %lhs) {
> + %ret = add i32 %lhs, 258 ; 0b00000000000000000000000100000010
> + ret i32 %ret
> +}
> +
> +define i32 @t2_const_var3_4_ok_1(i32 %lhs) {
> + %ret = add i32 %lhs, 4026531840 ; 0xF0000000
> + ret i32 %ret
> +}
> +
>
> Added: llvm/trunk/test/CodeGen/ARM/thumb2-mov2.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/thumb2-mov2.ll?rev=73622&view=auto
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/test/CodeGen/ARM/thumb2-mov2.ll (added)
> +++ llvm/trunk/test/CodeGen/ARM/thumb2-mov2.ll Wed Jun 17 13:13:58
> 2009
> @@ -0,0 +1,65 @@
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep movt |
> grep #1234
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep movt |
> grep #1234
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep movt |
> grep #1234
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep movt |
> grep #1234
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov |
> grep movt
> +
> +define i32 @t2MOVTi16_ok_1(i32 %a) {
> + %1 = and i32 %a, 65535
> + %2 = shl i32 1234, 16
> + %3 = or i32 %1, %2
> +
> + ret i32 %3
> +}
> +
> +define i32 @t2MOVTi16_test_1(i32 %a) {
> + %1 = shl i32 255, 8
> + %2 = shl i32 1234, 8
> + %3 = or i32 %1, 255 ; This give us 0xFFFF in %3
> + %4 = shl i32 %2, 8 ; This gives us (1234 << 16) in %4
> + %5 = and i32 %a, %3
> + %6 = or i32 %4, %5
> +
> + ret i32 %6
> +}
> +
> +define i32 @t2MOVTi16_test_2(i32 %a) {
> + %1 = shl i32 255, 8
> + %2 = shl i32 1234, 8
> + %3 = or i32 %1, 255 ; This give us 0xFFFF in %3
> + %4 = shl i32 %2, 6
> + %5 = and i32 %a, %3
> + %6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6
> + %7 = or i32 %5, %6
> +
> + ret i32 %7
> +}
> +
> +define i32 @t2MOVTi16_test_3(i32 %a) {
> + %1 = shl i32 255, 8
> + %2 = shl i32 1234, 8
> + %3 = or i32 %1, 255 ; This give us 0xFFFF in %3
> + %4 = shl i32 %2, 6
> + %5 = and i32 %a, %3
> + %6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6
> + %7 = lshr i32 %6, 6
> + %8 = shl i32 %7, 6
> + %9 = or i32 %5, %8
> +
> + ret i32 %9
> +}
> +
> +define i32 @t2MOVTi16_test_nomatch_1(i32 %a) {
> + %1 = shl i32 255, 8
> + %2 = shl i32 1234, 8
> + %3 = or i32 %1, 255 ; This give us 0xFFFF in %3
> + %4 = shl i32 %2, 6
> + %5 = and i32 %a, %3
> + %6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6
> + %7 = lshr i32 %6, 3
> + %8 = or i32 %5, %7
> +
> + ret i32 %8
> +}
> +
> +
>
> Added: llvm/trunk/test/CodeGen/ARM/thumb2-shifter.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/thumb2-shifter.ll?rev=73622&view=auto
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/test/CodeGen/ARM/thumb2-shifter.ll (added)
> +++ llvm/trunk/test/CodeGen/ARM/thumb2-shifter.ll Wed Jun 17
> 13:13:58 2009
> @@ -0,0 +1,40 @@
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep lsl
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep lsr
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep asr
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep ror
> +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov
> +
> +define i32 @t2ADDrs_lsl(i32 %X, i32 %Y) {
> + %A = shl i32 %Y, 16
> + %B = add i32 %X, %A
> + ret i32 %B
> +}
> +
> +define i32 @t2ADDrs_lsr(i32 %X, i32 %Y) {
> + %A = lshr i32 %Y, 16
> + %B = add i32 %X, %A
> + ret i32 %B
> +}
> +
> +define i32 @t2ADDrs_asr(i32 %X, i32 %Y) {
> + %A = ashr i32 %Y, 16
> + %B = add i32 %X, %A
> + ret i32 %B
> +}
> +
> +; i32 ror(n) = (x >> n) | (x << (32 - n))
> +define i32 @t2ADDrs_ror(i32 %X, i32 %Y) {
> + %A = lshr i32 %Y, 16
> + %B = shl i32 %Y, 16
> + %C = or i32 %B, %A
> + %R = add i32 %X, %C
> + ret i32 %R
> +}
> +
> +define i32 @t2ADDrs_noRegShift(i32 %X, i32 %Y, i8 %sh) {
> + %shift.upgrd.1 = zext i8 %sh to i32
> + %A = shl i32 %Y, %shift.upgrd.1
> + %B = add i32 %X, %A
> + ret i32 %B
> +}
> +
>
>
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