[llvm-commits] [llvm] r73747 - in /llvm/trunk/lib/Target/ARM: ARM.td ARMISelLowering.cpp ARMInstrInfo.td ARMSchedule.td ARMScheduleV6.td ARMSubtarget.h ARMTargetMachine.cpp ARMTargetMachine.h
Evan Cheng
evan.cheng at apple.com
Thu Jun 18 18:51:51 PDT 2009
Author: evancheng
Date: Thu Jun 18 20:51:50 2009
New Revision: 73747
URL: http://llvm.org/viewvc/llvm-project?rev=73747&view=rev
Log:
Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits.
Added:
llvm/trunk/lib/Target/ARM/ARMSchedule.td
llvm/trunk/lib/Target/ARM/ARMScheduleV6.td
Modified:
llvm/trunk/lib/Target/ARM/ARM.td
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMSubtarget.h
llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
Modified: llvm/trunk/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=73747&r1=73746&r2=73747&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td (original)
+++ llvm/trunk/lib/Target/ARM/ARM.td Thu Jun 18 20:51:50 2009
@@ -45,62 +45,72 @@
// ARM Processors supported.
//
-class Proc<string Name, list<SubtargetFeature> Features>
- : Processor<Name, NoItineraries, Features>;
+include "ARMSchedule.td"
+
+class ProcNoItin<string Name, list<SubtargetFeature> Features>
+ : Processor<Name, GenericItineraries, Features>;
// V4 Processors.
-def : Proc<"generic", []>;
-def : Proc<"arm8", []>;
-def : Proc<"arm810", []>;
-def : Proc<"strongarm", []>;
-def : Proc<"strongarm110", []>;
-def : Proc<"strongarm1100", []>;
-def : Proc<"strongarm1110", []>;
+def : ProcNoItin<"generic", []>;
+def : ProcNoItin<"arm8", []>;
+def : ProcNoItin<"arm810", []>;
+def : ProcNoItin<"strongarm", []>;
+def : ProcNoItin<"strongarm110", []>;
+def : ProcNoItin<"strongarm1100", []>;
+def : ProcNoItin<"strongarm1110", []>;
// V4T Processors.
-def : Proc<"arm7tdmi", [ArchV4T]>;
-def : Proc<"arm7tdmi-s", [ArchV4T]>;
-def : Proc<"arm710t", [ArchV4T]>;
-def : Proc<"arm720t", [ArchV4T]>;
-def : Proc<"arm9", [ArchV4T]>;
-def : Proc<"arm9tdmi", [ArchV4T]>;
-def : Proc<"arm920", [ArchV4T]>;
-def : Proc<"arm920t", [ArchV4T]>;
-def : Proc<"arm922t", [ArchV4T]>;
-def : Proc<"arm940t", [ArchV4T]>;
-def : Proc<"ep9312", [ArchV4T]>;
+def : ProcNoItin<"arm7tdmi", [ArchV4T]>;
+def : ProcNoItin<"arm7tdmi-s", [ArchV4T]>;
+def : ProcNoItin<"arm710t", [ArchV4T]>;
+def : ProcNoItin<"arm720t", [ArchV4T]>;
+def : ProcNoItin<"arm9", [ArchV4T]>;
+def : ProcNoItin<"arm9tdmi", [ArchV4T]>;
+def : ProcNoItin<"arm920", [ArchV4T]>;
+def : ProcNoItin<"arm920t", [ArchV4T]>;
+def : ProcNoItin<"arm922t", [ArchV4T]>;
+def : ProcNoItin<"arm940t", [ArchV4T]>;
+def : ProcNoItin<"ep9312", [ArchV4T]>;
// V5T Processors.
-def : Proc<"arm10tdmi", [ArchV5T]>;
-def : Proc<"arm1020t", [ArchV5T]>;
+def : ProcNoItin<"arm10tdmi", [ArchV5T]>;
+def : ProcNoItin<"arm1020t", [ArchV5T]>;
// V5TE Processors.
-def : Proc<"arm9e", [ArchV5TE]>;
-def : Proc<"arm926ej-s", [ArchV5TE]>;
-def : Proc<"arm946e-s", [ArchV5TE]>;
-def : Proc<"arm966e-s", [ArchV5TE]>;
-def : Proc<"arm968e-s", [ArchV5TE]>;
-def : Proc<"arm10e", [ArchV5TE]>;
-def : Proc<"arm1020e", [ArchV5TE]>;
-def : Proc<"arm1022e", [ArchV5TE]>;
-def : Proc<"xscale", [ArchV5TE]>;
-def : Proc<"iwmmxt", [ArchV5TE]>;
+def : ProcNoItin<"arm9e", [ArchV5TE]>;
+def : ProcNoItin<"arm926ej-s", [ArchV5TE]>;
+def : ProcNoItin<"arm946e-s", [ArchV5TE]>;
+def : ProcNoItin<"arm966e-s", [ArchV5TE]>;
+def : ProcNoItin<"arm968e-s", [ArchV5TE]>;
+def : ProcNoItin<"arm10e", [ArchV5TE]>;
+def : ProcNoItin<"arm1020e", [ArchV5TE]>;
+def : ProcNoItin<"arm1022e", [ArchV5TE]>;
+def : ProcNoItin<"xscale", [ArchV5TE]>;
+def : ProcNoItin<"iwmmxt", [ArchV5TE]>;
// V6 Processors.
-def : Proc<"arm1136j-s", [ArchV6]>;
-def : Proc<"arm1136jf-s", [ArchV6, FeatureVFP2]>;
-def : Proc<"arm1176jz-s", [ArchV6]>;
-def : Proc<"arm1176jzf-s", [ArchV6, FeatureVFP2]>;
-def : Proc<"mpcorenovfp", [ArchV6]>;
-def : Proc<"mpcore", [ArchV6, FeatureVFP2]>;
+def : Processor<"arm1136j-s", V6Itineraries,
+ [ArchV6]>;
+def : Processor<"arm1136jf-s", V6Itineraries,
+ [ArchV6, FeatureVFP2]>;
+def : Processor<"arm1176jz-s", V6Itineraries,
+ [ArchV6]>;
+def : Processor<"arm1176jzf-s", V6Itineraries,
+ [ArchV6, FeatureVFP2]>;
+def : Processor<"mpcorenovfp", V6Itineraries,
+ [ArchV6]>;
+def : Processor<"mpcore", V6Itineraries,
+ [ArchV6, FeatureVFP2]>;
// V6T2 Processors.
-def : Proc<"arm1156t2-s", [ArchV6T2, FeatureThumb2]>;
-def : Proc<"arm1156t2f-s", [ArchV6T2, FeatureThumb2, FeatureVFP2]>;
+def : Processor<"arm1156t2-s", V6Itineraries,
+ [ArchV6T2, FeatureThumb2]>;
+def : Processor<"arm1156t2f-s", V6Itineraries,
+ [ArchV6T2, FeatureThumb2, FeatureVFP2]>;
// V7 Processors.
-def : Proc<"cortex-a8", [ArchV7A, FeatureThumb2, FeatureNEON]>;
-def : Proc<"cortex-a9", [ArchV7A, FeatureThumb2, FeatureNEON]>;
+def : ProcNoItin<"cortex-a8", [ArchV7A, FeatureThumb2, FeatureNEON]>;
+def : ProcNoItin<"cortex-a9", [ArchV7A, FeatureThumb2, FeatureNEON]>;
//===----------------------------------------------------------------------===//
// Register File Description
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=73747&r1=73746&r2=73747&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jun 18 20:51:50 2009
@@ -292,6 +292,21 @@
setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2);
+ if (!Subtarget->isThumb()) {
+ // Use branch latency information to determine if-conversion limits.
+ const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
+ const InstrItineraryData &InstrItins = Subtarget->getInstrItineraryData();
+ unsigned Latency = InstrItins.getLatency(TII->get(ARM::BL).getSchedClass());
+ if (Latency > 1) {
+ setIfCvtBlockSizeLimit(Latency-1);
+ if (Latency > 2)
+ setIfCvtDupBlockSizeLimit(Latency-2);
+ } else {
+ setIfCvtBlockSizeLimit(10);
+ setIfCvtDupBlockSizeLimit(2);
+ }
+ }
+
maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
// Do not enable CodePlacementOpt for now: it currently runs after the
// ARMConstantIslandPass and messes up branch relaxation and placement
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=73747&r1=73746&r2=73747&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Jun 18 20:51:50 2009
@@ -539,7 +539,7 @@
LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1",
[]>;
-let isCall = 1,
+let isCall = 1, Itinerary = IIC_Br,
Defs = [R0, R1, R2, R3, R12, LR,
D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
@@ -567,7 +567,7 @@
}
}
-let isBranch = 1, isTerminator = 1 in {
+let isBranch = 1, isTerminator = 1, Itinerary = IIC_Br in {
// B is "predicable" since it can be xformed into a Bcc.
let isBarrier = 1 in {
let isPredicable = 1 in
Added: llvm/trunk/lib/Target/ARM/ARMSchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSchedule.td?rev=73747&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSchedule.td (added)
+++ llvm/trunk/lib/Target/ARM/ARMSchedule.td Thu Jun 18 20:51:50 2009
@@ -0,0 +1,35 @@
+//===- ARMSchedule.td - ARM Scheduling Definitions ---------*- tablegen -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Functional units across ARM processors
+//
+def FU_iALU : FuncUnit; // Integer alu unit
+def FU_iLdSt : FuncUnit; // Integer load / store unit
+def FU_FpALU : FuncUnit; // FP alu unit
+def FU_FpLdSt : FuncUnit; // FP load / store unit
+def FU_Br : FuncUnit; // Branch unit
+
+//===----------------------------------------------------------------------===//
+// Instruction Itinerary classes used for ARM
+//
+def IIC_iALU : InstrItinClass;
+def IIC_iLoad : InstrItinClass;
+def IIC_iStore : InstrItinClass;
+def IIC_fpALU : InstrItinClass;
+def IIC_fpLoad : InstrItinClass;
+def IIC_fpStore : InstrItinClass;
+def IIC_Br : InstrItinClass;
+
+//===----------------------------------------------------------------------===//
+// Processor instruction itineraries.
+
+def GenericItineraries : ProcessorItineraries<[]>;
+
+include "ARMScheduleV6.td"
Added: llvm/trunk/lib/Target/ARM/ARMScheduleV6.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleV6.td?rev=73747&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleV6.td (added)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleV6.td Thu Jun 18 20:51:50 2009
@@ -0,0 +1,22 @@
+//===- ARMSchedule.td - ARM v6 Scheduling Definitions ------*- tablegen -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the itinerary class data for the ARM v6 processors.
+//
+//===----------------------------------------------------------------------===//
+
+def V6Itineraries : ProcessorItineraries<[
+ InstrItinData<IIC_iALU , [InstrStage<1, [FU_iALU]>]>,
+ InstrItinData<IIC_iLoad , [InstrStage<2, [FU_iLdSt]>]>,
+ InstrItinData<IIC_iStore , [InstrStage<1, [FU_iLdSt]>]>,
+ InstrItinData<IIC_fpALU , [InstrStage<6, [FU_FpALU]>]>,
+ InstrItinData<IIC_fpLoad , [InstrStage<2, [FU_FpLdSt]>]>,
+ InstrItinData<IIC_fpStore , [InstrStage<1, [FU_FpLdSt]>]>,
+ InstrItinData<IIC_Br , [InstrStage<3, [FU_Br]>]>
+]>;
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=73747&r1=73746&r2=73747&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Thu Jun 18 20:51:50 2009
@@ -14,6 +14,7 @@
#ifndef ARMSUBTARGET_H
#define ARMSUBTARGET_H
+#include "llvm/Target/TargetInstrItineraries.h"
#include "llvm/Target/TargetSubtarget.h"
#include <string>
@@ -58,6 +59,9 @@
/// CPUString - String name of used CPU.
std::string CPUString;
+ /// Selected instruction itineraries (one entry per itinerary class.)
+ InstrItineraryData InstrItins;
+
public:
enum {
isELF, isDarwin
@@ -110,6 +114,10 @@
const std::string & getCPUString() const { return CPUString; }
+ /// getInstrItins - Return the instruction itineraies based on subtarget
+ /// selection.
+ const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
+
/// getStackAlignment - Returns the minimum alignment known to hold of the
/// stack frame on entry to the function and which must be maintained by every
/// function for this subtarget.
Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=73747&r1=73746&r2=73747&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Thu Jun 18 20:51:50 2009
@@ -102,7 +102,8 @@
InstrInfo(Subtarget),
FrameInfo(Subtarget),
JITInfo(),
- TLInfo(*this) {
+ TLInfo(*this),
+ InstrItins(Subtarget.getInstrItineraryData()) {
DefRelocModel = getRelocationModel();
}
Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=73747&r1=73746&r2=73747&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Thu Jun 18 20:51:50 2009
@@ -28,13 +28,14 @@
class Module;
class ARMTargetMachine : public LLVMTargetMachine {
- ARMSubtarget Subtarget;
- const TargetData DataLayout; // Calculates type size & alignment
- ARMInstrInfo InstrInfo;
- ARMFrameInfo FrameInfo;
- ARMJITInfo JITInfo;
- ARMTargetLowering TLInfo;
- Reloc::Model DefRelocModel; // Reloc model before it's overridden.
+ ARMSubtarget Subtarget;
+ const TargetData DataLayout; // Calculates type size & alignment
+ ARMInstrInfo InstrInfo;
+ ARMFrameInfo FrameInfo;
+ ARMJITInfo JITInfo;
+ ARMTargetLowering TLInfo;
+ InstrItineraryData InstrItins;
+ Reloc::Model DefRelocModel; // Reloc model before it's overridden.
protected:
// To avoid having target depend on the asmprinter stuff libraries, asmprinter
@@ -59,6 +60,9 @@
virtual ARMTargetLowering *getTargetLowering() const {
return const_cast<ARMTargetLowering*>(&TLInfo);
}
+ virtual const InstrItineraryData getInstrItineraryData() const {
+ return InstrItins;
+ }
static void registerAsmPrinter(AsmPrinterCtorFn F) {
AsmPrinterCtor = F;
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