[llvm-commits] [llvm] r72957 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/TargetLowering.cpp lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/dagcombine-buildvector.ll

[Evan Cheng]

On Jun 5, 2009, at 2:37 PM, Nate Begeman wrote:

>
> +  // The type legalizer will have broken apart v2i64 build_vector  
> created during
> +  // widening before the code which handles that case is run.  Look  
> for build
> +  // vector (load, load + 4, 0/undef, 0/undef)
> +  if (VT == MVT::v4i32 || VT == MVT::v4f32) {
> +    LoadSDNode *LD0 = dyn_cast<LoadSDNode>(N->getOperand(0));
> +    LoadSDNode *LD1 = dyn_cast<LoadSDNode>(N->getOperand(1));
> +    if (!LD0 || !LD1)
> +      return SDValue();
> +    if (LD0->getExtensionType() != ISD::NON_EXTLOAD ||
> +        LD1->getExtensionType() != ISD::NON_EXTLOAD)
> +      return SDValue();
> +    // Make sure the second elt is a consecutive load.
> +    if (!TLI.isConsecutiveLoad(LD1, LD0, EVT.getSizeInBits()/8, 1,
> +                               DAG.getMachineFunction().getFrameInfo 
> ()))
> +      return SDValue();

Nate, do you need to check if LD0 and LD1 each has a single data use?

Evan
>
> -  SDVTList Tys = DAG.getVTList(VT, MVT::Other);
> -  SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
> -  SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
> -  TargetLowering::TargetLoweringOpt TLO(DAG);
> -  TLO.CombineTo(SDValue(Base, 1), ResNode.getValue(1));
> -  DCI.CommitTargetLoweringOpt(TLO);
> -  return ResNode;
> +    SDValue N2 = N->getOperand(2);
> +    SDValue N3 = N->getOperand(3);
> +    if (!isZeroNode(N2) && N2.getOpcode() != ISD::UNDEF)
> +      return SDValue();
> +    if (!isZeroNode(N3) && N3.getOpcode() != ISD::UNDEF)
> +      return SDValue();
> +
> +    SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
> +    SDValue Ops[] = { LD0->getChain(), LD0->getBasePtr() };
> +    SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,  
> 2);
> +    TargetLowering::TargetLoweringOpt TLO(DAG);
> +    TLO.CombineTo(SDValue(LD0, 1), ResNode.getValue(1));
> +    DCI.CommitTargetLoweringOpt(TLO);
> +    return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
> +  }
> +  return SDValue();
> }
>
> /// PerformSELECTCombine - Do target-specific dag combines on SELECT  
> nodes.
>
> Modified: llvm/trunk/test/CodeGen/X86/dagcombine-buildvector.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dagcombine-buildvector.ll?rev=72957&r1=72956&r2=72957&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/test/CodeGen/X86/dagcombine-buildvector.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/dagcombine-buildvector.ll Fri Jun  5  
> 16:37:30 2009
> @@ -1,13 +1,25 @@
> -; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -o %t -f
> +; RUN: llvm-as < %s | llc -march=x86 -mcpu=penryn -disable-mmx -o  
> %t -f
> ; RUN: grep unpcklpd %t | count 1
> ; RUN: grep movapd %t | count 1
> +; RUN: grep movaps %t | count 1
>
> ; Shows a dag combine bug that will generate an illegal build vector
> ; with v2i64 build_vector i32, i32.
>
> -define void @test(<2 x double>* %dst, <4 x double> %src) {
> +define void @test(<2 x double>* %dst, <4 x double> %src) nounwind {
> entry:
>         %tmp7.i = shufflevector <4 x double> %src, <4 x double>  
> undef, <2 x i32> < i32 0, i32 2 >
>         store <2 x double> %tmp7.i, <2 x double>* %dst
>         ret void
> }
> +
> +define void @test2(<4 x i16>* %src, <4 x i32>* %dest) nounwind {
> +entry:
> +        %tmp1 = load <4 x i16>* %src
> +        %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8  
> x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef,  
> i32 undef>
> +        %0 = tail call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>  
> %tmp3)
> +        store <4 x i32> %0, <4 x i32>* %dest
> +        ret void
> +}
> +
> +declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind  
> readnone
>
>
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