[llvm-commits] [llvm] r73009 - in /llvm/trunk: lib/Target/PowerPC/PPCInstrAltivec.td test/CodeGen/PowerPC/vec_shift.ll

Eli Friedman eli.friedman at gmail.com
Sat Jun 6 18:07:56 PDT 2009


Author: efriedma
Date: Sat Jun  6 20:07:55 2009
New Revision: 73009

URL: http://llvm.org/viewvc/llvm-project?rev=73009&view=rev
Log:
PR3628: Add patterns to match SHL/SRL/SRA to the corresponding Altivec 
instructions.


Added:
    llvm/trunk/test/CodeGen/PowerPC/vec_shift.ll
Modified:
    llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td?rev=73009&r1=73008&r2=73009&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td Sat Jun  6 20:07:55 2009
@@ -666,3 +666,25 @@
 
 def : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC),
           (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC)>;
+
+// Vector shifts
+def : Pat<(v16i8 (shl (v16i8 VRRC:$vA), (v16i8 VRRC:$vB))),
+          (v16i8 (VSLB VRRC:$vA, VRRC:$vB))>;
+def : Pat<(v8i16 (shl (v8i16 VRRC:$vA), (v8i16 VRRC:$vB))),
+          (v8i16 (VSLH VRRC:$vA, VRRC:$vB))>;
+def : Pat<(v4i32 (shl (v4i32 VRRC:$vA), (v4i32 VRRC:$vB))),
+          (v4i32 (VSLW VRRC:$vA, VRRC:$vB))>;
+
+def : Pat<(v16i8 (srl (v16i8 VRRC:$vA), (v16i8 VRRC:$vB))),
+          (v16i8 (VSRB VRRC:$vA, VRRC:$vB))>;
+def : Pat<(v8i16 (srl (v8i16 VRRC:$vA), (v8i16 VRRC:$vB))),
+          (v8i16 (VSRH VRRC:$vA, VRRC:$vB))>;
+def : Pat<(v4i32 (srl (v4i32 VRRC:$vA), (v4i32 VRRC:$vB))),
+          (v4i32 (VSRW VRRC:$vA, VRRC:$vB))>;
+
+def : Pat<(v16i8 (sra (v16i8 VRRC:$vA), (v16i8 VRRC:$vB))),
+          (v16i8 (VSRAB VRRC:$vA, VRRC:$vB))>;
+def : Pat<(v8i16 (sra (v8i16 VRRC:$vA), (v8i16 VRRC:$vB))),
+          (v8i16 (VSRAH VRRC:$vA, VRRC:$vB))>;
+def : Pat<(v4i32 (sra (v4i32 VRRC:$vA), (v4i32 VRRC:$vB))),
+          (v4i32 (VSRAW VRRC:$vA, VRRC:$vB))>;

Added: llvm/trunk/test/CodeGen/PowerPC/vec_shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_shift.ll?rev=73009&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vec_shift.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/vec_shift.ll Sat Jun  6 20:07:55 2009
@@ -0,0 +1,10 @@
+; RUN: llvm-as < %s | llc  -march=ppc32 -mcpu=g5
+; PR3628
+
+define void @update(<4 x i32> %val, <4 x i32>* %dst) nounwind {
+entry:
+	%shl = shl <4 x i32> %val, < i32 4, i32 3, i32 2, i32 1 >
+	%shr = ashr <4 x i32> %shl, < i32 1, i32 2, i32 3, i32 4 >
+	store <4 x i32> %shr, <4 x i32>* %dst
+	ret void
+}





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