[llvm-commits] [llvm] r73006 - in /llvm/trunk: lib/Transforms/Scalar/InstructionCombining.cpp test/Transforms/InstCombine/vec_demanded_elts-3.ll

[Eli Friedman]

Author: efriedma
Date: Sat Jun  6 15:08:03 2009
New Revision: 73006

URL: http://llvm.org/viewvc/llvm-project?rev=73006&view=rev
Log:
PR4340: Run SimplifyDemandedVectorElts on insertelement instructions; 
sometimes it can find simplifications that won't be found otherwise.


Added:
    llvm/trunk/test/Transforms/InstCombine/vec_demanded_elts-3.ll
Modified:
    llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=73006&r1=73005&r2=73006&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Sat Jun  6 15:08:03 2009
@@ -12579,6 +12579,12 @@
     }
   }
 
+  unsigned VWidth = cast<VectorType>(VecOp->getType())->getNumElements();
+  APInt UndefElts(VWidth, 0);
+  APInt AllOnesEltMask(APInt::getAllOnesValue(VWidth));
+  if (SimplifyDemandedVectorElts(&IE, AllOnesEltMask, UndefElts))
+    return &IE;
+
   return 0;
 }
 

Added: llvm/trunk/test/Transforms/InstCombine/vec_demanded_elts-3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/vec_demanded_elts-3.ll?rev=73006&view=auto

==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/vec_demanded_elts-3.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/vec_demanded_elts-3.ll Sat Jun  6 15:08:03 2009
@@ -0,0 +1,14 @@
+; RUN: llvm-as < %s | opt -instcombine | llvm-dis | not grep load
+; PR4340
+
+define void @vac(<4 x float>* nocapture %a) nounwind {
+entry:
+	%tmp1 = load <4 x float>* %a		; <<4 x float>> [#uses=1]
+	%vecins = insertelement <4 x float> %tmp1, float 0.000000e+00, i32 0	; <<4 x float>> [#uses=1]
+	%vecins4 = insertelement <4 x float> %vecins, float 0.000000e+00, i32 1; <<4 x float>> [#uses=1]
+	%vecins6 = insertelement <4 x float> %vecins4, float 0.000000e+00, i32 2; <<4 x float>> [#uses=1]
+	%vecins8 = insertelement <4 x float> %vecins6, float 0.000000e+00, i32 3; <<4 x float>> [#uses=1]
+	store <4 x float> %vecins8, <4 x float>* %a
+	ret void
+}
+