[llvm-commits] [llvm] r72991 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/2009-06-05-VariableIndexInsert.ll

[Eli Friedman]

Author: efriedma
Date: Sat Jun  6 01:32:50 2009
New Revision: 72991

URL: http://llvm.org/viewvc/llvm-project?rev=72991&view=rev
Log:
Avoid crashing on a variable-index insertelement with element type i16.


Added:
    llvm/trunk/test/CodeGen/X86/2009-06-05-VariableIndexInsert.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=72991&r1=72990&r2=72991&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Jun  6 01:32:50 2009
@@ -4272,7 +4272,7 @@
   SDValue N1 = Op.getOperand(1);
   SDValue N2 = Op.getOperand(2);
 
-  if (EVT.getSizeInBits() == 16) {
+  if (EVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
     // Transform it so it match pinsrw which expects a 16-bit value in a GR32
     // as its second argument.
     if (N1.getValueType() != MVT::i32)

Added: llvm/trunk/test/CodeGen/X86/2009-06-05-VariableIndexInsert.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-06-05-VariableIndexInsert.ll?rev=72991&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-06-05-VariableIndexInsert.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2009-06-05-VariableIndexInsert.ll Sat Jun  6 01:32:50 2009
@@ -0,0 +1,11 @@
+; RUN: llvm-as < %s | llc
+
+define <2 x i64> @_mm_insert_epi16(<2 x i64> %a, i32 %b, i32 %imm) nounwind readnone {
+entry:
+	%conv = bitcast <2 x i64> %a to <8 x i16>		; <<8 x i16>> [#uses=1]
+	%conv2 = trunc i32 %b to i16		; <i16> [#uses=1]
+	%and = and i32 %imm, 7		; <i32> [#uses=1]
+	%vecins = insertelement <8 x i16> %conv, i16 %conv2, i32 %and		; <<8 x i16>> [#uses=1]
+	%conv6 = bitcast <8 x i16> %vecins to <2 x i64>		; <<2 x i64>> [#uses=1]
+	ret <2 x i64> %conv6
+}