[llvm-commits] [llvm] r72836 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.cpp test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll

[Eli Friedman]

Author: efriedma
Date: Wed Jun  3 21:32:04 2009
New Revision: 72836

URL: http://llvm.org/viewvc/llvm-project?rev=72836&view=rev
Log:
PR3739, part 2: Use an explicit store to spill XMM registers. (Previously,
the code tried to use "push", which doesn't exist for XMM registers.)


Added:
    llvm/trunk/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll
Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=72836&r1=72835&r2=72836&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Wed Jun  3 21:32:04 2009
@@ -2009,16 +2009,24 @@
 
   MachineFunction &MF = *MBB.getParent();
   X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
-  X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize);
+  unsigned CalleeFrameSize = 0;
   
   unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
   for (unsigned i = CSI.size(); i != 0; --i) {
     unsigned Reg = CSI[i-1].getReg();
+    const TargetRegisterClass *RegClass = CSI[i-1].getRegClass();
     // Add the callee-saved register as live-in. It's killed at the spill.
     MBB.addLiveIn(Reg);
-    BuildMI(MBB, MI, DL, get(Opc))
-      .addReg(Reg, RegState::Kill);
+    if (RegClass != &X86::VR128RegClass) {
+      CalleeFrameSize += SlotSize;
+      BuildMI(MBB, MI, DL, get(Opc))
+        .addReg(Reg, RegState::Kill);
+    } else {
+      storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), RegClass);
+    }
   }
+
+  X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
   return true;
 }
 
@@ -2036,7 +2044,12 @@
   unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
     unsigned Reg = CSI[i].getReg();
-    BuildMI(MBB, MI, DL, get(Opc), Reg);
+    const TargetRegisterClass *RegClass = CSI[i].getRegClass();
+    if (RegClass != &X86::VR128RegClass) {
+      BuildMI(MBB, MI, DL, get(Opc), Reg);
+    } else {
+      loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
+    }
   }
   return true;
 }

Added: llvm/trunk/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll?rev=72836&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll Wed Jun  3 21:32:04 2009
@@ -0,0 +1,12 @@
+; RUN: llvm-as < %s | llc -o %t1 -f
+; RUN: grep "subq.*\\\$40, \\\%rsp" %t1
+; RUN: grep "movaps	\\\%xmm8, \\\(\\\%rsp\\\)" %t1
+; RUN: grep "movaps	\\\%xmm7, 16\\\(\\\%rsp\\\)" %t1
+target triple = "x86_64-mingw64"
+
+define i32 @a() nounwind {
+entry:
+	tail call void asm sideeffect "", "~{xmm7},~{xmm8},~{dirflag},~{fpsr},~{flags}"() nounwind
+	ret i32 undef
+}
+