[llvm-commits] [llvm] r72697 - in /llvm/trunk/lib: ExecutionEngine/JIT/JIT.h Target/ARM/ARM.h Target/ARM/ARMCodeEmitter.cpp Target/Alpha/AlphaCodeEmitter.cpp Target/PowerPC/PPCCodeEmitter.cpp Target/PowerPC/PPCTargetMachine.cpp Target/X86/X86.h Target/X86/X86CodeEmitter.cpp Target/X86/X86TargetMachine.cpp
Bruno Cardoso Lopes
bruno.cardoso at gmail.com
Mon Jun 1 12:57:38 PDT 2009
Author: bruno
Date: Mon Jun 1 14:57:37 2009
New Revision: 72697
URL: http://llvm.org/viewvc/llvm-project?rev=72697&view=rev
Log:
Fix new CodeEmitter stuff to follow LLVM codying style. Patch by Aaron Gray
Modified:
llvm/trunk/lib/ExecutionEngine/JIT/JIT.h
llvm/trunk/lib/Target/ARM/ARM.h
llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp
llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp
llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
llvm/trunk/lib/Target/X86/X86.h
llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
Modified: llvm/trunk/lib/ExecutionEngine/JIT/JIT.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JIT.h?rev=72697&r1=72696&r2=72697&view=diff
==============================================================================
--- llvm/trunk/lib/ExecutionEngine/JIT/JIT.h (original)
+++ llvm/trunk/lib/ExecutionEngine/JIT/JIT.h Mon Jun 1 14:57:37 2009
@@ -51,7 +51,7 @@
class JIT : public ExecutionEngine {
TargetMachine &TM; // The current target we are compiling to
TargetJITInfo &TJI; // The JITInfo for the target we are compiling to
- JITCodeEmitter *JCE; // JCE object
+ JITCodeEmitter *JCE; // JCE object
JITState *jitstate;
Modified: llvm/trunk/lib/Target/ARM/ARM.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=72697&r1=72696&r2=72697&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.h (original)
+++ llvm/trunk/lib/Target/ARM/ARM.h Mon Jun 1 14:57:37 2009
@@ -98,15 +98,10 @@
FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM,
MachineCodeEmitter &MCE);
-FunctionPass *createARMCodeEmitterPass(
- ARMTargetMachine &TM, MachineCodeEmitter &MCE);
-/*
-template< class machineCodeEmitter>
-FunctionPass *createARMCodeEmitterPass(
- ARMTargetMachine &TM, machineCodeEmitter &MCE);
-*/
-FunctionPass *createARMJITCodeEmitterPass(
- ARMTargetMachine &TM, JITCodeEmitter &JCE);
+FunctionPass *createARMCodeEmitterPass( ARMTargetMachine &TM,
+ MachineCodeEmitter &MCE);
+FunctionPass *createARMJITCodeEmitterPass( ARMTargetMachine &TM,
+ JITCodeEmitter &JCE);
FunctionPass *createARMLoadStoreOptimizationPass();
FunctionPass *createARMConstantIslandPass();
Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=72697&r1=72696&r2=72697&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Mon Jun 1 14:57:37 2009
@@ -45,34 +45,31 @@
class ARMCodeEmitter {
public:
-
/// getBinaryCodeForInstr - This function, generated by the
/// CodeEmitterGenerator using TableGen, produces the binary encoding for
/// machine instructions.
-
unsigned getBinaryCodeForInstr(const MachineInstr &MI);
};
- template< class machineCodeEmitter>
- class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass,
- public ARMCodeEmitter
- {
+ template<class CodeEmitter>
+ class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass,
+ public ARMCodeEmitter {
ARMJITInfo *JTI;
const ARMInstrInfo *II;
const TargetData *TD;
TargetMachine &TM;
- machineCodeEmitter &MCE;
+ CodeEmitter &MCE;
const std::vector<MachineConstantPoolEntry> *MCPEs;
const std::vector<MachineJumpTableEntry> *MJTEs;
bool IsPIC;
public:
static char ID;
- explicit Emitter(TargetMachine &tm, machineCodeEmitter &mce)
+ explicit Emitter(TargetMachine &tm, CodeEmitter &mce)
: MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
MCE(mce), MCPEs(0), MJTEs(0),
IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
- Emitter(TargetMachine &tm, machineCodeEmitter &mce,
+ Emitter(TargetMachine &tm, CodeEmitter &mce,
const ARMInstrInfo &ii, const TargetData &td)
: MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
MCE(mce), MCPEs(0), MJTEs(0),
@@ -170,30 +167,28 @@
void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
intptr_t JTBase = 0);
};
- template <class machineCodeEmitter>
- char Emitter<machineCodeEmitter>::ID = 0;
+ template <class CodeEmitter>
+ char Emitter<CodeEmitter>::ID = 0;
}
/// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
/// to the specified MCE object.
namespace llvm {
-
-FunctionPass *createARMCodeEmitterPass(
- ARMTargetMachine &TM, MachineCodeEmitter &MCE)
-{
+
+FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM,
+ MachineCodeEmitter &MCE) {
return new Emitter<MachineCodeEmitter>(TM, MCE);
}
-FunctionPass *createARMJITCodeEmitterPass(
- ARMTargetMachine &TM, JITCodeEmitter &JCE)
-{
+FunctionPass *createARMJITCodeEmitterPass(ARMTargetMachine &TM,
+ JITCodeEmitter &JCE) {
return new Emitter<JITCodeEmitter>(TM, JCE);
}
} // end namespace llvm
-template< class machineCodeEmitter>
-bool Emitter< machineCodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
+template<class CodeEmitter>
+bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
MF.getTarget().getRelocationModel() != Reloc::Static) &&
"JIT relocation model must be set to static or default!");
@@ -222,8 +217,8 @@
/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
///
-template< class machineCodeEmitter>
-unsigned Emitter< machineCodeEmitter>::getShiftOp(unsigned Imm) const {
+template<class CodeEmitter>
+unsigned Emitter<CodeEmitter>::getShiftOp(unsigned Imm) const {
switch (ARM_AM::getAM2ShiftOpc(Imm)) {
default: assert(0 && "Unknown shift opc!");
case ARM_AM::asr: return 2;
@@ -237,9 +232,9 @@
/// getMachineOpValue - Return binary encoding of operand. If the machine
/// operand requires relocation, record the relocation and return zero.
-template< class machineCodeEmitter>
-unsigned Emitter< machineCodeEmitter>::getMachineOpValue(const MachineInstr &MI,
- const MachineOperand &MO) {
+template<class CodeEmitter>
+unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI,
+ const MachineOperand &MO) {
if (MO.isReg())
return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
else if (MO.isImm())
@@ -267,18 +262,19 @@
/// emitGlobalAddress - Emit the specified address to the code stream.
///
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
- bool NeedStub, intptr_t ACPV) {
- MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
- Reloc, GV, ACPV, NeedStub));
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
+ bool NeedStub, intptr_t ACPV) {
+ MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
+ GV, ACPV, NeedStub));
}
/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
/// be emitted to the current location in the function, and allow it to be PC
/// relative.
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
+ unsigned Reloc) {
MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
Reloc, ES));
}
@@ -286,8 +282,9 @@
/// emitConstPoolAddress - Arrange for the address of an constant pool
/// to be emitted to the current location in the function, and allow it to be PC
/// relative.
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI,
+ unsigned Reloc) {
// Tell JIT emitter we'll resolve the address.
MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
Reloc, CPI, 0, true));
@@ -296,22 +293,23 @@
/// emitJumpTableAddress - Arrange for the address of a jump table to
/// be emitted to the current location in the function, and allow it to be PC
/// relative.
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTIndex,
+ unsigned Reloc) {
MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
Reloc, JTIndex, 0, true));
}
/// emitMachineBasicBlock - Emit the specified address basic block.
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitMachineBasicBlock(MachineBasicBlock *BB,
- unsigned Reloc, intptr_t JTBase) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitMachineBasicBlock(MachineBasicBlock *BB,
+ unsigned Reloc, intptr_t JTBase) {
MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
Reloc, BB, JTBase));
}
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitWordLE(unsigned Binary) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitWordLE(unsigned Binary) {
#ifndef NDEBUG
DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
<< Binary << std::dec << "\n";
@@ -319,8 +317,8 @@
MCE.emitWordLE(Binary);
}
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitDWordLE(uint64_t Binary) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitDWordLE(uint64_t Binary) {
#ifndef NDEBUG
DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
<< (unsigned)Binary << std::dec << "\n";
@@ -330,8 +328,8 @@
MCE.emitDWordLE(Binary);
}
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitInstruction(const MachineInstr &MI) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI) {
DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI;
NumEmitted++; // Keep track of the # of mi's emitted
@@ -397,8 +395,8 @@
}
}
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) {
unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
@@ -465,8 +463,8 @@
}
}
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitMOVi2piecesInstruction(const MachineInstr &MI) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitMOVi2piecesInstruction(const MachineInstr &MI) {
const MachineOperand &MO0 = MI.getOperand(0);
const MachineOperand &MO1 = MI.getOperand(1);
assert(MO1.isImm() && "Not a valid so_imm value!");
@@ -507,8 +505,8 @@
emitWordLE(Binary);
}
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitLEApcrelJTInstruction(const MachineInstr &MI) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitLEApcrelJTInstruction(const MachineInstr &MI) {
// It's basically add r, pc, (LJTI - $+8)
const TargetInstrDesc &TID = MI.getDesc();
@@ -536,8 +534,8 @@
emitWordLE(Binary);
}
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitPseudoMoveInstruction(const MachineInstr &MI) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitPseudoMoveInstruction(const MachineInstr &MI) {
unsigned Opcode = MI.getDesc().Opcode;
// Part of binary is determined by TableGn.
@@ -576,15 +574,15 @@
emitWordLE(Binary);
}
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::addPCLabel(unsigned LabelID) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::addPCLabel(unsigned LabelID) {
DOUT << " ** LPC" << LabelID << " @ "
<< (void*)MCE.getCurrentPCValue() << '\n';
JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
}
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
unsigned Opcode = MI.getDesc().Opcode;
switch (Opcode) {
default:
@@ -653,8 +651,9 @@
}
}
-template< class machineCodeEmitter>
-unsigned Emitter< machineCodeEmitter>::getMachineSoRegOpValue(const MachineInstr &MI,
+template<class CodeEmitter>
+unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue(
+ const MachineInstr &MI,
const TargetInstrDesc &TID,
const MachineOperand &MO,
unsigned OpIdx) {
@@ -712,8 +711,8 @@
return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
}
-template< class machineCodeEmitter>
-unsigned Emitter< machineCodeEmitter>::getMachineSoImmOpValue(unsigned SoImm) {
+template<class CodeEmitter>
+unsigned Emitter<CodeEmitter>::getMachineSoImmOpValue(unsigned SoImm) {
// Encode rotate_imm.
unsigned Binary = (ARM_AM::getSOImmValRot(SoImm) >> 1)
<< ARMII::SoRotImmShift;
@@ -723,9 +722,9 @@
return Binary;
}
-template< class machineCodeEmitter>
-unsigned Emitter< machineCodeEmitter>::getAddrModeSBit(const MachineInstr &MI,
- const TargetInstrDesc &TID) const {
+template<class CodeEmitter>
+unsigned Emitter<CodeEmitter>::getAddrModeSBit(const MachineInstr &MI,
+ const TargetInstrDesc &TID) const {
for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
const MachineOperand &MO = MI.getOperand(i-1);
if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
@@ -734,8 +733,9 @@
return 0;
}
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitDataProcessingInstruction(const MachineInstr &MI,
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitDataProcessingInstruction(
+ const MachineInstr &MI,
unsigned ImplicitRd,
unsigned ImplicitRn) {
const TargetInstrDesc &TID = MI.getDesc();
@@ -798,8 +798,9 @@
emitWordLE(Binary);
}
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitLoadStoreInstruction(const MachineInstr &MI,
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitLoadStoreInstruction(
+ const MachineInstr &MI,
unsigned ImplicitRd,
unsigned ImplicitRn) {
const TargetInstrDesc &TID = MI.getDesc();
@@ -873,9 +874,9 @@
emitWordLE(Binary);
}
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitMiscLoadStoreInstruction(const MachineInstr &MI,
- unsigned ImplicitRn) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitMiscLoadStoreInstruction(const MachineInstr &MI,
+ unsigned ImplicitRn) {
const TargetInstrDesc &TID = MI.getDesc();
unsigned Form = TID.TSFlags & ARMII::FormMask;
bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
@@ -957,8 +958,9 @@
return Binary;
}
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitLoadStoreMultipleInstruction(
+ const MachineInstr &MI) {
// Part of binary is determined by TableGn.
unsigned Binary = getBinaryCodeForInstr(MI);
@@ -990,8 +992,8 @@
emitWordLE(Binary);
}
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitMulFrmInstruction(const MachineInstr &MI) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitMulFrmInstruction(const MachineInstr &MI) {
const TargetInstrDesc &TID = MI.getDesc();
// Part of binary is determined by TableGn.
@@ -1028,8 +1030,8 @@
emitWordLE(Binary);
}
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitExtendInstruction(const MachineInstr &MI) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitExtendInstruction(const MachineInstr &MI) {
const TargetInstrDesc &TID = MI.getDesc();
// Part of binary is determined by TableGn.
@@ -1066,8 +1068,8 @@
emitWordLE(Binary);
}
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitMiscArithInstruction(const MachineInstr &MI) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitMiscArithInstruction(const MachineInstr &MI) {
const TargetInstrDesc &TID = MI.getDesc();
// Part of binary is determined by TableGn.
@@ -1105,8 +1107,8 @@
emitWordLE(Binary);
}
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitBranchInstruction(const MachineInstr &MI) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitBranchInstruction(const MachineInstr &MI) {
const TargetInstrDesc &TID = MI.getDesc();
if (TID.Opcode == ARM::TPsoft)
@@ -1124,8 +1126,8 @@
emitWordLE(Binary);
}
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitInlineJumpTable(unsigned JTIndex) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitInlineJumpTable(unsigned JTIndex) {
// Remember the base address of the inline jump table.
uintptr_t JTBase = MCE.getCurrentPCValue();
JTI->addJumpTableBaseAddr(JTIndex, JTBase);
@@ -1144,8 +1146,8 @@
}
}
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitMiscBranchInstruction(const MachineInstr &MI) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitMiscBranchInstruction(const MachineInstr &MI) {
const TargetInstrDesc &TID = MI.getDesc();
// Handle jump tables.
@@ -1225,8 +1227,8 @@
return Binary;
}
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitVFPArithInstruction(const MachineInstr &MI) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitVFPArithInstruction(const MachineInstr &MI) {
const TargetInstrDesc &TID = MI.getDesc();
// Part of binary is determined by TableGn.
@@ -1265,8 +1267,9 @@
emitWordLE(Binary);
}
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitVFPConversionInstruction(const MachineInstr &MI) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitVFPConversionInstruction(
+ const MachineInstr &MI) {
const TargetInstrDesc &TID = MI.getDesc();
unsigned Form = TID.TSFlags & ARMII::FormMask;
@@ -1322,8 +1325,8 @@
emitWordLE(Binary);
}
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
// Part of binary is determined by TableGn.
unsigned Binary = getBinaryCodeForInstr(MI);
@@ -1357,8 +1360,9 @@
emitWordLE(Binary);
}
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitVFPLoadStoreMultipleInstruction(
+ const MachineInstr &MI) {
// Part of binary is determined by TableGn.
unsigned Binary = getBinaryCodeForInstr(MI);
@@ -1392,8 +1396,8 @@
emitWordLE(Binary);
}
-template< class machineCodeEmitter>
-void Emitter< machineCodeEmitter>::emitMiscInstruction(const MachineInstr &MI) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitMiscInstruction(const MachineInstr &MI) {
// Part of binary is determined by TableGn.
unsigned Binary = getBinaryCodeForInstr(MI);
Modified: llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp?rev=72697&r1=72696&r2=72697&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp Mon Jun 1 14:57:37 2009
@@ -32,7 +32,7 @@
class AlphaCodeEmitter {
MachineCodeEmitter &MCE;
public:
- AlphaCodeEmitter( MachineCodeEmitter &mce) : MCE(mce) {}
+ AlphaCodeEmitter(MachineCodeEmitter &mce) : MCE(mce) {}
/// getBinaryCodeForInstr - This function, generated by the
/// CodeEmitterGenerator using TableGen, produces the binary encoding for
@@ -42,25 +42,25 @@
/// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
- unsigned getMachineOpValue(const MachineInstr &MI, const MachineOperand &MO);
+ unsigned getMachineOpValue(const MachineInstr &MI,
+ const MachineOperand &MO);
};
- template <class machineCodeEmitter>
+ template <class CodeEmitter>
class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass,
public AlphaCodeEmitter
{
const AlphaInstrInfo *II;
- TargetMachine &TM;
- machineCodeEmitter &MCE;
+ TargetMachine &TM;
+ CodeEmitter &MCE;
public:
static char ID;
- explicit Emitter(TargetMachine &tm, machineCodeEmitter &mce)
- : MachineFunctionPass(&ID), AlphaCodeEmitter( mce),
+ explicit Emitter(TargetMachine &tm, CodeEmitter &mce)
+ : MachineFunctionPass(&ID), AlphaCodeEmitter(mce),
II(0), TM(tm), MCE(mce) {}
- Emitter(TargetMachine &tm, machineCodeEmitter &mce,
- const AlphaInstrInfo& ii)
- : MachineFunctionPass(&ID), AlphaCodeEmitter( mce),
+ Emitter(TargetMachine &tm, CodeEmitter &mce, const AlphaInstrInfo& ii)
+ : MachineFunctionPass(&ID), AlphaCodeEmitter(mce),
II(&ii), TM(tm), MCE(mce) {}
bool runOnMachineFunction(MachineFunction &MF);
@@ -75,25 +75,25 @@
void emitBasicBlock(MachineBasicBlock &MBB);
};
- template <class machineCodeEmitter>
- char Emitter<machineCodeEmitter>::ID = 0;
+ template <class CodeEmitter>
+ char Emitter<CodeEmitter>::ID = 0;
}
-/// createAlphaCodeEmitterPass - Return a pass that emits the collected Alpha code
-/// to the specified MCE object.
+/// createAlphaCodeEmitterPass - Return a pass that emits the collected Alpha
+/// code to the specified MCE object.
-FunctionPass *llvm::createAlphaCodeEmitterPass( AlphaTargetMachine &TM,
+FunctionPass *llvm::createAlphaCodeEmitterPass(AlphaTargetMachine &TM,
MachineCodeEmitter &MCE) {
return new Emitter<MachineCodeEmitter>(TM, MCE);
}
-FunctionPass *llvm::createAlphaJITCodeEmitterPass( AlphaTargetMachine &TM,
- JITCodeEmitter &JCE) {
+FunctionPass *llvm::createAlphaJITCodeEmitterPass(AlphaTargetMachine &TM,
+ JITCodeEmitter &JCE) {
return new Emitter<JITCodeEmitter>(TM, JCE);
}
-template <class machineCodeEmitter>
-bool Emitter<machineCodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
+template <class CodeEmitter>
+bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
II = ((AlphaTargetMachine&)MF.getTarget()).getInstrInfo();
do {
@@ -105,8 +105,8 @@
return false;
}
-template <class machineCodeEmitter>
-void Emitter<machineCodeEmitter>::emitBasicBlock(MachineBasicBlock &MBB) {
+template <class CodeEmitter>
+void Emitter<CodeEmitter>::emitBasicBlock(MachineBasicBlock &MBB) {
MCE.StartMachineBasicBlock(&MBB);
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
I != E; ++I) {
@@ -165,7 +165,7 @@
}
unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI,
- const MachineOperand &MO) {
+ const MachineOperand &MO) {
unsigned rv = 0; // Return value; defaults to 0 for unhandled cases
// or things that get fixed up later by the JIT.
Modified: llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp?rev=72697&r1=72696&r2=72697&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp Mon Jun 1 14:57:37 2009
@@ -23,7 +23,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/Passes.h"
-#include "llvm/Support/Debug.h"
+#include "llvm/Support/Debug.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Target/TargetOptions.h"
using namespace llvm;
@@ -33,8 +33,8 @@
TargetMachine &TM;
MachineCodeEmitter &MCE;
public:
- PPCCodeEmitter( TargetMachine &tm, MachineCodeEmitter &mce) :
- TM( tm), MCE( mce) {}
+ PPCCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce):
+ TM(tm), MCE(mce) {}
/// getBinaryCodeForInstr - This function, generated by the
/// CodeEmitterGenerator using TableGen, produces the binary encoding for
@@ -44,7 +44,8 @@
/// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
- unsigned getMachineOpValue(const MachineInstr &MI, const MachineOperand &MO);
+ unsigned getMachineOpValue(const MachineInstr &MI,
+ const MachineOperand &MO);
/// MovePCtoLROffset - When/if we see a MovePCtoLR instruction, we record
/// its address in the function into this pointer.
@@ -52,12 +53,12 @@
void *MovePCtoLROffset;
};
- template <class machineCodeEmitter>
+ template <class CodeEmitter>
class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass,
public PPCCodeEmitter
{
TargetMachine &TM;
- machineCodeEmitter &MCE;
+ CodeEmitter &MCE;
void getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<MachineModuleInfo>();
@@ -66,8 +67,8 @@
public:
static char ID;
- Emitter(TargetMachine &tm, machineCodeEmitter &mce)
- : MachineFunctionPass(&ID), PPCCodeEmitter( tm, mce), TM(tm), MCE(mce) {}
+ Emitter(TargetMachine &tm, CodeEmitter &mce)
+ : MachineFunctionPass(&ID), PPCCodeEmitter(tm, mce), TM(tm), MCE(mce) {}
const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
@@ -84,24 +85,24 @@
unsigned getValueBit(int64_t Val, unsigned bit) { return (Val >> bit) & 1; }
};
- template <class machineCodeEmitter>
- char Emitter<machineCodeEmitter>::ID = 0;
+ template <class CodeEmitter>
+ char Emitter<CodeEmitter>::ID = 0;
}
/// createPPCCodeEmitterPass - Return a pass that emits the collected PPC code
/// to the specified MCE object.
FunctionPass *llvm::createPPCCodeEmitterPass(PPCTargetMachine &TM,
- MachineCodeEmitter &MCE) {
+ MachineCodeEmitter &MCE) {
return new Emitter<MachineCodeEmitter>(TM, MCE);
}
FunctionPass *llvm::createPPCJITCodeEmitterPass(PPCTargetMachine &TM,
- JITCodeEmitter &JCE) {
+ JITCodeEmitter &JCE) {
return new Emitter<JITCodeEmitter>(TM, JCE);
}
-template <class machineCodeEmitter>
-bool Emitter<machineCodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
+template <class CodeEmitter>
+bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
MF.getTarget().getRelocationModel() != Reloc::Static) &&
"JIT relocation model must be set to static or default!");
@@ -117,8 +118,8 @@
return false;
}
-template <class machineCodeEmitter>
-void Emitter<machineCodeEmitter>::emitBasicBlock(MachineBasicBlock &MBB) {
+template <class CodeEmitter>
+void Emitter<CodeEmitter>::emitBasicBlock(MachineBasicBlock &MBB) {
MCE.StartMachineBasicBlock(&MBB);
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=72697&r1=72696&r2=72697&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Mon Jun 1 14:57:37 2009
@@ -220,7 +220,8 @@
bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
- bool DumpAsm, MachineCodeEmitter &MCE) {
+ bool DumpAsm,
+ MachineCodeEmitter &MCE) {
// Machine code emitter pass for PowerPC.
PM.add(createPPCCodeEmitterPass(*this, MCE));
if (DumpAsm) {
@@ -234,7 +235,8 @@
bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
- bool DumpAsm, JITCodeEmitter &JCE) {
+ bool DumpAsm,
+ JITCodeEmitter &JCE) {
// Machine code emitter pass for PowerPC.
PM.add(createPPCJITCodeEmitterPass(*this, JCE));
if (DumpAsm) {
Modified: llvm/trunk/lib/Target/X86/X86.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=72697&r1=72696&r2=72697&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.h (original)
+++ llvm/trunk/lib/Target/X86/X86.h Mon Jun 1 14:57:37 2009
@@ -28,7 +28,8 @@
/// createX86ISelDag - This pass converts a legalized DAG into a
/// X86-specific DAG, ready for instruction scheduling.
///
-FunctionPass *createX86ISelDag(X86TargetMachine &TM, CodeGenOpt::Level OptLevel);
+FunctionPass *createX86ISelDag(X86TargetMachine &TM,
+ CodeGenOpt::Level OptLevel);
/// createX86FloatingPointStackifierPass - This function returns a pass which
/// converts floating point register references and pseudo instructions into
@@ -53,10 +54,10 @@
/// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
/// to the specified MCE object.
-FunctionPass *createX86CodeEmitterPass(
- X86TargetMachine &TM, MachineCodeEmitter &MCE);
-FunctionPass *createX86JITCodeEmitterPass(
- X86TargetMachine &TM, JITCodeEmitter &JCE);
+FunctionPass *createX86CodeEmitterPass(X86TargetMachine &TM,
+ MachineCodeEmitter &MCE);
+FunctionPass *createX86JITCodeEmitterPass(X86TargetMachine &TM,
+ JITCodeEmitter &JCE);
/// createX86EmitCodeToMemory - Returns a pass that converts a register
/// allocated function into raw machine code in a dynamically
@@ -64,8 +65,8 @@
///
FunctionPass *createEmitX86CodeToMemory();
-/// createX86MaxStackAlignmentCalculatorPass - This function returns a pass which
-/// calculates maximal stack alignment required for function
+/// createX86MaxStackAlignmentCalculatorPass - This function returns a pass
+/// which calculates maximal stack alignment required for function
///
FunctionPass *createX86MaxStackAlignmentCalculatorPass();
Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=72697&r1=72696&r2=72697&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Mon Jun 1 14:57:37 2009
@@ -36,22 +36,22 @@
STATISTIC(NumEmitted, "Number of machine instructions emitted");
namespace {
-template< class machineCodeEmitter>
+template<class CodeEmitter>
class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
const X86InstrInfo *II;
const TargetData *TD;
X86TargetMachine &TM;
- machineCodeEmitter &MCE;
+ CodeEmitter &MCE;
intptr_t PICBaseOffset;
bool Is64BitMode;
bool IsPIC;
public:
static char ID;
- explicit Emitter(X86TargetMachine &tm, machineCodeEmitter &mce)
+ explicit Emitter(X86TargetMachine &tm, CodeEmitter &mce)
: MachineFunctionPass(&ID), II(0), TD(0), TM(tm),
MCE(mce), PICBaseOffset(0), Is64BitMode(false),
IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
- Emitter(X86TargetMachine &tm, machineCodeEmitter &mce,
+ Emitter(X86TargetMachine &tm, CodeEmitter &mce,
const X86InstrInfo &ii, const TargetData &td, bool is64)
: MachineFunctionPass(&ID), II(&ii), TD(&td), TM(tm),
MCE(mce), PICBaseOffset(0), Is64BitMode(is64),
@@ -99,8 +99,8 @@
bool gvNeedsNonLazyPtr(const GlobalValue *GV);
};
-template< class machineCodeEmitter>
- char Emitter<machineCodeEmitter>::ID = 0;
+template<class CodeEmitter>
+ char Emitter<CodeEmitter>::ID = 0;
}
/// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
@@ -108,21 +108,19 @@
namespace llvm {
-FunctionPass *createX86CodeEmitterPass(
- X86TargetMachine &TM, MachineCodeEmitter &MCE)
-{
+FunctionPass *createX86CodeEmitterPass(X86TargetMachine &TM,
+ MachineCodeEmitter &MCE) {
return new Emitter<MachineCodeEmitter>(TM, MCE);
}
-FunctionPass *createX86JITCodeEmitterPass(
- X86TargetMachine &TM, JITCodeEmitter &JCE)
-{
+FunctionPass *createX86JITCodeEmitterPass(X86TargetMachine &TM,
+ JITCodeEmitter &JCE) {
return new Emitter<JITCodeEmitter>(TM, JCE);
}
} // end namespace llvm
-template< class machineCodeEmitter>
-bool Emitter<machineCodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
+template<class CodeEmitter>
+bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
@@ -156,8 +154,8 @@
/// necessary to resolve the address of this block later and emits a dummy
/// value.
///
-template< class machineCodeEmitter>
-void Emitter<machineCodeEmitter>::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
// Remember where this reference was and where it is to so we can
// deal with it later.
MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
@@ -168,8 +166,8 @@
/// emitGlobalAddress - Emit the specified address to the code stream assuming
/// this is part of a "take the address of a global" instruction.
///
-template< class machineCodeEmitter>
-void Emitter<machineCodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
intptr_t Disp /* = 0 */,
intptr_t PCAdj /* = 0 */,
bool NeedStub /* = false */,
@@ -195,8 +193,9 @@
/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
/// be emitted to the current location in the function, and allow it to be PC
/// relative.
-template< class machineCodeEmitter>
-void Emitter<machineCodeEmitter>::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
+ unsigned Reloc) {
intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0;
MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
Reloc, ES, RelocCST));
@@ -209,8 +208,8 @@
/// emitConstPoolAddress - Arrange for the address of an constant pool
/// to be emitted to the current location in the function, and allow it to be PC
/// relative.
-template< class machineCodeEmitter>
-void Emitter<machineCodeEmitter>::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
intptr_t Disp /* = 0 */,
intptr_t PCAdj /* = 0 */) {
intptr_t RelocCST = 0;
@@ -230,8 +229,8 @@
/// emitJumpTableAddress - Arrange for the address of a jump table to
/// be emitted to the current location in the function, and allow it to be PC
/// relative.
-template< class machineCodeEmitter>
-void Emitter<machineCodeEmitter>::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
intptr_t PCAdj /* = 0 */) {
intptr_t RelocCST = 0;
if (Reloc == X86::reloc_picrel_word)
@@ -247,8 +246,8 @@
MCE.emitWordLE(0);
}
-template< class machineCodeEmitter>
-unsigned Emitter<machineCodeEmitter>::getX86RegNum(unsigned RegNo) const {
+template<class CodeEmitter>
+unsigned Emitter<CodeEmitter>::getX86RegNum(unsigned RegNo) const {
return II->getRegisterInfo().getX86RegNum(RegNo);
}
@@ -258,24 +257,27 @@
return RM | (RegOpcode << 3) | (Mod << 6);
}
-template< class machineCodeEmitter>
-void Emitter<machineCodeEmitter>::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitRegModRMByte(unsigned ModRMReg,
+ unsigned RegOpcodeFld){
MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
}
-template< class machineCodeEmitter>
-void Emitter<machineCodeEmitter>::emitRegModRMByte(unsigned RegOpcodeFld) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitRegModRMByte(unsigned RegOpcodeFld) {
MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0));
}
-template< class machineCodeEmitter>
-void Emitter<machineCodeEmitter>::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitSIBByte(unsigned SS,
+ unsigned Index,
+ unsigned Base) {
// SIB byte is in the same format as the ModRMByte...
MCE.emitByte(ModRMByte(SS, Index, Base));
}
-template< class machineCodeEmitter>
-void Emitter<machineCodeEmitter>::emitConstant(uint64_t Val, unsigned Size) {
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitConstant(uint64_t Val, unsigned Size) {
// Output the constant in little endian byte order...
for (unsigned i = 0; i != Size; ++i) {
MCE.emitByte(Val & 255);
@@ -289,16 +291,16 @@
return Value == (signed char)Value;
}
-template< class machineCodeEmitter>
-bool Emitter<machineCodeEmitter>::gvNeedsNonLazyPtr(const GlobalValue *GV) {
+template<class CodeEmitter>
+bool Emitter<CodeEmitter>::gvNeedsNonLazyPtr(const GlobalValue *GV) {
// For Darwin, simulate the linktime GOT by using the same non-lazy-pointer
// mechanism as 32-bit mode.
return (!Is64BitMode || TM.getSubtarget<X86Subtarget>().isTargetDarwin()) &&
TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM, false);
}
-template< class machineCodeEmitter>
-void Emitter<machineCodeEmitter>::emitDisplacementField(const MachineOperand *RelocOp,
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitDisplacementField(const MachineOperand *RelocOp,
int DispVal, intptr_t PCAdj) {
// If this is a simple integer displacement that doesn't require a relocation,
// emit it now.
@@ -332,8 +334,8 @@
}
}
-template< class machineCodeEmitter>
-void Emitter<machineCodeEmitter>::emitMemModRMByte(const MachineInstr &MI,
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI,
unsigned Op, unsigned RegOpcodeField,
intptr_t PCAdj) {
const MachineOperand &Op3 = MI.getOperand(Op+3);
@@ -450,8 +452,8 @@
}
}
-template< class machineCodeEmitter>
-void Emitter<machineCodeEmitter>::emitInstruction(
+template<class CodeEmitter>
+void Emitter<CodeEmitter>::emitInstruction(
const MachineInstr &MI,
const TargetInstrDesc *Desc) {
DOUT << MI;
@@ -672,7 +674,8 @@
getX86RegNum(MI.getOperand(CurOp).getReg()));
CurOp += 2;
if (CurOp != NumOps)
- emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
+ emitConstant(MI.getOperand(CurOp++).getImm(),
+ X86InstrInfo::sizeOfImm(Desc));
break;
case X86II::MRMSrcMem: {
@@ -692,7 +695,8 @@
PCAdj);
CurOp += AddrOperands + 1;
if (CurOp != NumOps)
- emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
+ emitConstant(MI.getOperand(CurOp++).getImm(),
+ X86InstrInfo::sizeOfImm(Desc));
break;
}
Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=72697&r1=72696&r2=72697&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Mon Jun 1 14:57:37 2009
@@ -116,7 +116,7 @@
return getJITMatchQuality()/2;
}
-X86_32TargetMachine::X86_32TargetMachine(const Module &M, const std::string &FS)
+X86_32TargetMachine::X86_32TargetMachine(const Module &M, const std::string &FS)
: X86TargetMachine(M, FS, false) {
}
@@ -221,7 +221,8 @@
bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
- bool DumpAsm, MachineCodeEmitter &MCE) {
+ bool DumpAsm,
+ MachineCodeEmitter &MCE) {
// FIXME: Move this to TargetJITInfo!
// On Darwin, do not override 64-bit setting made in X86TargetMachine().
if (DefRelocModel == Reloc::Default &&
@@ -250,7 +251,8 @@
bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
- bool DumpAsm, JITCodeEmitter &JCE) {
+ bool DumpAsm,
+ JITCodeEmitter &JCE) {
// FIXME: Move this to TargetJITInfo!
// On Darwin, do not override 64-bit setting made in X86TargetMachine().
if (DefRelocModel == Reloc::Default &&
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