[llvm-commits] [llvm] r72494 - in /llvm/trunk/lib/Target: PowerPC/PPCISelLowering.cpp X86/X86ISelLowering.cpp

[Chris Lattner]

On May 27, 2009, at 1:39 PM, Eli Friedman wrote:

> Author: efriedma
> Date: Wed May 27 15:39:00 2009
> New Revision: 72494
>
> URL: http://llvm.org/viewvc/llvm-project?rev=72494&view=rev
> Log:
> Ger rid of some dead code.

Is X86's InstructionSelectPreprocess dead now too?

-Chris

>
>
>
> Modified:
>    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
>    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=72494&r1=72493&r2=72494&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Wed May 27  
> 15:39:00 2009
> @@ -71,9 +71,6 @@
>   setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
>   setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
>
> -  // Shortening conversions involving ppcf128 get expanded (2 regs - 
> > 1 reg)
> -  setConvertAction(MVT::ppcf128, MVT::f64, Expand);
> -  setConvertAction(MVT::ppcf128, MVT::f32, Expand);
>   // This is used in the ppcf128->int sequence.  Note it has  
> different semantics
>   // from FP_ROUND:  that rounds to nearest, this rounds to zero.
>   setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=72494&r1=72493&r2=72494&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed May 27  
> 15:39:00 2009
> @@ -55,8 +55,6 @@
>   X86ScalarSSEf32 = Subtarget->hasSSE1();
>   X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
>
> -  bool Fast = false;
> -
>   RegInfo = TM.getRegisterInfo();
>   TD = getTargetData();
>
> @@ -410,16 +408,6 @@
>     // cases we handle.
>     addLegalFPImmediate(APFloat(+0.0)); // xorpd
>     addLegalFPImmediate(APFloat(+0.0f)); // xorps
> -
> -    // Floating truncations from f80 and extensions to f80 go  
> through memory.
> -    // If optimizing, we lie about this though and handle it in
> -    // InstructionSelectPreprocess so that dagcombine2 can hack on  
> these.
> -    if (Fast) {
> -      setConvertAction(MVT::f32, MVT::f80, Expand);
> -      setConvertAction(MVT::f64, MVT::f80, Expand);
> -      setConvertAction(MVT::f80, MVT::f32, Expand);
> -      setConvertAction(MVT::f80, MVT::f64, Expand);
> -    }
>   } else if (!UseSoftFloat && X86ScalarSSEf32) {
>     // Use SSE for f32, x87 for f64.
>     // Set up the FP register classes.
> @@ -449,18 +437,6 @@
>     addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
>     addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
>
> -    // SSE <-> X87 conversions go through memory.  If optimizing,  
> we lie about
> -    // this though and handle it in InstructionSelectPreprocess so  
> that
> -    // dagcombine2 can hack on these.
> -    if (Fast) {
> -      setConvertAction(MVT::f32, MVT::f64, Expand);
> -      setConvertAction(MVT::f32, MVT::f80, Expand);
> -      setConvertAction(MVT::f80, MVT::f32, Expand);
> -      setConvertAction(MVT::f64, MVT::f32, Expand);
> -      // And x87->x87 truncations also.
> -      setConvertAction(MVT::f80, MVT::f64, Expand);
> -    }
> -
>     if (!UnsafeFPMath) {
>       setOperationAction(ISD::FSIN           , MVT::f64  , Expand);
>       setOperationAction(ISD::FCOS           , MVT::f64  , Expand);
> @@ -476,15 +452,6 @@
>     setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
>     setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
>
> -    // Floating truncations go through memory.  If optimizing, we  
> lie about
> -    // this though and handle it in InstructionSelectPreprocess so  
> that
> -    // dagcombine2 can hack on these.
> -    if (Fast) {
> -      setConvertAction(MVT::f80, MVT::f32, Expand);
> -      setConvertAction(MVT::f64, MVT::f32, Expand);
> -      setConvertAction(MVT::f80, MVT::f64, Expand);
> -    }
> -
>     if (!UnsafeFPMath) {
>       setOperationAction(ISD::FSIN           , MVT::f64  , Expand);
>       setOperationAction(ISD::FCOS           , MVT::f64  , Expand);
>
>
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