[llvm-commits] [llvm] r72045 - /llvm/trunk/lib/Target/X86/X86InstrInfo.td
Dale Johannesen
dalej at apple.com
Tue May 19 09:51:05 PDT 2009
On May 19, 2009, at 2:25 AMPDT, Nicolas Geoffray wrote:
> Hi Dale,
>
> Dale Johannesen wrote:
>> Author: johannes
>> Date: Mon May 18 16:41:59 2009
>> New Revision: 72045
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=72045&view=rev
>> Log:
>> Add OpSize to 16-bit ADC and SBB.
>>
>
> What is OpSize? This patch is causing lots of memory errors in VMKit,
> I'm not sure why.
It indicates the operand size prefix, 0x66, should be emitted. It is
normal on 16-bit operations.
> Does the JIT in LLVM understand OpSize?
Yes, in fact it's entirely for use by the JIT. See XCodeEmitter.
Are you sure it's this patch? I'd be surprised if these new patterns
were getting matched at all right now.
> Thanks,
> Nicolas
>
>>
>> Modified:
>> llvm/trunk/lib/Target/X86/X86InstrInfo.td
>>
>> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=72045&r1=72044&r2=72045&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
>> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon May 18 16:41:59
>> 2009
>> @@ -2280,7 +2280,7 @@
>> def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
>> (ins GR16:$src1, GR16:$src2),
>> "adc{w}\t{$src2, $dst|$dst, $src2}",
>> - [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>;
>> + [(set GR16:$dst, (adde GR16:$src1,
>> GR16:$src2))]>, OpSize;
>> def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
>> (ins GR32:$src1, GR32:$src2),
>> "adc{l}\t{$src2, $dst|$dst, $src2}",
>> @@ -2293,7 +2293,8 @@
>> def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
>> (ins GR16:$src1, i16mem:$src2),
>> "adc{w}\t{$src2, $dst|$dst, $src2}",
>> - [(set GR16:$dst, (adde GR16:$src1, (load addr:
>> $src2)))]>;
>> + [(set GR16:$dst, (adde GR16:$src1, (load addr:
>> $src2)))]>,
>> + OpSize;
>> def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
>> (ins GR32:$src1, i32mem:$src2),
>> "adc{l}\t{$src2, $dst|$dst, $src2}",
>> @@ -2304,11 +2305,12 @@
>> def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
>> (ins GR16:$src1, i16imm:$src2),
>> "adc{w}\t{$src2, $dst|$dst, $src2}",
>> - [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>;
>> + [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>,
>> OpSize;
>> def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
>> (ins GR16:$src1, i16i8imm:$src2),
>> "adc{w}\t{$src2, $dst|$dst, $src2}",
>> - [(set GR16:$dst, (adde GR16:$src1,
>> i16immSExt8:$src2))]>;
>> + [(set GR16:$dst, (adde GR16:$src1,
>> i16immSExt8:$src2))]>,
>> + OpSize;
>> def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
>> (ins GR32:$src1, i32imm:$src2),
>> "adc{l}\t{$src2, $dst|$dst, $src2}",
>> @@ -2324,7 +2326,8 @@
>> [(store (adde (load addr:$dst), GR8:$src2), addr:
>> $dst)]>;
>> def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst,
>> GR16:$src2),
>> "adc{w}\t{$src2, $dst|$dst, $src2}",
>> - [(store (adde (load addr:$dst), GR16:$src2),
>> addr:$dst)]>;
>> + [(store (adde (load addr:$dst), GR16:$src2),
>> addr:$dst)]>,
>> + OpSize;
>> def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst,
>> GR32:$src2),
>> "adc{l}\t{$src2, $dst|$dst, $src2}",
>> [(store (adde (load addr:$dst), GR32:$src2),
>> addr:$dst)]>;
>> @@ -2333,10 +2336,12 @@
>> [(store (adde (loadi8 addr:$dst), imm:$src2),
>> addr:$dst)]>;
>> def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:
>> $src2),
>> "adc{w}\t{$src2, $dst|$dst, $src2}",
>> - [(store (adde (loadi16 addr:$dst), imm:$src2),
>> addr:$dst)]>;
>> + [(store (adde (loadi16 addr:$dst), imm:$src2),
>> addr:$dst)]>,
>> + OpSize;
>> def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst,
>> i16i8imm :$src2),
>> "adc{w}\t{$src2, $dst|$dst, $src2}",
>> - [(store (adde (load addr:$dst), i16immSExt8:$src2),
>> addr:$dst)]>;
>> + [(store (adde (load addr:$dst), i16immSExt8:$src2),
>> addr:$dst)]>,
>> + OpSize;
>> def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:
>> $src2),
>> "adc{l}\t{$src2, $dst|$dst, $src2}",
>> [(store (adde (loadi32 addr:$dst), imm:$src2),
>> addr:$dst)]>;
>> @@ -2452,7 +2457,7 @@
>> def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
>> (ins GR16:$src1, GR16:$src2),
>> "sbb{w}\t{$src2, $dst|$dst, $src2}",
>> - [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>;
>> + [(set GR16:$dst, (sube GR16:$src1,
>> GR16:$src2))]>, OpSize;
>> def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
>> (ins GR32:$src1, GR32:$src2),
>> "sbb{l}\t{$src2, $dst|$dst, $src2}",
>> @@ -2464,7 +2469,8 @@
>> [(store (sube (load addr:$dst), GR8:$src2), addr:
>> $dst)]>;
>> def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst,
>> GR16:$src2),
>> "sbb{w}\t{$src2, $dst|$dst, $src2}",
>> - [(store (sube (load addr:$dst), GR16:$src2),
>> addr:$dst)]>;
>> + [(store (sube (load addr:$dst), GR16:$src2),
>> addr:$dst)]>,
>> + OpSize;
>> def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst,
>> GR32:$src2),
>> "sbb{l}\t{$src2, $dst|$dst, $src2}",
>> [(store (sube (load addr:$dst), GR32:$src2),
>> addr:$dst)]>;
>> @@ -2473,10 +2479,12 @@
>> [(store (sube (loadi8 addr:$dst), imm:$src2),
>> addr:$dst)]>;
>> def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:
>> $src2),
>> "sbb{w}\t{$src2, $dst|$dst, $src2}",
>> - [(store (sube (loadi16 addr:$dst), imm:$src2),
>> addr:$dst)]>;
>> + [(store (sube (loadi16 addr:$dst), imm:$src2),
>> addr:$dst)]>,
>> + OpSize;
>> def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst,
>> i16i8imm :$src2),
>> "sbb{w}\t{$src2, $dst|$dst, $src2}",
>> - [(store (sube (load addr:$dst), i16immSExt8:$src2),
>> addr:$dst)]>;
>> + [(store (sube (load addr:$dst), i16immSExt8:$src2),
>> addr:$dst)]>,
>> + OpSize;
>> def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:
>> $src2),
>> "sbb{l}\t{$src2, $dst|$dst, $src2}",
>> [(store (sube (loadi32 addr:$dst), imm:$src2),
>> addr:$dst)]>;
>> @@ -2490,7 +2498,8 @@
>> def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
>> (ins GR16:$src1, i16mem:$src2),
>> "sbb{w}\t{$src2, $dst|$dst, $src2}",
>> - [(set GR16:$dst, (sube GR16:$src1, (load addr:
>> $src2)))]>;
>> + [(set GR16:$dst, (sube GR16:$src1, (load addr:
>> $src2)))]>,
>> + OpSize;
>> def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
>> (ins GR32:$src1, i32mem:$src2),
>> "sbb{l}\t{$src2, $dst|$dst, $src2}",
>> @@ -2501,11 +2510,12 @@
>> def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
>> (ins GR16:$src1, i16imm:$src2),
>> "sbb{w}\t{$src2, $dst|$dst, $src2}",
>> - [(set GR16:$dst, (sube GR16:$src1, imm:
>> $src2))]>;
>> + [(set GR16:$dst, (sube GR16:$src1, imm:
>> $src2))]>, OpSize;
>> def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
>> (ins GR16:$src1, i16i8imm:$src2),
>> "sbb{w}\t{$src2, $dst|$dst, $src2}",
>> - [(set GR16:$dst, (sube GR16:$src1,
>> i16immSExt8:$src2))]>;
>> + [(set GR16:$dst, (sube GR16:$src1,
>> i16immSExt8:$src2))]>,
>> + OpSize;
>> def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
>> (ins GR32:$src1, i32imm:$src2),
>> "sbb{l}\t{$src2, $dst|$dst, $src2}",
>>
>>
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