[llvm-commits] [llvm] r71933 - /llvm/trunk/lib/CodeGen/MachineVerifier.cpp

[Jakob Stoklund Olesen]

Author: stoklund
Date: Sat May 16 02:25:20 2009
New Revision: 71933

URL: http://llvm.org/viewvc/llvm-project?rev=71933&view=rev
Log:
Verify that explicit definitions in the TargetInstrDesc are matched by
explicit register define operands.

Modified:
    llvm/trunk/lib/CodeGen/MachineVerifier.cpp

Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=71933&r1=71932&r2=71933&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Sat May 16 02:25:20 2009
@@ -327,6 +327,18 @@
 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum)
 {
   const MachineInstr *MI = MO->getParent();
+  const TargetInstrDesc &TI = MI->getDesc();
+
+  // The first TI.NumDefs operands must be explicit register defines
+  if (MONum < TI.getNumDefs()) {
+    if (!MO->isReg())
+      report("Explicit definition must be a register", MO, MONum);
+    else if (!MO->isDef())
+      report("Explicit definition marked as use", MO, MONum);
+    else if (MO->isImplicit())
+      report("Explicit definition marked as implicit", MO, MONum);
+  }
+
   switch (MO->getType()) {
   case MachineOperand::MO_Register: {
     const unsigned Reg = MO->getReg();
@@ -374,7 +386,6 @@
     }
 
     // Check register classes.
-    const TargetInstrDesc &TI = MI->getDesc();
     if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
       const TargetOperandInfo &TOI = TI.OpInfo[MONum];
       unsigned SubIdx = MO->getSubReg();