[llvm-commits] [llvm] r71098 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll
Evan Cheng
evan.cheng at apple.com
Wed May 6 11:25:02 PDT 2009
Author: evancheng
Date: Wed May 6 13:25:01 2009
New Revision: 71098
URL: http://llvm.org/viewvc/llvm-project?rev=71098&view=rev
Log:
Do not use register as base ptr of pre- and post- inc/dec load / store nodes.
Added:
llvm/trunk/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=71098&r1=71097&r2=71098&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed May 6 13:25:01 2009
@@ -4536,7 +4536,7 @@
// Check #1. Preinc'ing a frame index would require copying the stack pointer
// (plus the implicit offset) to a register to preinc anyway.
- if (isa<FrameIndexSDNode>(BasePtr))
+ if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
return false;
// Check #2.
@@ -4663,6 +4663,9 @@
// nor a successor of N. Otherwise, if Op is folded that would
// create a cycle.
+ if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
+ continue;
+
// Check for #1.
bool TryNext = false;
for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
Added: llvm/trunk/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll?rev=71098&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll Wed May 6 13:25:01 2009
@@ -0,0 +1,11 @@
+; RUN: llvm-as < %s | llc -mtriple=arm-linuxeabi-unknown-gnu -mattr=+v6
+; PR4166
+
+ %"byte[]" = type { i32, i8* }
+ %tango.time.Time.Time = type { i64 }
+
+define fastcc void @t() {
+entry:
+ %tmp28 = call fastcc i1 null(i32* null, %"byte[]" undef, %"byte[]" undef, %tango.time.Time.Time* byval null) ; <i1> [#uses=0]
+ ret void
+}
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