[llvm-commits] [llvm] r70782 - /llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td

[Anton Korobeynikov]

Author: asl
Date: Sun May  3 10:50:18 2009
New Revision: 70782

URL: http://llvm.org/viewvc/llvm-project?rev=70782&view=rev
Log:
Handle implicit zext in a better way. Shamelessly stolen from x86 backend.
Thanks for Dan Gohman for suggestion!

Modified:
    llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td

Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td?rev=70782&r1=70781&r2=70782&view=diff

==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td Sun May  3 10:50:18 2009
@@ -209,6 +209,22 @@
                 "mov.b\t{$src, $dst}",
                 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>;
 
+// Any instruction that defines a 8-bit result leaves the high half of the
+// register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
+// be copying from a truncate, but any other 8-bit operation will zero-extend
+// up to 16 bits.
+def def8 : PatLeaf<(i8 GR8:$src), [{
+  return N->getOpcode() != ISD::TRUNCATE &&
+         N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&
+         N->getOpcode() != ISD::CopyFromReg;
+}]>;
+
+// In the case of a 8-bit def that is known to implicitly zero-extend,
+// we can use a SUBREG_TO_REG.
+def : Pat<(i16 (zext def8:$src)),
+          (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>;
+
+
 def MOV8mi  : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
                 "mov.b\t{$src, $dst}",
                 [(store (i8 imm:$src), addr:$dst)]>;