[llvm-commits] [llvm] r70764 - in /llvm/trunk: include/llvm/CodeGen/RuntimeLibcalls.h lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/TargetLowering.cpp

[Anton Korobeynikov]

Author: asl
Date: Sun May  3 08:18:16 2009
New Revision: 70764

URL: http://llvm.org/viewvc/llvm-project?rev=70764&view=rev
Log:
Properly handle sdiv / udiv / srem / urem libcalls

Modified:
    llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Modified: llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h?rev=70764&r1=70763&r2=70764&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h (original)
+++ llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h Sun May  3 08:18:16 2009
@@ -45,15 +45,19 @@
     MUL_I32,
     MUL_I64,
     MUL_I128,
+    SDIV_I16,
     SDIV_I32,
     SDIV_I64,
     SDIV_I128,
+    UDIV_I16,
     UDIV_I32,
     UDIV_I64,
     UDIV_I128,
+    SREM_I16,
     SREM_I32,
     SREM_I64,
     SREM_I128,
+    UREM_I16,
     UREM_I32,
     UREM_I64,
     UREM_I128,

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=70764&r1=70763&r2=70764&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sun May  3 08:18:16 2009
@@ -3308,16 +3308,20 @@
       switch (Node->getOpcode()) {
       case ISD::UDIV:
       case ISD::SDIV:
-        if (VT == MVT::i32) {
-          LC = Node->getOpcode() == ISD::UDIV
-               ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
-          isSigned = Node->getOpcode() == ISD::SDIV;
-        }
-        break;
+       isSigned = Node->getOpcode() == ISD::SDIV;
+       if (VT == MVT::i16)
+         LC = (isSigned ? RTLIB::SDIV_I16  : RTLIB::UDIV_I16);
+       else if (VT == MVT::i32)
+         LC = (isSigned ? RTLIB::SDIV_I32  : RTLIB::UDIV_I32);
+       else if (VT == MVT::i64)
+         LC = (isSigned ? RTLIB::SDIV_I64  : RTLIB::UDIV_I64);
+       else if (VT == MVT::i128)
+         LC = (isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128);
+       break;
       case ISD::MUL:
         if (VT == MVT::i16)
           LC = RTLIB::MUL_I16;
-        if (VT == MVT::i32)
+        else if (VT == MVT::i32)
           LC = RTLIB::MUL_I32;
         else if (VT == MVT::i64)
           LC = RTLIB::MUL_I64;

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=70764&r1=70763&r2=70764&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Sun May  3 08:18:16 2009
@@ -67,15 +67,19 @@
   Names[RTLIB::MUL_I32] = "__mulsi3";
   Names[RTLIB::MUL_I64] = "__muldi3";
   Names[RTLIB::MUL_I128] = "__multi3";
+  Names[RTLIB::SDIV_I16] = "__divhi3";
   Names[RTLIB::SDIV_I32] = "__divsi3";
   Names[RTLIB::SDIV_I64] = "__divdi3";
   Names[RTLIB::SDIV_I128] = "__divti3";
+  Names[RTLIB::UDIV_I32] = "__udivhi3";
   Names[RTLIB::UDIV_I32] = "__udivsi3";
   Names[RTLIB::UDIV_I64] = "__udivdi3";
   Names[RTLIB::UDIV_I128] = "__udivti3";
+  Names[RTLIB::SREM_I16] = "__modhi3";
   Names[RTLIB::SREM_I32] = "__modsi3";
   Names[RTLIB::SREM_I64] = "__moddi3";
   Names[RTLIB::SREM_I128] = "__modti3";
+  Names[RTLIB::UREM_I16] = "__umodsi3";
   Names[RTLIB::UREM_I32] = "__umodsi3";
   Names[RTLIB::UREM_I64] = "__umoddi3";
   Names[RTLIB::UREM_I128] = "__umodti3";