[llvm-commits] [llvm] r70719 - /llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td
Anton Korobeynikov
asl at math.spbu.ru
Sun May 3 06:04:41 PDT 2009
Author: asl
Date: Sun May 3 08:04:41 2009
New Revision: 70719
URL: http://llvm.org/viewvc/llvm-project?rev=70719&view=rev
Log:
Add reg-imm variants
Modified:
llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td
Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td?rev=70719&r1=70718&r2=70719&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td Sun May 3 08:04:41 2009
@@ -77,13 +77,26 @@
"add.w\t{$src2, $dst|$dst, $src2}",
[(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
(implicit SR)]>;
+}
+
+def ADD16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
+ "add.w\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
+ (implicit SR)]>;
let Uses = [SR] in {
+
+let isCommutable = 1 in { // X = ADDC Y, Z == X = ADDC Z, Y
def ADC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
"addc.w\t{$src2, $dst|$dst, $src2}",
[(set GR16:$dst, (adde GR16:$src1, GR16:$src2)),
(implicit SR)]>;
-}
+} // isCommutable
+
+def ADC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
+ "addc.w\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (adde GR16:$src1, imm:$src2)),
+ (implicit SR)]>;
}
let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
@@ -93,24 +106,44 @@
(implicit SR)]>;
}
-let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
+def AND16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
+ "and.w\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
+ (implicit SR)]>;
+
+let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
def XOR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
"xor.w\t{$src2, $dst|$dst, $src2}",
[(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
(implicit SR)]>;
}
+def XOR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
+ "xor.w\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
+ (implicit SR)]>;
+
def SUB16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
"sub.w\t{$src2, $dst|$dst, $src2}",
[(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
(implicit SR)]>;
+def SUB16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
+ "sub.w\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
+ (implicit SR)]>;
+
let Uses = [SR] in {
def SBC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
"subc.w\t{$src2, $dst|$dst, $src2}",
[(set GR16:$dst, (sube GR16:$src1, GR16:$src2)),
(implicit SR)]>;
+
+def SBC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
+ "subc.w\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (sube GR16:$src1, imm:$src2)),
+ (implicit SR)]>;
}
// FIXME: Provide proper encoding!
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