[llvm-commits] [llvm] r70712 - /llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td

[Anton Korobeynikov]

Author: asl
Date: Sun May  3 08:02:39 2009
New Revision: 70712

URL: http://llvm.org/viewvc/llvm-project?rev=70712&view=rev
Log:
Add simple reg-reg add.

Modified:
    llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td

Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td?rev=70712&r1=70711&r2=70712&view=diff

==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td Sun May  3 08:02:39 2009
@@ -60,3 +60,17 @@
                      "mov.w\t{$src, $dst|$dst, $src}",
                      [(set GR16:$dst, imm:$src)]>;
 }
+
+//===----------------------------------------------------------------------===//
+// Arithmetic Instructions
+
+let Defs = [SR] in {
+let isCommutable = 1 in { // X = ADD Y, Z  == X = ADD Z, Y
+
+// FIXME: Provide proper encoding!
+def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+                     "add.w\t{$src2, $dst|$dst, $src2}",
+                     [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
+                      (implicit SR)]>;
+}
+}