[llvm-commits] [llvm] r70710 - in /llvm/trunk/lib/Target/MSP430: MSP430AsmPrinter.cpp MSP430ISelLowering.cpp MSP430InstrInfo.cpp MSP430InstrInfo.h MSP430InstrInfo.td MSP430RegisterInfo.cpp MSP430RegisterInfo.td
Anton Korobeynikov
asl at math.spbu.ru
Sun May 3 06:02:04 PDT 2009
Author: asl
Date: Sun May 3 08:02:04 2009
New Revision: 70710
URL: http://llvm.org/viewvc/llvm-project?rev=70710&view=rev
Log:
Add code enough for emission of reg-reg and reg-imm moves. This allows us to compile "ret i16 0" properly!
Modified:
llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpp
llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp
llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h
llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td
llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp
llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td
Modified: llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpp?rev=70710&r1=70709&r2=70710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpp Sun May 3 08:02:04 2009
@@ -47,6 +47,7 @@
return "MSP430 Assembly Printer";
}
+ void printOperand(const MachineInstr *MI, int OpNum);
bool printInstruction(const MachineInstr *MI); // autogenerated.
void printMachineInstruction(const MachineInstr * MI);
bool runOnMachineFunction(MachineFunction &F);
@@ -108,7 +109,7 @@
return false;
}
-void MSP430AsmPrinter::printMachineInstruction(const MachineInstr * MI) {
+void MSP430AsmPrinter::printMachineInstruction(const MachineInstr *MI) {
++EmittedInsts;
// Call the autogenerated instruction printer routines.
@@ -117,3 +118,23 @@
assert(0 && "Should not happen");
}
+
+void MSP430AsmPrinter::printOperand(const MachineInstr *MI, int OpNum) {
+ const MachineOperand &MO = MI->getOperand(OpNum);
+ switch (MO.getType()) {
+ case MachineOperand::MO_Register:
+ if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
+ O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
+ else
+ assert(0 && "not implemented");
+ break;
+ case MachineOperand::MO_Immediate:
+ O << "#" << MO.getImm();
+ break;
+ case MachineOperand::MO_MachineBasicBlock:
+ printBasicBlockLabel(MO.getMBB());
+ break;
+ default:
+ assert(0 && "Not implemented yet!");
+ }
+}
Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp?rev=70710&r1=70709&r2=70710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp Sun May 3 08:02:04 2009
@@ -39,7 +39,7 @@
TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
// Set up the register classes.
- addRegisterClass(MVT::i16, MSP430::MSP430RegsRegisterClass);
+ addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
// Compute derived properties from the register classes
computeRegisterProperties();
@@ -111,7 +111,7 @@
abort();
case MVT::i16:
unsigned VReg =
- RegInfo.createVirtualRegister(MSP430::MSP430RegsRegisterClass);
+ RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg);
SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp?rev=70710&r1=70709&r2=70710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp Sun May 3 08:02:04 2009
@@ -26,3 +26,40 @@
MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm)
: TargetInstrInfoImpl(MSP430Insts, array_lengthof(MSP430Insts)),
RI(*this), TM(tm) {}
+
+bool MSP430InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I,
+ unsigned DestReg, unsigned SrcReg,
+ const TargetRegisterClass *DestRC,
+ const TargetRegisterClass *SrcRC) const {
+ if (DestRC != SrcRC) {
+ // Not yet supported!
+ return false;
+ }
+
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (I != MBB.end()) DL = I->getDebugLoc();
+
+ BuildMI(MBB, I, DL, get(MSP430::MOV16rr), DestReg).addReg(SrcReg);
+ return true;
+}
+
+bool
+MSP430InstrInfo::isMoveInstr(const MachineInstr& MI,
+ unsigned &SrcReg, unsigned &DstReg,
+ unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
+ SrcSubIdx = DstSubIdx = 0; // No sub-registers yet.
+
+ switch (MI.getOpcode()) {
+ default:
+ return false;
+ case MSP430::MOV16rr:
+ assert(MI.getNumOperands() >= 2 &&
+ MI.getOperand(0).isReg() &&
+ MI.getOperand(1).isReg() &&
+ "invalid register-register move instruction");
+ SrcReg = MI.getOperand(1).getReg();
+ DstReg = MI.getOperand(0).getReg();
+ return true;
+ }
+}
Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h?rev=70710&r1=70709&r2=70710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h Sun May 3 08:02:04 2009
@@ -32,6 +32,15 @@
/// always be able to get register info as well (through this method).
///
virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
+
+ bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+ unsigned DestReg, unsigned SrcReg,
+ const TargetRegisterClass *DestRC,
+ const TargetRegisterClass *SrcRC) const;
+
+ bool isMoveInstr(const MachineInstr& MI,
+ unsigned &SrcReg, unsigned &DstReg,
+ unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
};
}
Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td?rev=70710&r1=70709&r2=70710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td Sun May 3 08:02:04 2009
@@ -41,5 +41,22 @@
// FIXME: Provide proper encoding!
let isReturn = 1, isTerminator = 1 in {
- def RETI: Pseudo<(outs), (ins), "reti", [(retflag)]>;
+ def RETI : Pseudo<(outs), (ins), "reti", [(retflag)]>;
+}
+
+//===----------------------------------------------------------------------===//
+// Move Instructions
+
+// FIXME: Provide proper encoding!
+let neverHasSideEffects = 1 in {
+def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
+ "mov.w\t{$src, $dst|$dst, $src}",
+ []>;
+}
+
+// FIXME: Provide proper encoding!
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
+def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
+ "mov.w\t{$src, $dst|$dst, $src}",
+ [(set GR16:$dst, imm:$src)]>;
}
Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp?rev=70710&r1=70709&r2=70710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp Sun May 3 08:02:04 2009
@@ -42,10 +42,10 @@
const TargetRegisterClass* const*
MSP430RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
- &MSP430::MSP430RegsRegClass, &MSP430::MSP430RegsRegClass,
- &MSP430::MSP430RegsRegClass, &MSP430::MSP430RegsRegClass,
- &MSP430::MSP430RegsRegClass, &MSP430::MSP430RegsRegClass,
- &MSP430::MSP430RegsRegClass, &MSP430::MSP430RegsRegClass,
+ &MSP430::GR16RegClass, &MSP430::GR16RegClass,
+ &MSP430::GR16RegClass, &MSP430::GR16RegClass,
+ &MSP430::GR16RegClass, &MSP430::GR16RegClass,
+ &MSP430::GR16RegClass, &MSP430::GR16RegClass,
0
};
Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td?rev=70710&r1=70709&r2=70710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td Sun May 3 08:02:04 2009
@@ -37,7 +37,9 @@
def R14 : MSP430Reg<14, "R14">;
def R15 : MSP430Reg<15, "R15">;
-def MSP430Regs : RegisterClass<"MSP430", [i16], 16,
+// FIXME: we need subregs & special handling for 8 bit stuff
+
+def GR16 : RegisterClass<"MSP430", [i16], 16,
// Volatile registers
[R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
// Frame pointer, sometimes allocable
@@ -49,8 +51,8 @@
iterator allocation_order_end(const MachineFunction &MF) const;
}];
let MethodBodies = [{
- MSP430RegsClass::iterator
- MSP430RegsClass::allocation_order_end(const MachineFunction &MF) const {
+ GR16Class::iterator
+ GR16Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetRegisterInfo *RI = TM.getRegisterInfo();
// Depending on whether the function uses frame pointer or not, last 5 or 4
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