[llvm-commits] [llvm] r70701 - in /llvm/trunk/lib/Target/MSP430: MSP430RegisterInfo.cpp MSP430RegisterInfo.td

[Anton Korobeynikov]

Author: asl
Date: Sun May  3 07:59:16 2009
New Revision: 70701

URL: http://llvm.org/viewvc/llvm-project?rev=70701&view=rev
Log:
Fix register names, fix register allocation order, handle frame pointer.

Modified:
    llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp
    llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td

Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp?rev=70701&r1=70700&r2=70701&view=diff

==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp Sun May  3 07:59:16 2009
@@ -15,6 +15,8 @@
 
 #include "MSP430.h"
 #include "MSP430RegisterInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/Target/TargetMachine.h"
 #include "llvm/ADT/BitVector.h"
 
 using namespace llvm;

Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td?rev=70701&r1=70700&r2=70701&view=diff

==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td Sun May  3 07:59:16 2009
@@ -20,11 +20,11 @@
 //  Registers
 //===----------------------------------------------------------------------===//
 
-def PC  : MSP430Reg<0,  "PC">;
-def SP  : MSP430Reg<1,  "SP">;
-def SR  : MSP430Reg<2,  "SR">;
-def CG  : MSP430Reg<3,  "CG">;
-def R4  : MSP430Reg<4,  "R4">;
+def PC  : MSP430Reg<0,  "R0">;
+def SP  : MSP430Reg<1,  "R1">;
+def SR  : MSP430Reg<2,  "R2">;
+def CG  : MSP430Reg<3,  "R3">;
+def FP  : MSP430Reg<4,  "R4">;
 def R5  : MSP430Reg<5,  "R5">;
 def R6  : MSP430Reg<6,  "R6">;
 def R7  : MSP430Reg<7,  "R7">;
@@ -38,10 +38,12 @@
 def R15 : MSP430Reg<15, "R15">;
 
 def MSP430Regs : RegisterClass<"MSP430", [i16], 16,
-  // Volatile registers
-  [R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15,
-  // Volatile, but not allocable
-  PC, SP, SR, CG]>
+   // Volatile registers
+  [R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
+   // Frame pointer, sometimes allocable
+   FP,
+   // Volatile, but not allocable
+   PC, SP, SR, CG]>
 {
   let MethodProtos = [{
     iterator allocation_order_end(const MachineFunction &MF) const;
@@ -49,8 +51,14 @@
   let MethodBodies = [{
     MSP430RegsClass::iterator
     MSP430RegsClass::allocation_order_end(const MachineFunction &MF) const {
-      // The last 4 registers on the list above are reserved
-      return end()-4;
+      const TargetMachine &TM = MF.getTarget();
+      const TargetRegisterInfo *RI = TM.getRegisterInfo();
+      // Depending on whether the function uses frame pointer or not, last 5 or 4
+      // registers on the list above are reserved
+      if (RI->hasFP(MF))
+        return end()-5;
+      else
+        return end()-4;
     }
   }];
 }