[llvm-commits] [llvm] r70511 - /llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp

[Jakob Stoklund Olesen]

Author: stoklund
Date: Thu Apr 30 16:22:44 2009
New Revision: 70511

URL: http://llvm.org/viewvc/llvm-project?rev=70511&view=rev
Log:
Slightly change TableGen's definition of a register subclass.

A subclass is allowed to have a larger spill size than the superclass, and the
spill alignment must be a multiple of the superclass alignment. This causes
the following new subclass relations:

=== Alpha ===
F4RC -> F8RC

=== PPC ===
F4RC -> F8RC

=== SPU ===
R8C -> R16C -> R32C/R32FP -> R64C/R64FP -> GPRC/VECREG

=== X86 ===
FR32  -> FR64  -> VR128
RFP32 -> RFP64 -> RFP80

These subclass relations are consistent with the behaviour of -join-cross-class-copies.

Modified:
    llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp

Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=70511&r1=70510&r2=70511&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Thu Apr 30 16:22:44 2009
@@ -340,8 +340,21 @@
       bool Empty = true;
       for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
         const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
+
+        // RC2 is a sub-class of RC if it is a valid replacement for any
+        // instruction operand where an RC register is required. It must satisfy
+        // these conditions:
+        //
+        // 1. All RC2 registers are also in RC.
+        // 2. The RC2 spill size must not be smaller that the RC spill size.
+        // 3. RC2 spill alignment must be compatible with RC.
+        //
+        // Sub-classes are used to determine if a virtual register can be used
+        // as an instruction operand, or if it must be copied first.
+
         if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() ||
-            RC.SpillSize != RC2.SpillSize || !isSubRegisterClass(RC2, RegSet))
+            (RC.SpillAlignment && RC2.SpillAlignment % RC.SpillAlignment) ||
+            RC.SpillSize > RC2.SpillSize || !isSubRegisterClass(RC2, RegSet))
           continue;
       
         if (!Empty) OS << ", ";